xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/amlogic/meson-s4.dtsi (revision bf386f26)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	firmware {
		sm: secure-monitor {
			compatible = "amlogic,meson-gxbb-sm";

			pwrc: power-controller {
				compatible = "amlogic,meson-s4-pwrc";
				#power-domain-cells = <1>;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x2000>,
			      <0x0 0xfff04000 0 0x2000>,
			      <0x0 0xfff06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb4: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,meson-s4-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4000 {
					reg = <0x0 0x4000 0x0 0x004c>,
					      <0x0 0x40c0 0x0 0x0220>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 82>;
				};
			};

			gpio_intc: interrupt-controller@4080 {
				compatible = "amlogic,meson-s4-gpio-intc",
					     "amlogic,meson-gpio-intc";
				reg = <0x0 0x4080 0x0 0x20>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
					<10 11 12 13 14 15 16 17 18 19 20 21>;
			};

			uart_b: serial@7a000 {
				compatible = "amlogic,meson-s4-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x7a000 0x0 0x18>;
				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			reset: reset-controller@2000 {
				compatible = "amlogic,meson-s4-reset";
				reg = <0x0 0x2000 0x0 0x98>;
				#reset-cells = <1>;
			};
		};
	};
};