1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gxl.dtsi"
8
9/ {
10	compatible = "amlogic,meson-gxm";
11
12	cpus {
13		cpu-map {
14			cluster0 {
15				core0 {
16					cpu = <&cpu0>;
17				};
18				core1 {
19					cpu = <&cpu1>;
20				};
21				core2 {
22					cpu = <&cpu2>;
23				};
24				core3 {
25					cpu = <&cpu3>;
26				};
27			};
28
29			cluster1 {
30				core0 {
31					cpu = <&cpu4>;
32				};
33				core1 {
34					cpu = <&cpu5>;
35				};
36				core2 {
37					cpu = <&cpu6>;
38				};
39				core3 {
40					cpu = <&cpu7>;
41				};
42			};
43		};
44
45		cpu4: cpu@100 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53";
48			reg = <0x0 0x100>;
49			enable-method = "psci";
50			next-level-cache = <&l2>;
51			clocks = <&scpi_dvfs 1>;
52		};
53
54		cpu5: cpu@101 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x0 0x101>;
58			enable-method = "psci";
59			next-level-cache = <&l2>;
60			clocks = <&scpi_dvfs 1>;
61		};
62
63		cpu6: cpu@102 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x0 0x102>;
67			enable-method = "psci";
68			next-level-cache = <&l2>;
69			clocks = <&scpi_dvfs 1>;
70		};
71
72		cpu7: cpu@103 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			reg = <0x0 0x103>;
76			enable-method = "psci";
77			next-level-cache = <&l2>;
78			clocks = <&scpi_dvfs 1>;
79		};
80	};
81};
82
83&apb {
84	usb2_phy2: phy@78040 {
85		compatible = "amlogic,meson-gxl-usb2-phy";
86		#phy-cells = <0>;
87		reg = <0x0 0x78040 0x0 0x20>;
88		clocks = <&clkc CLKID_USB>;
89		clock-names = "phy";
90		resets = <&reset RESET_USB_OTG>;
91		reset-names = "phy";
92		status = "okay";
93	};
94
95	mali: gpu@c0000 {
96		compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
97		reg = <0x0 0xc0000 0x0 0x40000>;
98		interrupt-parent = <&gic>;
99		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
100			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
101			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
102		interrupt-names = "gpu", "mmu", "job";
103		clocks = <&clkc CLKID_MALI>;
104		resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
105
106		/*
107		 * Mali clocking is provided by two identical clock paths
108		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
109		 * free mux to safely change frequency while running.
110		 */
111		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
112				  <&clkc CLKID_MALI_0>,
113				  <&clkc CLKID_MALI>; /* Glitch free mux */
114		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
115					 <0>, /* Do Nothing */
116					 <&clkc CLKID_MALI_0>;
117		assigned-clock-rates = <0>, /* Do Nothing */
118				       <666666666>,
119				       <0>; /* Do Nothing */
120	};
121};
122
123&clkc_AO {
124	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
125};
126
127&saradc {
128	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
129};
130
131&scpi_dvfs {
132	clock-indices = <0 1>;
133	clock-output-names = "vbig", "vlittle";
134};
135
136&vpu {
137	compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
138};
139
140&hdmi_tx {
141	compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
142};
143
144&dwc3 {
145	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
146};
147