1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb: usb@d0078080 {
18			compatible = "amlogic,meson-gxl-usb-ctrl";
19			reg = <0x0 0xd0078080 0x0 0x20>;
20			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
21			#address-cells = <2>;
22			#size-cells = <2>;
23			ranges;
24
25			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26			clock-names = "usb_ctrl", "ddr";
27			resets = <&reset RESET_USB_OTG>;
28
29			dr_mode = "otg";
30
31			phys = <&usb2_phy0>, <&usb2_phy1>;
32			phy-names = "usb2-phy0", "usb2-phy1";
33
34			dwc2: usb@c9100000 {
35				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36				reg = <0x0 0xc9100000 0x0 0x40000>;
37				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38				clocks = <&clkc CLKID_USB1>;
39				clock-names = "otg";
40				phys = <&usb2_phy1>;
41				dr_mode = "peripheral";
42				g-rx-fifo-size = <192>;
43				g-np-tx-fifo-size = <128>;
44				g-tx-fifo-size = <128 128 16 16 16>;
45			};
46
47			dwc3: usb@c9000000 {
48				compatible = "snps,dwc3";
49				reg = <0x0 0xc9000000 0x0 0x100000>;
50				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51				dr_mode = "host";
52				maximum-speed = "high-speed";
53				snps,dis_u2_susphy_quirk;
54			};
55		};
56
57		acodec: audio-controller@c8832000 {
58			compatible = "amlogic,t9015";
59			reg = <0x0 0xc8832000 0x0 0x14>;
60			#sound-dai-cells = <0>;
61			sound-name-prefix = "ACODEC";
62			clocks = <&clkc CLKID_ACODEC>;
63			clock-names = "pclk";
64			resets = <&reset RESET_ACODEC>;
65			status = "disabled";
66		};
67
68		crypto: crypto@c883e000 {
69			compatible = "amlogic,gxl-crypto";
70			reg = <0x0 0xc883e000 0x0 0x36>;
71			interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73			clocks = <&clkc CLKID_BLKMV>;
74			clock-names = "blkmv";
75			status = "okay";
76		};
77	};
78};
79
80&aiu {
81	compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82	clocks = <&clkc CLKID_AIU_GLUE>,
83		 <&clkc CLKID_I2S_OUT>,
84		 <&clkc CLKID_AOCLK_GATE>,
85		 <&clkc CLKID_CTS_AMCLK>,
86		 <&clkc CLKID_MIXER_IFACE>,
87		 <&clkc CLKID_IEC958>,
88		 <&clkc CLKID_IEC958_GATE>,
89		 <&clkc CLKID_CTS_MCLK_I958>,
90		 <&clkc CLKID_CTS_I958>;
91	clock-names = "pclk",
92		      "i2s_pclk",
93		      "i2s_aoclk",
94		      "i2s_mclk",
95		      "i2s_mixer",
96		      "spdif_pclk",
97		      "spdif_aoclk",
98		      "spdif_mclk",
99		      "spdif_mclk_sel";
100	resets = <&reset RESET_AIU>;
101};
102
103&apb {
104	usb2_phy0: phy@78000 {
105		compatible = "amlogic,meson-gxl-usb2-phy";
106		#phy-cells = <0>;
107		reg = <0x0 0x78000 0x0 0x20>;
108		clocks = <&clkc CLKID_USB>;
109		clock-names = "phy";
110		resets = <&reset RESET_USB_OTG>;
111		reset-names = "phy";
112		status = "okay";
113	};
114
115	usb2_phy1: phy@78020 {
116		compatible = "amlogic,meson-gxl-usb2-phy";
117		#phy-cells = <0>;
118		reg = <0x0 0x78020 0x0 0x20>;
119		clocks = <&clkc CLKID_USB>;
120		clock-names = "phy";
121		resets = <&reset RESET_USB_OTG>;
122		reset-names = "phy";
123		status = "okay";
124	};
125};
126
127&efuse {
128	clocks = <&clkc CLKID_EFUSE>;
129};
130
131&ethmac {
132	clocks = <&clkc CLKID_ETH>,
133		 <&clkc CLKID_FCLK_DIV2>,
134		 <&clkc CLKID_MPLL2>,
135		 <&clkc CLKID_FCLK_DIV2>;
136	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
137
138	mdio0: mdio {
139		#address-cells = <1>;
140		#size-cells = <0>;
141		compatible = "snps,dwmac-mdio";
142	};
143};
144
145&aobus {
146	pinctrl_aobus: pinctrl@14 {
147		compatible = "amlogic,meson-gxl-aobus-pinctrl";
148		#address-cells = <2>;
149		#size-cells = <2>;
150		ranges;
151
152		gpio_ao: bank@14 {
153			reg = <0x0 0x00014 0x0 0x8>,
154			      <0x0 0x0002c 0x0 0x4>,
155			      <0x0 0x00024 0x0 0x8>;
156			reg-names = "mux", "pull", "gpio";
157			gpio-controller;
158			#gpio-cells = <2>;
159			gpio-ranges = <&pinctrl_aobus 0 0 14>;
160		};
161
162		uart_ao_a_pins: uart_ao_a {
163			mux {
164				groups = "uart_tx_ao_a", "uart_rx_ao_a";
165				function = "uart_ao";
166				bias-disable;
167			};
168		};
169
170		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171			mux {
172				groups = "uart_cts_ao_a",
173				       "uart_rts_ao_a";
174				function = "uart_ao";
175				bias-disable;
176			};
177		};
178
179		uart_ao_b_pins: uart_ao_b {
180			mux {
181				groups = "uart_tx_ao_b", "uart_rx_ao_b";
182				function = "uart_ao_b";
183				bias-disable;
184			};
185		};
186
187		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188			mux {
189				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190				function = "uart_ao_b";
191				bias-disable;
192			};
193		};
194
195		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196			mux {
197				groups = "uart_cts_ao_b",
198				       "uart_rts_ao_b";
199				function = "uart_ao_b";
200				bias-disable;
201			};
202		};
203
204		remote_input_ao_pins: remote_input_ao {
205			mux {
206				groups = "remote_input_ao";
207				function = "remote_input_ao";
208				bias-disable;
209			};
210		};
211
212		i2c_ao_pins: i2c_ao {
213			mux {
214				groups = "i2c_sck_ao",
215				       "i2c_sda_ao";
216				function = "i2c_ao";
217				bias-disable;
218			};
219		};
220
221		pwm_ao_a_3_pins: pwm_ao_a_3 {
222			mux {
223				groups = "pwm_ao_a_3";
224				function = "pwm_ao_a";
225				bias-disable;
226			};
227		};
228
229		pwm_ao_a_8_pins: pwm_ao_a_8 {
230			mux {
231				groups = "pwm_ao_a_8";
232				function = "pwm_ao_a";
233				bias-disable;
234			};
235		};
236
237		pwm_ao_b_pins: pwm_ao_b {
238			mux {
239				groups = "pwm_ao_b";
240				function = "pwm_ao_b";
241				bias-disable;
242			};
243		};
244
245		pwm_ao_b_6_pins: pwm_ao_b_6 {
246			mux {
247				groups = "pwm_ao_b_6";
248				function = "pwm_ao_b";
249				bias-disable;
250			};
251		};
252
253		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254			mux {
255				groups = "i2s_out_ch23_ao";
256				function = "i2s_out_ao";
257				bias-disable;
258			};
259		};
260
261		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262			mux {
263				groups = "i2s_out_ch45_ao";
264				function = "i2s_out_ao";
265				bias-disable;
266			};
267		};
268
269		spdif_out_ao_6_pins: spdif_out_ao_6 {
270			mux {
271				groups = "spdif_out_ao_6";
272				function = "spdif_out_ao";
273				bias-disable;
274			};
275		};
276
277		spdif_out_ao_9_pins: spdif_out_ao_9 {
278			mux {
279				groups = "spdif_out_ao_9";
280				function = "spdif_out_ao";
281				bias-disable;
282			};
283		};
284
285		ao_cec_pins: ao_cec {
286			mux {
287				groups = "ao_cec";
288				function = "cec_ao";
289				bias-disable;
290			};
291		};
292
293		ee_cec_pins: ee_cec {
294			mux {
295				groups = "ee_cec";
296				function = "cec_ao";
297				bias-disable;
298			};
299		};
300	};
301};
302
303&cec_AO {
304	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305	clock-names = "core";
306};
307
308&clkc_AO {
309	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310	clocks = <&xtal>, <&clkc CLKID_CLK81>;
311	clock-names = "xtal", "mpeg-clk";
312};
313
314&gpio_intc {
315	compatible = "amlogic,meson-gxl-gpio-intc",
316		     "amlogic,meson-gpio-intc";
317	status = "okay";
318};
319
320&hdmi_tx {
321	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322	resets = <&reset RESET_HDMITX_CAPB3>,
323		 <&reset RESET_HDMI_SYSTEM_RESET>,
324		 <&reset RESET_HDMI_TX>;
325	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326	clocks = <&clkc CLKID_HDMI>,
327		 <&clkc CLKID_HDMI_PCLK>,
328		 <&clkc CLKID_GCLK_VENCI_INT0>;
329	clock-names = "isfr", "iahb", "venci";
330	power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
331};
332
333&sysctrl {
334	clkc: clock-controller {
335		compatible = "amlogic,gxl-clkc";
336		#clock-cells = <1>;
337		clocks = <&xtal>;
338		clock-names = "xtal";
339	};
340};
341
342&hwrng {
343	clocks = <&clkc CLKID_RNG0>;
344	clock-names = "core";
345};
346
347&i2c_A {
348	clocks = <&clkc CLKID_I2C>;
349};
350
351&i2c_AO {
352	clocks = <&clkc CLKID_AO_I2C>;
353};
354
355&i2c_B {
356	clocks = <&clkc CLKID_I2C>;
357};
358
359&i2c_C {
360	clocks = <&clkc CLKID_I2C>;
361};
362
363&periphs {
364	pinctrl_periphs: pinctrl@4b0 {
365		compatible = "amlogic,meson-gxl-periphs-pinctrl";
366		#address-cells = <2>;
367		#size-cells = <2>;
368		ranges;
369
370		gpio: bank@4b0 {
371			reg = <0x0 0x004b0 0x0 0x28>,
372			      <0x0 0x004e8 0x0 0x14>,
373			      <0x0 0x00520 0x0 0x14>,
374			      <0x0 0x00430 0x0 0x40>;
375			reg-names = "mux", "pull", "pull-enable", "gpio";
376			gpio-controller;
377			#gpio-cells = <2>;
378			gpio-ranges = <&pinctrl_periphs 0 0 100>;
379		};
380
381		emmc_pins: emmc {
382			mux-0 {
383				groups = "emmc_nand_d07",
384				       "emmc_cmd";
385				function = "emmc";
386				bias-pull-up;
387			};
388
389			mux-1 {
390				groups = "emmc_clk";
391				function = "emmc";
392				bias-disable;
393			};
394		};
395
396		emmc_ds_pins: emmc-ds {
397			mux {
398				groups = "emmc_ds";
399				function = "emmc";
400				bias-pull-down;
401			};
402		};
403
404		emmc_clk_gate_pins: emmc_clk_gate {
405			mux {
406				groups = "BOOT_8";
407				function = "gpio_periphs";
408				bias-pull-down;
409			};
410		};
411
412		nor_pins: nor {
413			mux {
414				groups = "nor_d",
415				       "nor_q",
416				       "nor_c",
417				       "nor_cs";
418				function = "nor";
419				bias-disable;
420			};
421		};
422
423		spi_pins: spi-pins {
424			mux {
425				groups = "spi_miso",
426					"spi_mosi",
427					"spi_sclk";
428				function = "spi";
429				bias-disable;
430			};
431		};
432
433		spi_idle_high_pins: spi-idle-high-pins {
434			mux {
435				groups = "spi_sclk";
436				bias-pull-up;
437			};
438		};
439
440		spi_idle_low_pins: spi-idle-low-pins {
441			mux {
442				groups = "spi_sclk";
443				bias-pull-down;
444			};
445		};
446
447		spi_ss0_pins: spi-ss0 {
448			mux {
449				groups = "spi_ss0";
450				function = "spi";
451				bias-disable;
452			};
453		};
454
455		sdcard_pins: sdcard {
456			mux-0 {
457				groups = "sdcard_d0",
458				       "sdcard_d1",
459				       "sdcard_d2",
460				       "sdcard_d3",
461				       "sdcard_cmd";
462				function = "sdcard";
463				bias-pull-up;
464			};
465
466			mux-1 {
467				groups = "sdcard_clk";
468				function = "sdcard";
469				bias-disable;
470			};
471		};
472
473		sdcard_clk_gate_pins: sdcard_clk_gate {
474			mux {
475				groups = "CARD_2";
476				function = "gpio_periphs";
477				bias-pull-down;
478			};
479		};
480
481		sdio_pins: sdio {
482			mux-0 {
483				groups = "sdio_d0",
484				       "sdio_d1",
485				       "sdio_d2",
486				       "sdio_d3",
487				       "sdio_cmd";
488				function = "sdio";
489				bias-pull-up;
490			};
491
492			mux-1 {
493				groups = "sdio_clk";
494				function = "sdio";
495				bias-disable;
496			};
497		};
498
499		sdio_clk_gate_pins: sdio_clk_gate {
500			mux {
501				groups = "GPIOX_4";
502				function = "gpio_periphs";
503				bias-pull-down;
504			};
505		};
506
507		sdio_irq_pins: sdio_irq {
508			mux {
509				groups = "sdio_irq";
510				function = "sdio";
511				bias-disable;
512			};
513		};
514
515		uart_a_pins: uart_a {
516			mux {
517				groups = "uart_tx_a",
518				       "uart_rx_a";
519				function = "uart_a";
520				bias-disable;
521			};
522		};
523
524		uart_a_cts_rts_pins: uart_a_cts_rts {
525			mux {
526				groups = "uart_cts_a",
527				       "uart_rts_a";
528				function = "uart_a";
529				bias-disable;
530			};
531		};
532
533		uart_b_pins: uart_b {
534			mux {
535				groups = "uart_tx_b",
536				       "uart_rx_b";
537				function = "uart_b";
538				bias-disable;
539			};
540		};
541
542		uart_b_cts_rts_pins: uart_b_cts_rts {
543			mux {
544				groups = "uart_cts_b",
545				       "uart_rts_b";
546				function = "uart_b";
547				bias-disable;
548			};
549		};
550
551		uart_c_pins: uart_c {
552			mux {
553				groups = "uart_tx_c",
554				       "uart_rx_c";
555				function = "uart_c";
556				bias-disable;
557			};
558		};
559
560		uart_c_cts_rts_pins: uart_c_cts_rts {
561			mux {
562				groups = "uart_cts_c",
563				       "uart_rts_c";
564				function = "uart_c";
565				bias-disable;
566			};
567		};
568
569		i2c_a_pins: i2c_a {
570			mux {
571				groups = "i2c_sck_a",
572				     "i2c_sda_a";
573				function = "i2c_a";
574				bias-disable;
575			};
576		};
577
578		i2c_b_pins: i2c_b {
579			mux {
580				groups = "i2c_sck_b",
581				      "i2c_sda_b";
582				function = "i2c_b";
583				bias-disable;
584			};
585		};
586
587		i2c_c_pins: i2c_c {
588			mux {
589				groups = "i2c_sck_c",
590				      "i2c_sda_c";
591				function = "i2c_c";
592				bias-disable;
593			};
594		};
595
596		i2c_c_dv18_pins: i2c_c_dv18 {
597			mux {
598				groups = "i2c_sck_c_dv19",
599				      "i2c_sda_c_dv18";
600				function = "i2c_c";
601				bias-disable;
602			};
603		};
604
605		eth_pins: eth_c {
606			mux {
607				groups = "eth_mdio",
608				       "eth_mdc",
609				       "eth_clk_rx_clk",
610				       "eth_rx_dv",
611				       "eth_rxd0",
612				       "eth_rxd1",
613				       "eth_rxd2",
614				       "eth_rxd3",
615				       "eth_rgmii_tx_clk",
616				       "eth_tx_en",
617				       "eth_txd0",
618				       "eth_txd1",
619				       "eth_txd2",
620				       "eth_txd3";
621				function = "eth";
622				bias-disable;
623			};
624		};
625
626		eth_link_led_pins: eth_link_led {
627			mux {
628				groups = "eth_link_led";
629				function = "eth_led";
630				bias-disable;
631			};
632		};
633
634		eth_act_led_pins: eth_act_led {
635			mux {
636				groups = "eth_act_led";
637				function = "eth_led";
638			};
639		};
640
641		pwm_a_pins: pwm_a {
642			mux {
643				groups = "pwm_a";
644				function = "pwm_a";
645				bias-disable;
646			};
647		};
648
649		pwm_b_pins: pwm_b {
650			mux {
651				groups = "pwm_b";
652				function = "pwm_b";
653				bias-disable;
654			};
655		};
656
657		pwm_c_pins: pwm_c {
658			mux {
659				groups = "pwm_c";
660				function = "pwm_c";
661				bias-disable;
662			};
663		};
664
665		pwm_d_pins: pwm_d {
666			mux {
667				groups = "pwm_d";
668				function = "pwm_d";
669				bias-disable;
670			};
671		};
672
673		pwm_e_pins: pwm_e {
674			mux {
675				groups = "pwm_e";
676				function = "pwm_e";
677				bias-disable;
678			};
679		};
680
681		pwm_f_clk_pins: pwm_f_clk {
682			mux {
683				groups = "pwm_f_clk";
684				function = "pwm_f";
685				bias-disable;
686			};
687		};
688
689		pwm_f_x_pins: pwm_f_x {
690			mux {
691				groups = "pwm_f_x";
692				function = "pwm_f";
693				bias-disable;
694			};
695		};
696
697		hdmi_hpd_pins: hdmi_hpd {
698			mux {
699				groups = "hdmi_hpd";
700				function = "hdmi_hpd";
701				bias-disable;
702			};
703		};
704
705		hdmi_i2c_pins: hdmi_i2c {
706			mux {
707				groups = "hdmi_sda", "hdmi_scl";
708				function = "hdmi_i2c";
709				bias-disable;
710			};
711		};
712
713		i2s_am_clk_pins: i2s_am_clk {
714			mux {
715				groups = "i2s_am_clk";
716				function = "i2s_out";
717				bias-disable;
718			};
719		};
720
721		i2s_out_ao_clk_pins: i2s_out_ao_clk {
722			mux {
723				groups = "i2s_out_ao_clk";
724				function = "i2s_out";
725				bias-disable;
726			};
727		};
728
729		i2s_out_lr_clk_pins: i2s_out_lr_clk {
730			mux {
731				groups = "i2s_out_lr_clk";
732				function = "i2s_out";
733				bias-disable;
734			};
735		};
736
737		i2s_out_ch01_pins: i2s_out_ch01 {
738			mux {
739				groups = "i2s_out_ch01";
740				function = "i2s_out";
741				bias-disable;
742			};
743		};
744		i2sout_ch23_z_pins: i2sout_ch23_z {
745			mux {
746				groups = "i2sout_ch23_z";
747				function = "i2s_out";
748				bias-disable;
749			};
750		};
751
752		i2sout_ch45_z_pins: i2sout_ch45_z {
753			mux {
754				groups = "i2sout_ch45_z";
755				function = "i2s_out";
756				bias-disable;
757			};
758		};
759
760		i2sout_ch67_z_pins: i2sout_ch67_z {
761			mux {
762				groups = "i2sout_ch67_z";
763				function = "i2s_out";
764				bias-disable;
765			};
766		};
767
768		spdif_out_h_pins: spdif_out_ao_h {
769			mux {
770				groups = "spdif_out_h";
771				function = "spdif_out";
772				bias-disable;
773			};
774		};
775	};
776
777	eth_phy_mux: mdio@558 {
778		reg = <0x0 0x558 0x0 0xc>;
779		compatible = "amlogic,gxl-mdio-mux";
780		#address-cells = <1>;
781		#size-cells = <0>;
782		clocks = <&clkc CLKID_FCLK_DIV4>;
783		clock-names = "ref";
784		mdio-parent-bus = <&mdio0>;
785
786		external_mdio: mdio@0 {
787			reg = <0x0>;
788			#address-cells = <1>;
789			#size-cells = <0>;
790		};
791
792		internal_mdio: mdio@1 {
793			reg = <0x1>;
794			#address-cells = <1>;
795			#size-cells = <0>;
796
797			internal_phy: ethernet-phy@8 {
798				compatible = "ethernet-phy-id0181.4400";
799				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
800				reg = <8>;
801				max-speed = <100>;
802			};
803		};
804	};
805};
806
807&pwrc {
808	resets = <&reset RESET_VIU>,
809		 <&reset RESET_VENC>,
810		 <&reset RESET_VCBUS>,
811		 <&reset RESET_BT656>,
812		 <&reset RESET_DVIN_RESET>,
813		 <&reset RESET_RDMA>,
814		 <&reset RESET_VENCI>,
815		 <&reset RESET_VENCP>,
816		 <&reset RESET_VDAC>,
817		 <&reset RESET_VDI6>,
818		 <&reset RESET_VENCL>,
819		 <&reset RESET_VID_LOCK>;
820	reset-names = "viu", "venc", "vcbus", "bt656",
821		      "dvin", "rdma", "venci", "vencp",
822		      "vdac", "vdi6", "vencl", "vid_lock";
823	clocks = <&clkc CLKID_VPU>,
824	         <&clkc CLKID_VAPB>;
825	clock-names = "vpu", "vapb";
826	/*
827	 * VPU clocking is provided by two identical clock paths
828	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
829	 * free mux to safely change frequency while running.
830	 * Same for VAPB but with a final gate after the glitch free mux.
831	 */
832	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
833			  <&clkc CLKID_VPU_0>,
834			  <&clkc CLKID_VPU>, /* Glitch free mux */
835			  <&clkc CLKID_VAPB_0_SEL>,
836			  <&clkc CLKID_VAPB_0>,
837			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
838	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
839				 <0>, /* Do Nothing */
840				 <&clkc CLKID_VPU_0>,
841				 <&clkc CLKID_FCLK_DIV4>,
842				 <0>, /* Do Nothing */
843				 <&clkc CLKID_VAPB_0>;
844	assigned-clock-rates = <0>, /* Do Nothing */
845			       <666666666>,
846			       <0>, /* Do Nothing */
847			       <0>, /* Do Nothing */
848			       <250000000>,
849			       <0>; /* Do Nothing */
850};
851
852&saradc {
853	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
854	clocks = <&xtal>,
855		 <&clkc CLKID_SAR_ADC>,
856		 <&clkc CLKID_SAR_ADC_CLK>,
857		 <&clkc CLKID_SAR_ADC_SEL>;
858	clock-names = "clkin", "core", "adc_clk", "adc_sel";
859};
860
861&sd_emmc_a {
862	clocks = <&clkc CLKID_SD_EMMC_A>,
863		 <&clkc CLKID_SD_EMMC_A_CLK0>,
864		 <&clkc CLKID_FCLK_DIV2>;
865	clock-names = "core", "clkin0", "clkin1";
866	resets = <&reset RESET_SD_EMMC_A>;
867};
868
869&sd_emmc_b {
870	clocks = <&clkc CLKID_SD_EMMC_B>,
871		 <&clkc CLKID_SD_EMMC_B_CLK0>,
872		 <&clkc CLKID_FCLK_DIV2>;
873	clock-names = "core", "clkin0", "clkin1";
874	resets = <&reset RESET_SD_EMMC_B>;
875};
876
877&sd_emmc_c {
878	clocks = <&clkc CLKID_SD_EMMC_C>,
879		 <&clkc CLKID_SD_EMMC_C_CLK0>,
880		 <&clkc CLKID_FCLK_DIV2>;
881	clock-names = "core", "clkin0", "clkin1";
882	resets = <&reset RESET_SD_EMMC_C>;
883};
884
885&simplefb_hdmi {
886	clocks = <&clkc CLKID_HDMI_PCLK>,
887		 <&clkc CLKID_CLK81>,
888		 <&clkc CLKID_GCLK_VENCI_INT0>;
889};
890
891&spicc {
892	clocks = <&clkc CLKID_SPICC>;
893	clock-names = "core";
894	resets = <&reset RESET_PERIPHS_SPICC>;
895	num-cs = <1>;
896};
897
898&spifc {
899	clocks = <&clkc CLKID_SPI>;
900};
901
902&uart_A {
903	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
904	clock-names = "xtal", "pclk", "baud";
905};
906
907&uart_AO {
908	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
909	clock-names = "xtal", "pclk", "baud";
910};
911
912&uart_AO_B {
913	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
914	clock-names = "xtal", "pclk", "baud";
915};
916
917&uart_B {
918	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
919	clock-names = "xtal", "pclk", "baud";
920};
921
922&uart_C {
923	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
924	clock-names = "xtal", "pclk", "baud";
925};
926
927&vpu {
928	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
929	power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
930};
931
932&vdec {
933	compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
934	clocks = <&clkc CLKID_DOS_PARSER>,
935		 <&clkc CLKID_DOS>,
936		 <&clkc CLKID_VDEC_1>,
937		 <&clkc CLKID_VDEC_HEVC>;
938	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
939	resets = <&reset RESET_PARSER>;
940	reset-names = "esparser";
941};
942