1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47
48/ {
49	compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53	reg = <0x0 0xc9410000 0x0 0x10000
54	       0x0 0xc8834540 0x0 0x4>;
55
56	clocks = <&clkc CLKID_ETH>,
57		 <&clkc CLKID_FCLK_DIV2>,
58		 <&clkc CLKID_MPLL2>;
59	clock-names = "stmmaceth", "clkin0", "clkin1";
60
61	mdio0: mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		compatible = "snps,dwmac-mdio";
65	};
66};
67
68&aobus {
69	pinctrl_aobus: pinctrl@14 {
70		compatible = "amlogic,meson-gxl-aobus-pinctrl";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gpio_ao: bank@14 {
76			reg = <0x0 0x00014 0x0 0x8>,
77			      <0x0 0x0002c 0x0 0x4>,
78			      <0x0 0x00024 0x0 0x8>;
79			reg-names = "mux", "pull", "gpio";
80			gpio-controller;
81			#gpio-cells = <2>;
82		};
83
84		uart_ao_a_pins: uart_ao_a {
85			mux {
86				groups = "uart_tx_ao_a", "uart_rx_ao_a";
87				function = "uart_ao";
88			};
89		};
90
91		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
92			mux {
93				groups = "uart_cts_ao_a",
94				       "uart_rts_ao_a";
95				function = "uart_ao";
96			};
97		};
98
99		uart_ao_b_pins: uart_ao_b {
100			mux {
101				groups = "uart_tx_ao_b", "uart_rx_ao_b";
102				function = "uart_ao_b";
103			};
104		};
105
106		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
107			mux {
108				groups = "uart_cts_ao_b",
109				       "uart_rts_ao_b";
110				function = "uart_ao_b";
111			};
112		};
113
114		remote_input_ao_pins: remote_input_ao {
115			mux {
116				groups = "remote_input_ao";
117				function = "remote_input_ao";
118			};
119		};
120
121		pwm_ao_a_3_pins: pwm_ao_a_3 {
122			mux {
123				groups = "pwm_ao_a_3";
124				function = "pwm_ao_a";
125			};
126		};
127
128		pwm_ao_a_8_pins: pwm_ao_a_8 {
129			mux {
130				groups = "pwm_ao_a_8";
131				function = "pwm_ao_a";
132			};
133		};
134
135		pwm_ao_b_pins: pwm_ao_b {
136			mux {
137				groups = "pwm_ao_b";
138				function = "pwm_ao_b";
139			};
140		};
141	};
142};
143
144&periphs {
145	pinctrl_periphs: pinctrl@4b0 {
146		compatible = "amlogic,meson-gxl-periphs-pinctrl";
147		#address-cells = <2>;
148		#size-cells = <2>;
149		ranges;
150
151		gpio: bank@4b0 {
152			reg = <0x0 0x004b0 0x0 0x28>,
153			      <0x0 0x004e8 0x0 0x14>,
154			      <0x0 0x00120 0x0 0x14>,
155			      <0x0 0x00430 0x0 0x40>;
156			reg-names = "mux", "pull", "pull-enable", "gpio";
157			gpio-controller;
158			#gpio-cells = <2>;
159		};
160
161		emmc_pins: emmc {
162			mux {
163				groups = "emmc_nand_d07",
164				       "emmc_cmd",
165				       "emmc_clk",
166				       "emmc_ds";
167				function = "emmc";
168			};
169		};
170
171		sdcard_pins: sdcard {
172			mux {
173				groups = "sdcard_d0",
174				       "sdcard_d1",
175				       "sdcard_d2",
176				       "sdcard_d3",
177				       "sdcard_cmd",
178				       "sdcard_clk";
179				function = "sdcard";
180			};
181		};
182
183		sdio_pins: sdio {
184			mux {
185				groups = "sdio_d0",
186				       "sdio_d1",
187				       "sdio_d2",
188				       "sdio_d3",
189				       "sdio_cmd",
190				       "sdio_clk";
191				function = "sdio";
192			};
193		};
194
195		sdio_irq_pins: sdio_irq {
196			mux {
197				groups = "sdio_irq";
198				function = "sdio";
199			};
200		};
201
202		uart_a_pins: uart_a {
203			mux {
204				groups = "uart_tx_a",
205				       "uart_rx_a";
206				function = "uart_a";
207			};
208		};
209
210		uart_a_cts_rts_pins: uart_a_cts_rts {
211			mux {
212				groups = "uart_cts_a",
213				       "uart_rts_a";
214				function = "uart_a";
215			};
216		};
217
218		uart_b_pins: uart_b {
219			mux {
220				groups = "uart_tx_b",
221				       "uart_rx_b";
222				function = "uart_b";
223			};
224		};
225
226		uart_b_cts_rts_pins: uart_b_cts_rts {
227			mux {
228				groups = "uart_cts_b",
229				       "uart_rts_b";
230				function = "uart_b";
231			};
232		};
233
234		uart_c_pins: uart_c {
235			mux {
236				groups = "uart_tx_c",
237				       "uart_rx_c";
238				function = "uart_c";
239			};
240		};
241
242		uart_c_cts_rts_pins: uart_c_cts_rts {
243			mux {
244				groups = "uart_cts_c",
245				       "uart_rts_c";
246				function = "uart_c";
247			};
248		};
249
250		i2c_a_pins: i2c_a {
251			mux {
252				groups = "i2c_sck_a",
253				     "i2c_sda_a";
254				function = "i2c_a";
255			};
256		};
257
258		i2c_b_pins: i2c_b {
259			mux {
260				groups = "i2c_sck_b",
261				      "i2c_sda_b";
262				function = "i2c_b";
263			};
264		};
265
266		i2c_c_pins: i2c_c {
267			mux {
268				groups = "i2c_sck_c",
269				      "i2c_sda_c";
270				function = "i2c_c";
271			};
272		};
273
274		eth_pins: eth_c {
275			mux {
276				groups = "eth_mdio",
277				       "eth_mdc",
278				       "eth_clk_rx_clk",
279				       "eth_rx_dv",
280				       "eth_rxd0",
281				       "eth_rxd1",
282				       "eth_rxd2",
283				       "eth_rxd3",
284				       "eth_rgmii_tx_clk",
285				       "eth_tx_en",
286				       "eth_txd0",
287				       "eth_txd1",
288				       "eth_txd2",
289				       "eth_txd3";
290				function = "eth";
291			};
292		};
293
294		pwm_a_pins: pwm_a {
295			mux {
296				groups = "pwm_a";
297				function = "pwm_a";
298			};
299		};
300
301		pwm_b_pins: pwm_b {
302			mux {
303				groups = "pwm_b";
304				function = "pwm_b";
305			};
306		};
307
308		pwm_c_pins: pwm_c {
309			mux {
310				groups = "pwm_c";
311				function = "pwm_c";
312			};
313		};
314
315		pwm_d_pins: pwm_d {
316			mux {
317				groups = "pwm_d";
318				function = "pwm_d";
319			};
320		};
321
322		pwm_e_pins: pwm_e {
323			mux {
324				groups = "pwm_e";
325				function = "pwm_e";
326			};
327		};
328
329		pwm_f_clk_pins: pwm_f_clk {
330			mux {
331				groups = "pwm_f_clk";
332				function = "pwm_f";
333			};
334		};
335
336		pwm_f_x_pins: pwm_f_x {
337			mux {
338				groups = "pwm_f_x";
339				function = "pwm_f";
340			};
341		};
342
343		hdmi_hpd_pins: hdmi_hpd {
344			mux {
345				groups = "hdmi_hpd";
346				function = "hdmi_hpd";
347			};
348		};
349
350		hdmi_i2c_pins: hdmi_i2c {
351			mux {
352				groups = "hdmi_sda", "hdmi_scl";
353				function = "hdmi_i2c";
354			};
355		};
356	};
357
358	eth-phy-mux {
359		compatible = "mdio-mux-mmioreg", "mdio-mux";
360		#address-cells = <1>;
361		#size-cells = <0>;
362		reg = <0x0 0x55c 0x0 0x4>;
363		mux-mask = <0xffffffff>;
364		mdio-parent-bus = <&mdio0>;
365
366		internal_mdio: mdio@e40908ff {
367			reg = <0xe40908ff>;
368			#address-cells = <1>;
369			#size-cells = <0>;
370
371			internal_phy: ethernet-phy@8 {
372				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
373				reg = <8>;
374				max-speed = <100>;
375			};
376		};
377
378		external_mdio: mdio@2009087f {
379			reg = <0x2009087f>;
380			#address-cells = <1>;
381			#size-cells = <0>;
382		};
383	};
384};
385
386&hiubus {
387	clkc: clock-controller@0 {
388		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
389		#clock-cells = <1>;
390		reg = <0x0 0x0 0x0 0x3db>;
391	};
392};
393
394&i2c_A {
395	clocks = <&clkc CLKID_I2C>;
396};
397
398&i2c_B {
399	clocks = <&clkc CLKID_I2C>;
400};
401
402&i2c_C {
403	clocks = <&clkc CLKID_I2C>;
404};
405
406&saradc {
407	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
408	clocks = <&xtal>,
409		 <&clkc CLKID_SAR_ADC>,
410		 <&clkc CLKID_SANA>,
411		 <&clkc CLKID_SAR_ADC_CLK>,
412		 <&clkc CLKID_SAR_ADC_SEL>;
413	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
414};
415
416&sd_emmc_a {
417	clocks = <&clkc CLKID_SD_EMMC_A>,
418		 <&xtal>,
419		 <&clkc CLKID_FCLK_DIV2>;
420	clock-names = "core", "clkin0", "clkin1";
421};
422
423&sd_emmc_b {
424	clocks = <&clkc CLKID_SD_EMMC_B>,
425		 <&xtal>,
426		 <&clkc CLKID_FCLK_DIV2>;
427       clock-names = "core", "clkin0", "clkin1";
428};
429
430&sd_emmc_c {
431	clocks = <&clkc CLKID_SD_EMMC_C>,
432		 <&xtal>,
433		 <&clkc CLKID_FCLK_DIV2>;
434	clock-names = "core", "clkin0", "clkin1";
435};
436
437&vpu {
438	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
439};
440