1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47
48/ {
49	compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53	reg = <0x0 0xc9410000 0x0 0x10000
54	       0x0 0xc8834540 0x0 0x4>;
55
56	clocks = <&clkc CLKID_ETH>,
57		 <&clkc CLKID_FCLK_DIV2>,
58		 <&clkc CLKID_MPLL2>;
59	clock-names = "stmmaceth", "clkin0", "clkin1";
60
61	mdio0: mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		compatible = "snps,dwmac-mdio";
65	};
66};
67
68&aobus {
69	pinctrl_aobus: pinctrl@14 {
70		compatible = "amlogic,meson-gxl-aobus-pinctrl";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gpio_ao: bank@14 {
76			reg = <0x0 0x00014 0x0 0x8>,
77			      <0x0 0x0002c 0x0 0x4>,
78			      <0x0 0x00024 0x0 0x8>;
79			reg-names = "mux", "pull", "gpio";
80			gpio-controller;
81			#gpio-cells = <2>;
82			gpio-ranges = <&pinctrl_aobus 0 0 14>;
83		};
84
85		uart_ao_a_pins: uart_ao_a {
86			mux {
87				groups = "uart_tx_ao_a", "uart_rx_ao_a";
88				function = "uart_ao";
89			};
90		};
91
92		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
93			mux {
94				groups = "uart_cts_ao_a",
95				       "uart_rts_ao_a";
96				function = "uart_ao";
97			};
98		};
99
100		uart_ao_b_pins: uart_ao_b {
101			mux {
102				groups = "uart_tx_ao_b", "uart_rx_ao_b";
103				function = "uart_ao_b";
104			};
105		};
106
107		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
108			mux {
109				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
110				function = "uart_ao_b";
111			};
112		};
113
114		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
115			mux {
116				groups = "uart_cts_ao_b",
117				       "uart_rts_ao_b";
118				function = "uart_ao_b";
119			};
120		};
121
122		remote_input_ao_pins: remote_input_ao {
123			mux {
124				groups = "remote_input_ao";
125				function = "remote_input_ao";
126			};
127		};
128
129		i2c_ao_pins: i2c_ao {
130			mux {
131				groups = "i2c_sck_ao",
132				       "i2c_sda_ao";
133				function = "i2c_ao";
134			};
135		};
136
137		pwm_ao_a_3_pins: pwm_ao_a_3 {
138			mux {
139				groups = "pwm_ao_a_3";
140				function = "pwm_ao_a";
141			};
142		};
143
144		pwm_ao_a_8_pins: pwm_ao_a_8 {
145			mux {
146				groups = "pwm_ao_a_8";
147				function = "pwm_ao_a";
148			};
149		};
150
151		pwm_ao_b_pins: pwm_ao_b {
152			mux {
153				groups = "pwm_ao_b";
154				function = "pwm_ao_b";
155			};
156		};
157
158		pwm_ao_b_6_pins: pwm_ao_b_6 {
159			mux {
160				groups = "pwm_ao_b_6";
161				function = "pwm_ao_b";
162			};
163		};
164
165		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
166			mux {
167				groups = "i2s_out_ch23_ao";
168				function = "i2s_out_ao";
169			};
170		};
171
172		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
173			mux {
174				groups = "i2s_out_ch45_ao";
175				function = "i2s_out_ao";
176			};
177		};
178	};
179};
180
181&periphs {
182	pinctrl_periphs: pinctrl@4b0 {
183		compatible = "amlogic,meson-gxl-periphs-pinctrl";
184		#address-cells = <2>;
185		#size-cells = <2>;
186		ranges;
187
188		gpio: bank@4b0 {
189			reg = <0x0 0x004b0 0x0 0x28>,
190			      <0x0 0x004e8 0x0 0x14>,
191			      <0x0 0x00120 0x0 0x14>,
192			      <0x0 0x00430 0x0 0x40>;
193			reg-names = "mux", "pull", "pull-enable", "gpio";
194			gpio-controller;
195			#gpio-cells = <2>;
196			gpio-ranges = <&pinctrl_periphs 0 14 101>;
197		};
198
199		emmc_pins: emmc {
200			mux {
201				groups = "emmc_nand_d07",
202				       "emmc_cmd",
203				       "emmc_clk",
204				       "emmc_ds";
205				function = "emmc";
206			};
207		};
208
209		nor_pins: nor {
210			mux {
211				groups = "nor_d",
212				       "nor_q",
213				       "nor_c",
214				       "nor_cs";
215				function = "nor";
216			};
217		};
218
219		sdcard_pins: sdcard {
220			mux {
221				groups = "sdcard_d0",
222				       "sdcard_d1",
223				       "sdcard_d2",
224				       "sdcard_d3",
225				       "sdcard_cmd",
226				       "sdcard_clk";
227				function = "sdcard";
228			};
229		};
230
231		sdio_pins: sdio {
232			mux {
233				groups = "sdio_d0",
234				       "sdio_d1",
235				       "sdio_d2",
236				       "sdio_d3",
237				       "sdio_cmd",
238				       "sdio_clk";
239				function = "sdio";
240			};
241		};
242
243		sdio_irq_pins: sdio_irq {
244			mux {
245				groups = "sdio_irq";
246				function = "sdio";
247			};
248		};
249
250		uart_a_pins: uart_a {
251			mux {
252				groups = "uart_tx_a",
253				       "uart_rx_a";
254				function = "uart_a";
255			};
256		};
257
258		uart_a_cts_rts_pins: uart_a_cts_rts {
259			mux {
260				groups = "uart_cts_a",
261				       "uart_rts_a";
262				function = "uart_a";
263			};
264		};
265
266		uart_b_pins: uart_b {
267			mux {
268				groups = "uart_tx_b",
269				       "uart_rx_b";
270				function = "uart_b";
271			};
272		};
273
274		uart_b_cts_rts_pins: uart_b_cts_rts {
275			mux {
276				groups = "uart_cts_b",
277				       "uart_rts_b";
278				function = "uart_b";
279			};
280		};
281
282		uart_c_pins: uart_c {
283			mux {
284				groups = "uart_tx_c",
285				       "uart_rx_c";
286				function = "uart_c";
287			};
288		};
289
290		uart_c_cts_rts_pins: uart_c_cts_rts {
291			mux {
292				groups = "uart_cts_c",
293				       "uart_rts_c";
294				function = "uart_c";
295			};
296		};
297
298		i2c_a_pins: i2c_a {
299			mux {
300				groups = "i2c_sck_a",
301				     "i2c_sda_a";
302				function = "i2c_a";
303			};
304		};
305
306		i2c_b_pins: i2c_b {
307			mux {
308				groups = "i2c_sck_b",
309				      "i2c_sda_b";
310				function = "i2c_b";
311			};
312		};
313
314		i2c_c_pins: i2c_c {
315			mux {
316				groups = "i2c_sck_c",
317				      "i2c_sda_c";
318				function = "i2c_c";
319			};
320		};
321
322		eth_pins: eth_c {
323			mux {
324				groups = "eth_mdio",
325				       "eth_mdc",
326				       "eth_clk_rx_clk",
327				       "eth_rx_dv",
328				       "eth_rxd0",
329				       "eth_rxd1",
330				       "eth_rxd2",
331				       "eth_rxd3",
332				       "eth_rgmii_tx_clk",
333				       "eth_tx_en",
334				       "eth_txd0",
335				       "eth_txd1",
336				       "eth_txd2",
337				       "eth_txd3";
338				function = "eth";
339			};
340		};
341
342		pwm_a_pins: pwm_a {
343			mux {
344				groups = "pwm_a";
345				function = "pwm_a";
346			};
347		};
348
349		pwm_b_pins: pwm_b {
350			mux {
351				groups = "pwm_b";
352				function = "pwm_b";
353			};
354		};
355
356		pwm_c_pins: pwm_c {
357			mux {
358				groups = "pwm_c";
359				function = "pwm_c";
360			};
361		};
362
363		pwm_d_pins: pwm_d {
364			mux {
365				groups = "pwm_d";
366				function = "pwm_d";
367			};
368		};
369
370		pwm_e_pins: pwm_e {
371			mux {
372				groups = "pwm_e";
373				function = "pwm_e";
374			};
375		};
376
377		pwm_f_clk_pins: pwm_f_clk {
378			mux {
379				groups = "pwm_f_clk";
380				function = "pwm_f";
381			};
382		};
383
384		pwm_f_x_pins: pwm_f_x {
385			mux {
386				groups = "pwm_f_x";
387				function = "pwm_f";
388			};
389		};
390
391		hdmi_hpd_pins: hdmi_hpd {
392			mux {
393				groups = "hdmi_hpd";
394				function = "hdmi_hpd";
395			};
396		};
397
398		hdmi_i2c_pins: hdmi_i2c {
399			mux {
400				groups = "hdmi_sda", "hdmi_scl";
401				function = "hdmi_i2c";
402			};
403		};
404
405		i2s_am_clk_pins: i2s_am_clk {
406			mux {
407				groups = "i2s_am_clk";
408				function = "i2s_out";
409			};
410		};
411
412		i2s_out_ao_clk_pins: i2s_out_ao_clk {
413			mux {
414				groups = "i2s_out_ao_clk";
415				function = "i2s_out";
416			};
417		};
418
419		i2s_out_lr_clk_pins: i2s_out_lr_clk {
420			mux {
421				groups = "i2s_out_lr_clk";
422				function = "i2s_out";
423			};
424		};
425
426		i2s_out_ch01_pins: i2s_out_ch01 {
427			mux {
428				groups = "i2s_out_ch01";
429				function = "i2s_out";
430			};
431		};
432		i2sout_ch23_z_pins: i2sout_ch23_z {
433			mux {
434				groups = "i2sout_ch23_z";
435				function = "i2s_out";
436			};
437		};
438
439		i2sout_ch45_z_pins: i2sout_ch45_z {
440			mux {
441				groups = "i2sout_ch45_z";
442				function = "i2s_out";
443			};
444		};
445
446		i2sout_ch67_z_pins: i2sout_ch67_z {
447			mux {
448				groups = "i2sout_ch67_z";
449				function = "i2s_out";
450			};
451		};
452	};
453
454	eth-phy-mux {
455		compatible = "mdio-mux-mmioreg", "mdio-mux";
456		#address-cells = <1>;
457		#size-cells = <0>;
458		reg = <0x0 0x55c 0x0 0x4>;
459		mux-mask = <0xffffffff>;
460		mdio-parent-bus = <&mdio0>;
461
462		internal_mdio: mdio@e40908ff {
463			reg = <0xe40908ff>;
464			#address-cells = <1>;
465			#size-cells = <0>;
466
467			internal_phy: ethernet-phy@8 {
468				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
469				reg = <8>;
470				max-speed = <100>;
471			};
472		};
473
474		external_mdio: mdio@2009087f {
475			reg = <0x2009087f>;
476			#address-cells = <1>;
477			#size-cells = <0>;
478		};
479	};
480};
481
482&hiubus {
483	clkc: clock-controller@0 {
484		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
485		#clock-cells = <1>;
486		reg = <0x0 0x0 0x0 0x3db>;
487	};
488};
489
490&i2c_A {
491	clocks = <&clkc CLKID_I2C>;
492};
493
494&i2c_AO {
495	clocks = <&clkc CLKID_AO_I2C>;
496};
497
498&i2c_B {
499	clocks = <&clkc CLKID_I2C>;
500};
501
502&i2c_C {
503	clocks = <&clkc CLKID_I2C>;
504};
505
506&saradc {
507	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
508	clocks = <&xtal>,
509		 <&clkc CLKID_SAR_ADC>,
510		 <&clkc CLKID_SANA>,
511		 <&clkc CLKID_SAR_ADC_CLK>,
512		 <&clkc CLKID_SAR_ADC_SEL>;
513	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
514};
515
516&sd_emmc_a {
517	clocks = <&clkc CLKID_SD_EMMC_A>,
518		 <&xtal>,
519		 <&clkc CLKID_FCLK_DIV2>;
520	clock-names = "core", "clkin0", "clkin1";
521};
522
523&sd_emmc_b {
524	clocks = <&clkc CLKID_SD_EMMC_B>,
525		 <&xtal>,
526		 <&clkc CLKID_FCLK_DIV2>;
527       clock-names = "core", "clkin0", "clkin1";
528};
529
530&sd_emmc_c {
531	clocks = <&clkc CLKID_SD_EMMC_C>,
532		 <&xtal>,
533		 <&clkc CLKID_FCLK_DIV2>;
534	clock-names = "core", "clkin0", "clkin1";
535};
536
537&spifc {
538	clocks = <&clkc CLKID_SPI>;
539};
540
541&vpu {
542	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
543};
544