1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb: usb@d0078080 {
18			compatible = "amlogic,meson-gxl-usb-ctrl";
19			reg = <0x0 0xd0078080 0x0 0x20>;
20			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
21			#address-cells = <2>;
22			#size-cells = <2>;
23			ranges;
24
25			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26			clock-names = "usb_ctrl", "ddr";
27			resets = <&reset RESET_USB_OTG>;
28
29			dr_mode = "otg";
30
31			phys = <&usb2_phy0>, <&usb2_phy1>;
32			phy-names = "usb2-phy0", "usb2-phy1";
33
34			dwc2: usb@c9100000 {
35				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36				reg = <0x0 0xc9100000 0x0 0x40000>;
37				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38				clocks = <&clkc CLKID_USB1>;
39				clock-names = "otg";
40				phys = <&usb2_phy1>;
41				dr_mode = "peripheral";
42				g-rx-fifo-size = <192>;
43				g-np-tx-fifo-size = <128>;
44				g-tx-fifo-size = <128 128 16 16 16>;
45			};
46
47			dwc3: usb@c9000000 {
48				compatible = "snps,dwc3";
49				reg = <0x0 0xc9000000 0x0 0x100000>;
50				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51				dr_mode = "host";
52				maximum-speed = "high-speed";
53				snps,dis_u2_susphy_quirk;
54			};
55		};
56
57		acodec: audio-controller@c8832000 {
58			compatible = "amlogic,t9015";
59			reg = <0x0 0xc8832000 0x0 0x14>;
60			#sound-dai-cells = <0>;
61			sound-name-prefix = "ACODEC";
62			clocks = <&clkc CLKID_ACODEC>;
63			clock-names = "pclk";
64			resets = <&reset RESET_ACODEC>;
65			status = "disabled";
66		};
67
68		crypto: crypto@c883e000 {
69			compatible = "amlogic,gxl-crypto";
70			reg = <0x0 0xc883e000 0x0 0x36>;
71			interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73			clocks = <&clkc CLKID_BLKMV>;
74			clock-names = "blkmv";
75			status = "okay";
76		};
77	};
78};
79
80&aiu {
81	compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82	clocks = <&clkc CLKID_AIU_GLUE>,
83		 <&clkc CLKID_I2S_OUT>,
84		 <&clkc CLKID_AOCLK_GATE>,
85		 <&clkc CLKID_CTS_AMCLK>,
86		 <&clkc CLKID_MIXER_IFACE>,
87		 <&clkc CLKID_IEC958>,
88		 <&clkc CLKID_IEC958_GATE>,
89		 <&clkc CLKID_CTS_MCLK_I958>,
90		 <&clkc CLKID_CTS_I958>;
91	clock-names = "pclk",
92		      "i2s_pclk",
93		      "i2s_aoclk",
94		      "i2s_mclk",
95		      "i2s_mixer",
96		      "spdif_pclk",
97		      "spdif_aoclk",
98		      "spdif_mclk",
99		      "spdif_mclk_sel";
100	resets = <&reset RESET_AIU>;
101};
102
103&apb {
104	usb2_phy0: phy@78000 {
105		compatible = "amlogic,meson-gxl-usb2-phy";
106		#phy-cells = <0>;
107		reg = <0x0 0x78000 0x0 0x20>;
108		clocks = <&clkc CLKID_USB>;
109		clock-names = "phy";
110		resets = <&reset RESET_USB_OTG>;
111		reset-names = "phy";
112		status = "okay";
113	};
114
115	usb2_phy1: phy@78020 {
116		compatible = "amlogic,meson-gxl-usb2-phy";
117		#phy-cells = <0>;
118		reg = <0x0 0x78020 0x0 0x20>;
119		clocks = <&clkc CLKID_USB>;
120		clock-names = "phy";
121		resets = <&reset RESET_USB_OTG>;
122		reset-names = "phy";
123		status = "okay";
124	};
125};
126
127&efuse {
128	clocks = <&clkc CLKID_EFUSE>;
129};
130
131&ethmac {
132	clocks = <&clkc CLKID_ETH>,
133		 <&clkc CLKID_FCLK_DIV2>,
134		 <&clkc CLKID_MPLL2>;
135	clock-names = "stmmaceth", "clkin0", "clkin1";
136
137	mdio0: mdio {
138		#address-cells = <1>;
139		#size-cells = <0>;
140		compatible = "snps,dwmac-mdio";
141	};
142};
143
144&aobus {
145	pinctrl_aobus: pinctrl@14 {
146		compatible = "amlogic,meson-gxl-aobus-pinctrl";
147		#address-cells = <2>;
148		#size-cells = <2>;
149		ranges;
150
151		gpio_ao: bank@14 {
152			reg = <0x0 0x00014 0x0 0x8>,
153			      <0x0 0x0002c 0x0 0x4>,
154			      <0x0 0x00024 0x0 0x8>;
155			reg-names = "mux", "pull", "gpio";
156			gpio-controller;
157			#gpio-cells = <2>;
158			gpio-ranges = <&pinctrl_aobus 0 0 14>;
159		};
160
161		uart_ao_a_pins: uart_ao_a {
162			mux {
163				groups = "uart_tx_ao_a", "uart_rx_ao_a";
164				function = "uart_ao";
165				bias-disable;
166			};
167		};
168
169		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
170			mux {
171				groups = "uart_cts_ao_a",
172				       "uart_rts_ao_a";
173				function = "uart_ao";
174				bias-disable;
175			};
176		};
177
178		uart_ao_b_pins: uart_ao_b {
179			mux {
180				groups = "uart_tx_ao_b", "uart_rx_ao_b";
181				function = "uart_ao_b";
182				bias-disable;
183			};
184		};
185
186		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
187			mux {
188				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
189				function = "uart_ao_b";
190				bias-disable;
191			};
192		};
193
194		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
195			mux {
196				groups = "uart_cts_ao_b",
197				       "uart_rts_ao_b";
198				function = "uart_ao_b";
199				bias-disable;
200			};
201		};
202
203		remote_input_ao_pins: remote_input_ao {
204			mux {
205				groups = "remote_input_ao";
206				function = "remote_input_ao";
207				bias-disable;
208			};
209		};
210
211		i2c_ao_pins: i2c_ao {
212			mux {
213				groups = "i2c_sck_ao",
214				       "i2c_sda_ao";
215				function = "i2c_ao";
216				bias-disable;
217			};
218		};
219
220		pwm_ao_a_3_pins: pwm_ao_a_3 {
221			mux {
222				groups = "pwm_ao_a_3";
223				function = "pwm_ao_a";
224				bias-disable;
225			};
226		};
227
228		pwm_ao_a_8_pins: pwm_ao_a_8 {
229			mux {
230				groups = "pwm_ao_a_8";
231				function = "pwm_ao_a";
232				bias-disable;
233			};
234		};
235
236		pwm_ao_b_pins: pwm_ao_b {
237			mux {
238				groups = "pwm_ao_b";
239				function = "pwm_ao_b";
240				bias-disable;
241			};
242		};
243
244		pwm_ao_b_6_pins: pwm_ao_b_6 {
245			mux {
246				groups = "pwm_ao_b_6";
247				function = "pwm_ao_b";
248				bias-disable;
249			};
250		};
251
252		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
253			mux {
254				groups = "i2s_out_ch23_ao";
255				function = "i2s_out_ao";
256				bias-disable;
257			};
258		};
259
260		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
261			mux {
262				groups = "i2s_out_ch45_ao";
263				function = "i2s_out_ao";
264				bias-disable;
265			};
266		};
267
268		spdif_out_ao_6_pins: spdif_out_ao_6 {
269			mux {
270				groups = "spdif_out_ao_6";
271				function = "spdif_out_ao";
272				bias-disable;
273			};
274		};
275
276		spdif_out_ao_9_pins: spdif_out_ao_9 {
277			mux {
278				groups = "spdif_out_ao_9";
279				function = "spdif_out_ao";
280				bias-disable;
281			};
282		};
283
284		ao_cec_pins: ao_cec {
285			mux {
286				groups = "ao_cec";
287				function = "cec_ao";
288				bias-disable;
289			};
290		};
291
292		ee_cec_pins: ee_cec {
293			mux {
294				groups = "ee_cec";
295				function = "cec_ao";
296				bias-disable;
297			};
298		};
299	};
300};
301
302&cec_AO {
303	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
304	clock-names = "core";
305};
306
307&clkc_AO {
308	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
309	clocks = <&xtal>, <&clkc CLKID_CLK81>;
310	clock-names = "xtal", "mpeg-clk";
311};
312
313&gpio_intc {
314	compatible = "amlogic,meson-gpio-intc",
315		     "amlogic,meson-gxl-gpio-intc";
316	status = "okay";
317};
318
319&hdmi_tx {
320	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
321	resets = <&reset RESET_HDMITX_CAPB3>,
322		 <&reset RESET_HDMI_SYSTEM_RESET>,
323		 <&reset RESET_HDMI_TX>;
324	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
325	clocks = <&clkc CLKID_HDMI_PCLK>,
326		 <&clkc CLKID_CLK81>,
327		 <&clkc CLKID_GCLK_VENCI_INT0>;
328	clock-names = "isfr", "iahb", "venci";
329};
330
331&sysctrl {
332	clkc: clock-controller {
333		compatible = "amlogic,gxl-clkc";
334		#clock-cells = <1>;
335		clocks = <&xtal>;
336		clock-names = "xtal";
337	};
338};
339
340&hwrng {
341	clocks = <&clkc CLKID_RNG0>;
342	clock-names = "core";
343};
344
345&i2c_A {
346	clocks = <&clkc CLKID_I2C>;
347};
348
349&i2c_AO {
350	clocks = <&clkc CLKID_AO_I2C>;
351};
352
353&i2c_B {
354	clocks = <&clkc CLKID_I2C>;
355};
356
357&i2c_C {
358	clocks = <&clkc CLKID_I2C>;
359};
360
361&periphs {
362	pinctrl_periphs: pinctrl@4b0 {
363		compatible = "amlogic,meson-gxl-periphs-pinctrl";
364		#address-cells = <2>;
365		#size-cells = <2>;
366		ranges;
367
368		gpio: bank@4b0 {
369			reg = <0x0 0x004b0 0x0 0x28>,
370			      <0x0 0x004e8 0x0 0x14>,
371			      <0x0 0x00520 0x0 0x14>,
372			      <0x0 0x00430 0x0 0x40>;
373			reg-names = "mux", "pull", "pull-enable", "gpio";
374			gpio-controller;
375			#gpio-cells = <2>;
376			gpio-ranges = <&pinctrl_periphs 0 0 100>;
377		};
378
379		emmc_pins: emmc {
380			mux-0 {
381				groups = "emmc_nand_d07",
382				       "emmc_cmd";
383				function = "emmc";
384				bias-pull-up;
385			};
386
387			mux-1 {
388				groups = "emmc_clk";
389				function = "emmc";
390				bias-disable;
391			};
392		};
393
394		emmc_ds_pins: emmc-ds {
395			mux {
396				groups = "emmc_ds";
397				function = "emmc";
398				bias-pull-down;
399			};
400		};
401
402		emmc_clk_gate_pins: emmc_clk_gate {
403			mux {
404				groups = "BOOT_8";
405				function = "gpio_periphs";
406				bias-pull-down;
407			};
408		};
409
410		nor_pins: nor {
411			mux {
412				groups = "nor_d",
413				       "nor_q",
414				       "nor_c",
415				       "nor_cs";
416				function = "nor";
417				bias-disable;
418			};
419		};
420
421		spi_pins: spi-pins {
422			mux {
423				groups = "spi_miso",
424					"spi_mosi",
425					"spi_sclk";
426				function = "spi";
427				bias-disable;
428			};
429		};
430
431		spi_ss0_pins: spi-ss0 {
432			mux {
433				groups = "spi_ss0";
434				function = "spi";
435				bias-disable;
436			};
437		};
438
439		sdcard_pins: sdcard {
440			mux-0 {
441				groups = "sdcard_d0",
442				       "sdcard_d1",
443				       "sdcard_d2",
444				       "sdcard_d3",
445				       "sdcard_cmd";
446				function = "sdcard";
447				bias-pull-up;
448			};
449
450			mux-1 {
451				groups = "sdcard_clk";
452				function = "sdcard";
453				bias-disable;
454			};
455		};
456
457		sdcard_clk_gate_pins: sdcard_clk_gate {
458			mux {
459				groups = "CARD_2";
460				function = "gpio_periphs";
461				bias-pull-down;
462			};
463		};
464
465		sdio_pins: sdio {
466			mux-0 {
467				groups = "sdio_d0",
468				       "sdio_d1",
469				       "sdio_d2",
470				       "sdio_d3",
471				       "sdio_cmd";
472				function = "sdio";
473				bias-pull-up;
474			};
475
476			mux-1 {
477				groups = "sdio_clk";
478				function = "sdio";
479				bias-disable;
480			};
481		};
482
483		sdio_clk_gate_pins: sdio_clk_gate {
484			mux {
485				groups = "GPIOX_4";
486				function = "gpio_periphs";
487				bias-pull-down;
488			};
489		};
490
491		sdio_irq_pins: sdio_irq {
492			mux {
493				groups = "sdio_irq";
494				function = "sdio";
495				bias-disable;
496			};
497		};
498
499		uart_a_pins: uart_a {
500			mux {
501				groups = "uart_tx_a",
502				       "uart_rx_a";
503				function = "uart_a";
504				bias-disable;
505			};
506		};
507
508		uart_a_cts_rts_pins: uart_a_cts_rts {
509			mux {
510				groups = "uart_cts_a",
511				       "uart_rts_a";
512				function = "uart_a";
513				bias-disable;
514			};
515		};
516
517		uart_b_pins: uart_b {
518			mux {
519				groups = "uart_tx_b",
520				       "uart_rx_b";
521				function = "uart_b";
522				bias-disable;
523			};
524		};
525
526		uart_b_cts_rts_pins: uart_b_cts_rts {
527			mux {
528				groups = "uart_cts_b",
529				       "uart_rts_b";
530				function = "uart_b";
531				bias-disable;
532			};
533		};
534
535		uart_c_pins: uart_c {
536			mux {
537				groups = "uart_tx_c",
538				       "uart_rx_c";
539				function = "uart_c";
540				bias-disable;
541			};
542		};
543
544		uart_c_cts_rts_pins: uart_c_cts_rts {
545			mux {
546				groups = "uart_cts_c",
547				       "uart_rts_c";
548				function = "uart_c";
549				bias-disable;
550			};
551		};
552
553		i2c_a_pins: i2c_a {
554			mux {
555				groups = "i2c_sck_a",
556				     "i2c_sda_a";
557				function = "i2c_a";
558				bias-disable;
559			};
560		};
561
562		i2c_b_pins: i2c_b {
563			mux {
564				groups = "i2c_sck_b",
565				      "i2c_sda_b";
566				function = "i2c_b";
567				bias-disable;
568			};
569		};
570
571		i2c_c_pins: i2c_c {
572			mux {
573				groups = "i2c_sck_c",
574				      "i2c_sda_c";
575				function = "i2c_c";
576				bias-disable;
577			};
578		};
579
580		i2c_c_dv18_pins: i2c_c_dv18 {
581			mux {
582				groups = "i2c_sck_c_dv19",
583				      "i2c_sda_c_dv18";
584				function = "i2c_c";
585				bias-disable;
586			};
587		};
588
589		eth_pins: eth_c {
590			mux {
591				groups = "eth_mdio",
592				       "eth_mdc",
593				       "eth_clk_rx_clk",
594				       "eth_rx_dv",
595				       "eth_rxd0",
596				       "eth_rxd1",
597				       "eth_rxd2",
598				       "eth_rxd3",
599				       "eth_rgmii_tx_clk",
600				       "eth_tx_en",
601				       "eth_txd0",
602				       "eth_txd1",
603				       "eth_txd2",
604				       "eth_txd3";
605				function = "eth";
606				bias-disable;
607			};
608		};
609
610		eth_link_led_pins: eth_link_led {
611			mux {
612				groups = "eth_link_led";
613				function = "eth_led";
614				bias-disable;
615			};
616		};
617
618		eth_act_led_pins: eth_act_led {
619			mux {
620				groups = "eth_act_led";
621				function = "eth_led";
622			};
623		};
624
625		pwm_a_pins: pwm_a {
626			mux {
627				groups = "pwm_a";
628				function = "pwm_a";
629				bias-disable;
630			};
631		};
632
633		pwm_b_pins: pwm_b {
634			mux {
635				groups = "pwm_b";
636				function = "pwm_b";
637				bias-disable;
638			};
639		};
640
641		pwm_c_pins: pwm_c {
642			mux {
643				groups = "pwm_c";
644				function = "pwm_c";
645				bias-disable;
646			};
647		};
648
649		pwm_d_pins: pwm_d {
650			mux {
651				groups = "pwm_d";
652				function = "pwm_d";
653				bias-disable;
654			};
655		};
656
657		pwm_e_pins: pwm_e {
658			mux {
659				groups = "pwm_e";
660				function = "pwm_e";
661				bias-disable;
662			};
663		};
664
665		pwm_f_clk_pins: pwm_f_clk {
666			mux {
667				groups = "pwm_f_clk";
668				function = "pwm_f";
669				bias-disable;
670			};
671		};
672
673		pwm_f_x_pins: pwm_f_x {
674			mux {
675				groups = "pwm_f_x";
676				function = "pwm_f";
677				bias-disable;
678			};
679		};
680
681		hdmi_hpd_pins: hdmi_hpd {
682			mux {
683				groups = "hdmi_hpd";
684				function = "hdmi_hpd";
685				bias-disable;
686			};
687		};
688
689		hdmi_i2c_pins: hdmi_i2c {
690			mux {
691				groups = "hdmi_sda", "hdmi_scl";
692				function = "hdmi_i2c";
693				bias-disable;
694			};
695		};
696
697		i2s_am_clk_pins: i2s_am_clk {
698			mux {
699				groups = "i2s_am_clk";
700				function = "i2s_out";
701				bias-disable;
702			};
703		};
704
705		i2s_out_ao_clk_pins: i2s_out_ao_clk {
706			mux {
707				groups = "i2s_out_ao_clk";
708				function = "i2s_out";
709				bias-disable;
710			};
711		};
712
713		i2s_out_lr_clk_pins: i2s_out_lr_clk {
714			mux {
715				groups = "i2s_out_lr_clk";
716				function = "i2s_out";
717				bias-disable;
718			};
719		};
720
721		i2s_out_ch01_pins: i2s_out_ch01 {
722			mux {
723				groups = "i2s_out_ch01";
724				function = "i2s_out";
725				bias-disable;
726			};
727		};
728		i2sout_ch23_z_pins: i2sout_ch23_z {
729			mux {
730				groups = "i2sout_ch23_z";
731				function = "i2s_out";
732				bias-disable;
733			};
734		};
735
736		i2sout_ch45_z_pins: i2sout_ch45_z {
737			mux {
738				groups = "i2sout_ch45_z";
739				function = "i2s_out";
740				bias-disable;
741			};
742		};
743
744		i2sout_ch67_z_pins: i2sout_ch67_z {
745			mux {
746				groups = "i2sout_ch67_z";
747				function = "i2s_out";
748				bias-disable;
749			};
750		};
751
752		spdif_out_h_pins: spdif_out_ao_h {
753			mux {
754				groups = "spdif_out_h";
755				function = "spdif_out";
756				bias-disable;
757			};
758		};
759	};
760
761	eth-phy-mux {
762		compatible = "mdio-mux-mmioreg", "mdio-mux";
763		#address-cells = <1>;
764		#size-cells = <0>;
765		reg = <0x0 0x55c 0x0 0x4>;
766		mux-mask = <0xffffffff>;
767		mdio-parent-bus = <&mdio0>;
768
769		internal_mdio: mdio@e40908ff {
770			reg = <0xe40908ff>;
771			#address-cells = <1>;
772			#size-cells = <0>;
773
774			internal_phy: ethernet-phy@8 {
775				compatible = "ethernet-phy-id0181.4400";
776				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
777				reg = <8>;
778				max-speed = <100>;
779			};
780		};
781
782		external_mdio: mdio@2009087f {
783			reg = <0x2009087f>;
784			#address-cells = <1>;
785			#size-cells = <0>;
786		};
787	};
788};
789
790&pwrc_vpu {
791	resets = <&reset RESET_VIU>,
792		 <&reset RESET_VENC>,
793		 <&reset RESET_VCBUS>,
794		 <&reset RESET_BT656>,
795		 <&reset RESET_DVIN_RESET>,
796		 <&reset RESET_RDMA>,
797		 <&reset RESET_VENCI>,
798		 <&reset RESET_VENCP>,
799		 <&reset RESET_VDAC>,
800		 <&reset RESET_VDI6>,
801		 <&reset RESET_VENCL>,
802		 <&reset RESET_VID_LOCK>;
803	clocks = <&clkc CLKID_VPU>,
804	         <&clkc CLKID_VAPB>;
805	clock-names = "vpu", "vapb";
806	/*
807	 * VPU clocking is provided by two identical clock paths
808	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
809	 * free mux to safely change frequency while running.
810	 * Same for VAPB but with a final gate after the glitch free mux.
811	 */
812	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
813			  <&clkc CLKID_VPU_0>,
814			  <&clkc CLKID_VPU>, /* Glitch free mux */
815			  <&clkc CLKID_VAPB_0_SEL>,
816			  <&clkc CLKID_VAPB_0>,
817			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
818	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
819				 <0>, /* Do Nothing */
820				 <&clkc CLKID_VPU_0>,
821				 <&clkc CLKID_FCLK_DIV4>,
822				 <0>, /* Do Nothing */
823				 <&clkc CLKID_VAPB_0>;
824	assigned-clock-rates = <0>, /* Do Nothing */
825			       <666666666>,
826			       <0>, /* Do Nothing */
827			       <0>, /* Do Nothing */
828			       <250000000>,
829			       <0>; /* Do Nothing */
830};
831
832&saradc {
833	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
834	clocks = <&xtal>,
835		 <&clkc CLKID_SAR_ADC>,
836		 <&clkc CLKID_SAR_ADC_CLK>,
837		 <&clkc CLKID_SAR_ADC_SEL>;
838	clock-names = "clkin", "core", "adc_clk", "adc_sel";
839};
840
841&sd_emmc_a {
842	clocks = <&clkc CLKID_SD_EMMC_A>,
843		 <&clkc CLKID_SD_EMMC_A_CLK0>,
844		 <&clkc CLKID_FCLK_DIV2>;
845	clock-names = "core", "clkin0", "clkin1";
846	resets = <&reset RESET_SD_EMMC_A>;
847};
848
849&sd_emmc_b {
850	clocks = <&clkc CLKID_SD_EMMC_B>,
851		 <&clkc CLKID_SD_EMMC_B_CLK0>,
852		 <&clkc CLKID_FCLK_DIV2>;
853	clock-names = "core", "clkin0", "clkin1";
854	resets = <&reset RESET_SD_EMMC_B>;
855};
856
857&sd_emmc_c {
858	clocks = <&clkc CLKID_SD_EMMC_C>,
859		 <&clkc CLKID_SD_EMMC_C_CLK0>,
860		 <&clkc CLKID_FCLK_DIV2>;
861	clock-names = "core", "clkin0", "clkin1";
862	resets = <&reset RESET_SD_EMMC_C>;
863};
864
865&simplefb_hdmi {
866	clocks = <&clkc CLKID_HDMI_PCLK>,
867		 <&clkc CLKID_CLK81>,
868		 <&clkc CLKID_GCLK_VENCI_INT0>;
869};
870
871&spicc {
872	clocks = <&clkc CLKID_SPICC>;
873	clock-names = "core";
874	resets = <&reset RESET_PERIPHS_SPICC>;
875	num-cs = <1>;
876};
877
878&spifc {
879	clocks = <&clkc CLKID_SPI>;
880};
881
882&uart_A {
883	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
884	clock-names = "xtal", "pclk", "baud";
885};
886
887&uart_AO {
888	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
889	clock-names = "xtal", "pclk", "baud";
890};
891
892&uart_AO_B {
893	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
894	clock-names = "xtal", "pclk", "baud";
895};
896
897&uart_B {
898	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
899	clock-names = "xtal", "pclk", "baud";
900};
901
902&uart_C {
903	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
904	clock-names = "xtal", "pclk", "baud";
905};
906
907&vpu {
908	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
909	power-domains = <&pwrc_vpu>;
910};
911
912&vdec {
913	compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
914	clocks = <&clkc CLKID_DOS_PARSER>,
915		 <&clkc CLKID_DOS>,
916		 <&clkc CLKID_VDEC_1>,
917		 <&clkc CLKID_VDEC_HEVC>;
918	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
919	resets = <&reset RESET_PARSER>;
920	reset-names = "esparser";
921};
922