1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb: usb@d0078080 {
18			compatible = "amlogic,meson-gxl-usb-ctrl";
19			reg = <0x0 0xd0078080 0x0 0x20>;
20			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
21			#address-cells = <2>;
22			#size-cells = <2>;
23			ranges;
24
25			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26			clock-names = "usb_ctrl", "ddr";
27			resets = <&reset RESET_USB_OTG>;
28
29			dr_mode = "otg";
30
31			phys = <&usb2_phy0>, <&usb2_phy1>;
32			phy-names = "usb2-phy0", "usb2-phy1";
33
34			dwc2: usb@c9100000 {
35				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36				reg = <0x0 0xc9100000 0x0 0x40000>;
37				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38				clocks = <&clkc CLKID_USB1>;
39				clock-names = "otg";
40				phys = <&usb2_phy1>;
41				dr_mode = "peripheral";
42				g-rx-fifo-size = <192>;
43				g-np-tx-fifo-size = <128>;
44				g-tx-fifo-size = <128 128 16 16 16>;
45			};
46
47			dwc3: usb@c9000000 {
48				compatible = "snps,dwc3";
49				reg = <0x0 0xc9000000 0x0 0x100000>;
50				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51				dr_mode = "host";
52				maximum-speed = "high-speed";
53				snps,dis_u2_susphy_quirk;
54			};
55		};
56
57		acodec: audio-controller@c8832000 {
58			compatible = "amlogic,t9015";
59			reg = <0x0 0xc8832000 0x0 0x14>;
60			#sound-dai-cells = <0>;
61			sound-name-prefix = "ACODEC";
62			clocks = <&clkc CLKID_ACODEC>;
63			clock-names = "pclk";
64			resets = <&reset RESET_ACODEC>;
65			status = "disabled";
66		};
67
68		crypto: crypto@c883e000 {
69			compatible = "amlogic,gxl-crypto";
70			reg = <0x0 0xc883e000 0x0 0x36>;
71			interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73			clocks = <&clkc CLKID_BLKMV>;
74			clock-names = "blkmv";
75			status = "okay";
76		};
77	};
78};
79
80&aiu {
81	compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82	clocks = <&clkc CLKID_AIU_GLUE>,
83		 <&clkc CLKID_I2S_OUT>,
84		 <&clkc CLKID_AOCLK_GATE>,
85		 <&clkc CLKID_CTS_AMCLK>,
86		 <&clkc CLKID_MIXER_IFACE>,
87		 <&clkc CLKID_IEC958>,
88		 <&clkc CLKID_IEC958_GATE>,
89		 <&clkc CLKID_CTS_MCLK_I958>,
90		 <&clkc CLKID_CTS_I958>;
91	clock-names = "pclk",
92		      "i2s_pclk",
93		      "i2s_aoclk",
94		      "i2s_mclk",
95		      "i2s_mixer",
96		      "spdif_pclk",
97		      "spdif_aoclk",
98		      "spdif_mclk",
99		      "spdif_mclk_sel";
100	resets = <&reset RESET_AIU>;
101};
102
103&apb {
104	usb2_phy0: phy@78000 {
105		compatible = "amlogic,meson-gxl-usb2-phy";
106		#phy-cells = <0>;
107		reg = <0x0 0x78000 0x0 0x20>;
108		clocks = <&clkc CLKID_USB>;
109		clock-names = "phy";
110		resets = <&reset RESET_USB_OTG>;
111		reset-names = "phy";
112		status = "okay";
113	};
114
115	usb2_phy1: phy@78020 {
116		compatible = "amlogic,meson-gxl-usb2-phy";
117		#phy-cells = <0>;
118		reg = <0x0 0x78020 0x0 0x20>;
119		clocks = <&clkc CLKID_USB>;
120		clock-names = "phy";
121		resets = <&reset RESET_USB_OTG>;
122		reset-names = "phy";
123		status = "okay";
124	};
125};
126
127&efuse {
128	clocks = <&clkc CLKID_EFUSE>;
129};
130
131&ethmac {
132	clocks = <&clkc CLKID_ETH>,
133		 <&clkc CLKID_FCLK_DIV2>,
134		 <&clkc CLKID_MPLL2>,
135		 <&clkc CLKID_FCLK_DIV2>;
136	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
137
138	mdio0: mdio {
139		#address-cells = <1>;
140		#size-cells = <0>;
141		compatible = "snps,dwmac-mdio";
142	};
143};
144
145&aobus {
146	pinctrl_aobus: pinctrl@14 {
147		compatible = "amlogic,meson-gxl-aobus-pinctrl";
148		#address-cells = <2>;
149		#size-cells = <2>;
150		ranges;
151
152		gpio_ao: bank@14 {
153			reg = <0x0 0x00014 0x0 0x8>,
154			      <0x0 0x0002c 0x0 0x4>,
155			      <0x0 0x00024 0x0 0x8>;
156			reg-names = "mux", "pull", "gpio";
157			gpio-controller;
158			#gpio-cells = <2>;
159			gpio-ranges = <&pinctrl_aobus 0 0 14>;
160		};
161
162		uart_ao_a_pins: uart_ao_a {
163			mux {
164				groups = "uart_tx_ao_a", "uart_rx_ao_a";
165				function = "uart_ao";
166				bias-disable;
167			};
168		};
169
170		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171			mux {
172				groups = "uart_cts_ao_a",
173				       "uart_rts_ao_a";
174				function = "uart_ao";
175				bias-disable;
176			};
177		};
178
179		uart_ao_b_pins: uart_ao_b {
180			mux {
181				groups = "uart_tx_ao_b", "uart_rx_ao_b";
182				function = "uart_ao_b";
183				bias-disable;
184			};
185		};
186
187		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188			mux {
189				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190				function = "uart_ao_b";
191				bias-disable;
192			};
193		};
194
195		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196			mux {
197				groups = "uart_cts_ao_b",
198				       "uart_rts_ao_b";
199				function = "uart_ao_b";
200				bias-disable;
201			};
202		};
203
204		remote_input_ao_pins: remote_input_ao {
205			mux {
206				groups = "remote_input_ao";
207				function = "remote_input_ao";
208				bias-disable;
209			};
210		};
211
212		i2c_ao_pins: i2c_ao {
213			mux {
214				groups = "i2c_sck_ao",
215				       "i2c_sda_ao";
216				function = "i2c_ao";
217				bias-disable;
218			};
219		};
220
221		pwm_ao_a_3_pins: pwm_ao_a_3 {
222			mux {
223				groups = "pwm_ao_a_3";
224				function = "pwm_ao_a";
225				bias-disable;
226			};
227		};
228
229		pwm_ao_a_8_pins: pwm_ao_a_8 {
230			mux {
231				groups = "pwm_ao_a_8";
232				function = "pwm_ao_a";
233				bias-disable;
234			};
235		};
236
237		pwm_ao_b_pins: pwm_ao_b {
238			mux {
239				groups = "pwm_ao_b";
240				function = "pwm_ao_b";
241				bias-disable;
242			};
243		};
244
245		pwm_ao_b_6_pins: pwm_ao_b_6 {
246			mux {
247				groups = "pwm_ao_b_6";
248				function = "pwm_ao_b";
249				bias-disable;
250			};
251		};
252
253		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254			mux {
255				groups = "i2s_out_ch23_ao";
256				function = "i2s_out_ao";
257				bias-disable;
258			};
259		};
260
261		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262			mux {
263				groups = "i2s_out_ch45_ao";
264				function = "i2s_out_ao";
265				bias-disable;
266			};
267		};
268
269		spdif_out_ao_6_pins: spdif_out_ao_6 {
270			mux {
271				groups = "spdif_out_ao_6";
272				function = "spdif_out_ao";
273				bias-disable;
274			};
275		};
276
277		spdif_out_ao_9_pins: spdif_out_ao_9 {
278			mux {
279				groups = "spdif_out_ao_9";
280				function = "spdif_out_ao";
281				bias-disable;
282			};
283		};
284
285		ao_cec_pins: ao_cec {
286			mux {
287				groups = "ao_cec";
288				function = "cec_ao";
289				bias-disable;
290			};
291		};
292
293		ee_cec_pins: ee_cec {
294			mux {
295				groups = "ee_cec";
296				function = "cec_ao";
297				bias-disable;
298			};
299		};
300	};
301};
302
303&cec_AO {
304	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305	clock-names = "core";
306};
307
308&clkc_AO {
309	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310	clocks = <&xtal>, <&clkc CLKID_CLK81>;
311	clock-names = "xtal", "mpeg-clk";
312};
313
314&gpio_intc {
315	compatible = "amlogic,meson-gpio-intc",
316		     "amlogic,meson-gxl-gpio-intc";
317	status = "okay";
318};
319
320&hdmi_tx {
321	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322	resets = <&reset RESET_HDMITX_CAPB3>,
323		 <&reset RESET_HDMI_SYSTEM_RESET>,
324		 <&reset RESET_HDMI_TX>;
325	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326	clocks = <&clkc CLKID_HDMI_PCLK>,
327		 <&clkc CLKID_CLK81>,
328		 <&clkc CLKID_GCLK_VENCI_INT0>;
329	clock-names = "isfr", "iahb", "venci";
330};
331
332&sysctrl {
333	clkc: clock-controller {
334		compatible = "amlogic,gxl-clkc";
335		#clock-cells = <1>;
336		clocks = <&xtal>;
337		clock-names = "xtal";
338	};
339};
340
341&i2c_A {
342	clocks = <&clkc CLKID_I2C>;
343};
344
345&i2c_AO {
346	clocks = <&clkc CLKID_AO_I2C>;
347};
348
349&i2c_B {
350	clocks = <&clkc CLKID_I2C>;
351};
352
353&i2c_C {
354	clocks = <&clkc CLKID_I2C>;
355};
356
357&periphs {
358	pinctrl_periphs: pinctrl@4b0 {
359		compatible = "amlogic,meson-gxl-periphs-pinctrl";
360		#address-cells = <2>;
361		#size-cells = <2>;
362		ranges;
363
364		gpio: bank@4b0 {
365			reg = <0x0 0x004b0 0x0 0x28>,
366			      <0x0 0x004e8 0x0 0x14>,
367			      <0x0 0x00520 0x0 0x14>,
368			      <0x0 0x00430 0x0 0x40>;
369			reg-names = "mux", "pull", "pull-enable", "gpio";
370			gpio-controller;
371			#gpio-cells = <2>;
372			gpio-ranges = <&pinctrl_periphs 0 0 100>;
373		};
374
375		emmc_pins: emmc {
376			mux-0 {
377				groups = "emmc_nand_d07",
378				       "emmc_cmd";
379				function = "emmc";
380				bias-pull-up;
381			};
382
383			mux-1 {
384				groups = "emmc_clk";
385				function = "emmc";
386				bias-disable;
387			};
388		};
389
390		emmc_ds_pins: emmc-ds {
391			mux {
392				groups = "emmc_ds";
393				function = "emmc";
394				bias-pull-down;
395			};
396		};
397
398		emmc_clk_gate_pins: emmc_clk_gate {
399			mux {
400				groups = "BOOT_8";
401				function = "gpio_periphs";
402				bias-pull-down;
403			};
404		};
405
406		nor_pins: nor {
407			mux {
408				groups = "nor_d",
409				       "nor_q",
410				       "nor_c",
411				       "nor_cs";
412				function = "nor";
413				bias-disable;
414			};
415		};
416
417		spi_pins: spi-pins {
418			mux {
419				groups = "spi_miso",
420					"spi_mosi",
421					"spi_sclk";
422				function = "spi";
423				bias-disable;
424			};
425		};
426
427		spi_ss0_pins: spi-ss0 {
428			mux {
429				groups = "spi_ss0";
430				function = "spi";
431				bias-disable;
432			};
433		};
434
435		sdcard_pins: sdcard {
436			mux-0 {
437				groups = "sdcard_d0",
438				       "sdcard_d1",
439				       "sdcard_d2",
440				       "sdcard_d3",
441				       "sdcard_cmd";
442				function = "sdcard";
443				bias-pull-up;
444			};
445
446			mux-1 {
447				groups = "sdcard_clk";
448				function = "sdcard";
449				bias-disable;
450			};
451		};
452
453		sdcard_clk_gate_pins: sdcard_clk_gate {
454			mux {
455				groups = "CARD_2";
456				function = "gpio_periphs";
457				bias-pull-down;
458			};
459		};
460
461		sdio_pins: sdio {
462			mux-0 {
463				groups = "sdio_d0",
464				       "sdio_d1",
465				       "sdio_d2",
466				       "sdio_d3",
467				       "sdio_cmd";
468				function = "sdio";
469				bias-pull-up;
470			};
471
472			mux-1 {
473				groups = "sdio_clk";
474				function = "sdio";
475				bias-disable;
476			};
477		};
478
479		sdio_clk_gate_pins: sdio_clk_gate {
480			mux {
481				groups = "GPIOX_4";
482				function = "gpio_periphs";
483				bias-pull-down;
484			};
485		};
486
487		sdio_irq_pins: sdio_irq {
488			mux {
489				groups = "sdio_irq";
490				function = "sdio";
491				bias-disable;
492			};
493		};
494
495		uart_a_pins: uart_a {
496			mux {
497				groups = "uart_tx_a",
498				       "uart_rx_a";
499				function = "uart_a";
500				bias-disable;
501			};
502		};
503
504		uart_a_cts_rts_pins: uart_a_cts_rts {
505			mux {
506				groups = "uart_cts_a",
507				       "uart_rts_a";
508				function = "uart_a";
509				bias-disable;
510			};
511		};
512
513		uart_b_pins: uart_b {
514			mux {
515				groups = "uart_tx_b",
516				       "uart_rx_b";
517				function = "uart_b";
518				bias-disable;
519			};
520		};
521
522		uart_b_cts_rts_pins: uart_b_cts_rts {
523			mux {
524				groups = "uart_cts_b",
525				       "uart_rts_b";
526				function = "uart_b";
527				bias-disable;
528			};
529		};
530
531		uart_c_pins: uart_c {
532			mux {
533				groups = "uart_tx_c",
534				       "uart_rx_c";
535				function = "uart_c";
536				bias-disable;
537			};
538		};
539
540		uart_c_cts_rts_pins: uart_c_cts_rts {
541			mux {
542				groups = "uart_cts_c",
543				       "uart_rts_c";
544				function = "uart_c";
545				bias-disable;
546			};
547		};
548
549		i2c_a_pins: i2c_a {
550			mux {
551				groups = "i2c_sck_a",
552				     "i2c_sda_a";
553				function = "i2c_a";
554				bias-disable;
555			};
556		};
557
558		i2c_b_pins: i2c_b {
559			mux {
560				groups = "i2c_sck_b",
561				      "i2c_sda_b";
562				function = "i2c_b";
563				bias-disable;
564			};
565		};
566
567		i2c_c_pins: i2c_c {
568			mux {
569				groups = "i2c_sck_c",
570				      "i2c_sda_c";
571				function = "i2c_c";
572				bias-disable;
573			};
574		};
575
576		i2c_c_dv18_pins: i2c_c_dv18 {
577			mux {
578				groups = "i2c_sck_c_dv19",
579				      "i2c_sda_c_dv18";
580				function = "i2c_c";
581				bias-disable;
582			};
583		};
584
585		eth_pins: eth_c {
586			mux {
587				groups = "eth_mdio",
588				       "eth_mdc",
589				       "eth_clk_rx_clk",
590				       "eth_rx_dv",
591				       "eth_rxd0",
592				       "eth_rxd1",
593				       "eth_rxd2",
594				       "eth_rxd3",
595				       "eth_rgmii_tx_clk",
596				       "eth_tx_en",
597				       "eth_txd0",
598				       "eth_txd1",
599				       "eth_txd2",
600				       "eth_txd3";
601				function = "eth";
602				bias-disable;
603			};
604		};
605
606		eth_link_led_pins: eth_link_led {
607			mux {
608				groups = "eth_link_led";
609				function = "eth_led";
610				bias-disable;
611			};
612		};
613
614		eth_act_led_pins: eth_act_led {
615			mux {
616				groups = "eth_act_led";
617				function = "eth_led";
618			};
619		};
620
621		pwm_a_pins: pwm_a {
622			mux {
623				groups = "pwm_a";
624				function = "pwm_a";
625				bias-disable;
626			};
627		};
628
629		pwm_b_pins: pwm_b {
630			mux {
631				groups = "pwm_b";
632				function = "pwm_b";
633				bias-disable;
634			};
635		};
636
637		pwm_c_pins: pwm_c {
638			mux {
639				groups = "pwm_c";
640				function = "pwm_c";
641				bias-disable;
642			};
643		};
644
645		pwm_d_pins: pwm_d {
646			mux {
647				groups = "pwm_d";
648				function = "pwm_d";
649				bias-disable;
650			};
651		};
652
653		pwm_e_pins: pwm_e {
654			mux {
655				groups = "pwm_e";
656				function = "pwm_e";
657				bias-disable;
658			};
659		};
660
661		pwm_f_clk_pins: pwm_f_clk {
662			mux {
663				groups = "pwm_f_clk";
664				function = "pwm_f";
665				bias-disable;
666			};
667		};
668
669		pwm_f_x_pins: pwm_f_x {
670			mux {
671				groups = "pwm_f_x";
672				function = "pwm_f";
673				bias-disable;
674			};
675		};
676
677		hdmi_hpd_pins: hdmi_hpd {
678			mux {
679				groups = "hdmi_hpd";
680				function = "hdmi_hpd";
681				bias-disable;
682			};
683		};
684
685		hdmi_i2c_pins: hdmi_i2c {
686			mux {
687				groups = "hdmi_sda", "hdmi_scl";
688				function = "hdmi_i2c";
689				bias-disable;
690			};
691		};
692
693		i2s_am_clk_pins: i2s_am_clk {
694			mux {
695				groups = "i2s_am_clk";
696				function = "i2s_out";
697				bias-disable;
698			};
699		};
700
701		i2s_out_ao_clk_pins: i2s_out_ao_clk {
702			mux {
703				groups = "i2s_out_ao_clk";
704				function = "i2s_out";
705				bias-disable;
706			};
707		};
708
709		i2s_out_lr_clk_pins: i2s_out_lr_clk {
710			mux {
711				groups = "i2s_out_lr_clk";
712				function = "i2s_out";
713				bias-disable;
714			};
715		};
716
717		i2s_out_ch01_pins: i2s_out_ch01 {
718			mux {
719				groups = "i2s_out_ch01";
720				function = "i2s_out";
721				bias-disable;
722			};
723		};
724		i2sout_ch23_z_pins: i2sout_ch23_z {
725			mux {
726				groups = "i2sout_ch23_z";
727				function = "i2s_out";
728				bias-disable;
729			};
730		};
731
732		i2sout_ch45_z_pins: i2sout_ch45_z {
733			mux {
734				groups = "i2sout_ch45_z";
735				function = "i2s_out";
736				bias-disable;
737			};
738		};
739
740		i2sout_ch67_z_pins: i2sout_ch67_z {
741			mux {
742				groups = "i2sout_ch67_z";
743				function = "i2s_out";
744				bias-disable;
745			};
746		};
747
748		spdif_out_h_pins: spdif_out_ao_h {
749			mux {
750				groups = "spdif_out_h";
751				function = "spdif_out";
752				bias-disable;
753			};
754		};
755	};
756
757	eth-phy-mux {
758		compatible = "mdio-mux-mmioreg", "mdio-mux";
759		#address-cells = <1>;
760		#size-cells = <0>;
761		reg = <0x0 0x55c 0x0 0x4>;
762		mux-mask = <0xffffffff>;
763		mdio-parent-bus = <&mdio0>;
764
765		internal_mdio: mdio@e40908ff {
766			reg = <0xe40908ff>;
767			#address-cells = <1>;
768			#size-cells = <0>;
769
770			internal_phy: ethernet-phy@8 {
771				compatible = "ethernet-phy-id0181.4400";
772				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
773				reg = <8>;
774				max-speed = <100>;
775			};
776		};
777
778		external_mdio: mdio@2009087f {
779			reg = <0x2009087f>;
780			#address-cells = <1>;
781			#size-cells = <0>;
782		};
783	};
784};
785
786&pwrc {
787	resets = <&reset RESET_VIU>,
788		 <&reset RESET_VENC>,
789		 <&reset RESET_VCBUS>,
790		 <&reset RESET_BT656>,
791		 <&reset RESET_DVIN_RESET>,
792		 <&reset RESET_RDMA>,
793		 <&reset RESET_VENCI>,
794		 <&reset RESET_VENCP>,
795		 <&reset RESET_VDAC>,
796		 <&reset RESET_VDI6>,
797		 <&reset RESET_VENCL>,
798		 <&reset RESET_VID_LOCK>;
799	reset-names = "viu", "venc", "vcbus", "bt656",
800		      "dvin", "rdma", "venci", "vencp",
801		      "vdac", "vdi6", "vencl", "vid_lock";
802	clocks = <&clkc CLKID_VPU>,
803	         <&clkc CLKID_VAPB>;
804	clock-names = "vpu", "vapb";
805	/*
806	 * VPU clocking is provided by two identical clock paths
807	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
808	 * free mux to safely change frequency while running.
809	 * Same for VAPB but with a final gate after the glitch free mux.
810	 */
811	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
812			  <&clkc CLKID_VPU_0>,
813			  <&clkc CLKID_VPU>, /* Glitch free mux */
814			  <&clkc CLKID_VAPB_0_SEL>,
815			  <&clkc CLKID_VAPB_0>,
816			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
817	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
818				 <0>, /* Do Nothing */
819				 <&clkc CLKID_VPU_0>,
820				 <&clkc CLKID_FCLK_DIV4>,
821				 <0>, /* Do Nothing */
822				 <&clkc CLKID_VAPB_0>;
823	assigned-clock-rates = <0>, /* Do Nothing */
824			       <666666666>,
825			       <0>, /* Do Nothing */
826			       <0>, /* Do Nothing */
827			       <250000000>,
828			       <0>; /* Do Nothing */
829};
830
831&saradc {
832	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
833	clocks = <&xtal>,
834		 <&clkc CLKID_SAR_ADC>,
835		 <&clkc CLKID_SAR_ADC_CLK>,
836		 <&clkc CLKID_SAR_ADC_SEL>;
837	clock-names = "clkin", "core", "adc_clk", "adc_sel";
838};
839
840&sd_emmc_a {
841	clocks = <&clkc CLKID_SD_EMMC_A>,
842		 <&clkc CLKID_SD_EMMC_A_CLK0>,
843		 <&clkc CLKID_FCLK_DIV2>;
844	clock-names = "core", "clkin0", "clkin1";
845	resets = <&reset RESET_SD_EMMC_A>;
846};
847
848&sd_emmc_b {
849	clocks = <&clkc CLKID_SD_EMMC_B>,
850		 <&clkc CLKID_SD_EMMC_B_CLK0>,
851		 <&clkc CLKID_FCLK_DIV2>;
852	clock-names = "core", "clkin0", "clkin1";
853	resets = <&reset RESET_SD_EMMC_B>;
854};
855
856&sd_emmc_c {
857	clocks = <&clkc CLKID_SD_EMMC_C>,
858		 <&clkc CLKID_SD_EMMC_C_CLK0>,
859		 <&clkc CLKID_FCLK_DIV2>;
860	clock-names = "core", "clkin0", "clkin1";
861	resets = <&reset RESET_SD_EMMC_C>;
862};
863
864&simplefb_hdmi {
865	clocks = <&clkc CLKID_HDMI_PCLK>,
866		 <&clkc CLKID_CLK81>,
867		 <&clkc CLKID_GCLK_VENCI_INT0>;
868};
869
870&spicc {
871	clocks = <&clkc CLKID_SPICC>;
872	clock-names = "core";
873	resets = <&reset RESET_PERIPHS_SPICC>;
874	num-cs = <1>;
875};
876
877&spifc {
878	clocks = <&clkc CLKID_SPI>;
879};
880
881&uart_A {
882	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
883	clock-names = "xtal", "pclk", "baud";
884};
885
886&uart_AO {
887	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
888	clock-names = "xtal", "pclk", "baud";
889};
890
891&uart_AO_B {
892	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
893	clock-names = "xtal", "pclk", "baud";
894};
895
896&uart_B {
897	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
898	clock-names = "xtal", "pclk", "baud";
899};
900
901&uart_C {
902	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
903	clock-names = "xtal", "pclk", "baud";
904};
905
906&vpu {
907	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
908	power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
909};
910
911&vdec {
912	compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
913	clocks = <&clkc CLKID_DOS_PARSER>,
914		 <&clkc CLKID_DOS>,
915		 <&clkc CLKID_VDEC_1>,
916		 <&clkc CLKID_VDEC_HEVC>;
917	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
918	resets = <&reset RESET_PARSER>;
919	reset-names = "esparser";
920};
921