1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47
48/ {
49	compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53	reg = <0x0 0xc9410000 0x0 0x10000
54	       0x0 0xc8834540 0x0 0x4>;
55
56	clocks = <&clkc CLKID_ETH>,
57		 <&clkc CLKID_FCLK_DIV2>,
58		 <&clkc CLKID_MPLL2>;
59	clock-names = "stmmaceth", "clkin0", "clkin1";
60
61	mdio0: mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		compatible = "snps,dwmac-mdio";
65	};
66};
67
68&aobus {
69	pinctrl_aobus: pinctrl@14 {
70		compatible = "amlogic,meson-gxl-aobus-pinctrl";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gpio_ao: bank@14 {
76			reg = <0x0 0x00014 0x0 0x8>,
77			      <0x0 0x0002c 0x0 0x4>,
78			      <0x0 0x00024 0x0 0x8>;
79			reg-names = "mux", "pull", "gpio";
80			gpio-controller;
81			#gpio-cells = <2>;
82		};
83
84		uart_ao_a_pins: uart_ao_a {
85			mux {
86				groups = "uart_tx_ao_a", "uart_rx_ao_a";
87				function = "uart_ao";
88			};
89		};
90
91		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
92			mux {
93				groups = "uart_cts_ao_a",
94				       "uart_rts_ao_a";
95				function = "uart_ao";
96			};
97		};
98
99		uart_ao_b_pins: uart_ao_b {
100			mux {
101				groups = "uart_tx_ao_b", "uart_rx_ao_b";
102				function = "uart_ao_b";
103			};
104		};
105
106		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
107			mux {
108				groups = "uart_cts_ao_b",
109				       "uart_rts_ao_b";
110				function = "uart_ao_b";
111			};
112		};
113
114		remote_input_ao_pins: remote_input_ao {
115			mux {
116				groups = "remote_input_ao";
117				function = "remote_input_ao";
118			};
119		};
120	};
121};
122
123&periphs {
124	pinctrl_periphs: pinctrl@4b0 {
125		compatible = "amlogic,meson-gxl-periphs-pinctrl";
126		#address-cells = <2>;
127		#size-cells = <2>;
128		ranges;
129
130		gpio: bank@4b0 {
131			reg = <0x0 0x004b0 0x0 0x28>,
132			      <0x0 0x004e8 0x0 0x14>,
133			      <0x0 0x00120 0x0 0x14>,
134			      <0x0 0x00430 0x0 0x40>;
135			reg-names = "mux", "pull", "pull-enable", "gpio";
136			gpio-controller;
137			#gpio-cells = <2>;
138		};
139
140		emmc_pins: emmc {
141			mux {
142				groups = "emmc_nand_d07",
143				       "emmc_cmd",
144				       "emmc_clk",
145				       "emmc_ds";
146				function = "emmc";
147			};
148		};
149
150		sdcard_pins: sdcard {
151			mux {
152				groups = "sdcard_d0",
153				       "sdcard_d1",
154				       "sdcard_d2",
155				       "sdcard_d3",
156				       "sdcard_cmd",
157				       "sdcard_clk";
158				function = "sdcard";
159			};
160		};
161
162		sdio_pins: sdio {
163			mux {
164				groups = "sdio_d0",
165				       "sdio_d1",
166				       "sdio_d2",
167				       "sdio_d3",
168				       "sdio_cmd",
169				       "sdio_clk";
170				function = "sdio";
171			};
172		};
173
174		sdio_irq_pins: sdio_irq {
175			mux {
176				groups = "sdio_irq";
177				function = "sdio";
178			};
179		};
180
181		uart_a_pins: uart_a {
182			mux {
183				groups = "uart_tx_a",
184				       "uart_rx_a";
185				function = "uart_a";
186			};
187		};
188
189		uart_a_cts_rts_pins: uart_a_cts_rts {
190			mux {
191				groups = "uart_cts_a",
192				       "uart_rts_a";
193				function = "uart_a";
194			};
195		};
196
197		uart_b_pins: uart_b {
198			mux {
199				groups = "uart_tx_b",
200				       "uart_rx_b";
201				function = "uart_b";
202			};
203		};
204
205		uart_b_cts_rts_pins: uart_b_cts_rts {
206			mux {
207				groups = "uart_cts_b",
208				       "uart_rts_b";
209				function = "uart_b";
210			};
211		};
212
213		uart_c_pins: uart_c {
214			mux {
215				groups = "uart_tx_c",
216				       "uart_rx_c";
217				function = "uart_c";
218			};
219		};
220
221		uart_c_cts_rts_pins: uart_c_cts_rts {
222			mux {
223				groups = "uart_cts_c",
224				       "uart_rts_c";
225				function = "uart_c";
226			};
227		};
228
229		i2c_a_pins: i2c_a {
230			mux {
231				groups = "i2c_sck_a",
232				     "i2c_sda_a";
233				function = "i2c_a";
234			};
235		};
236
237		i2c_b_pins: i2c_b {
238			mux {
239				groups = "i2c_sck_b",
240				      "i2c_sda_b";
241				function = "i2c_b";
242			};
243		};
244
245		i2c_c_pins: i2c_c {
246			mux {
247				groups = "i2c_sck_c",
248				      "i2c_sda_c";
249				function = "i2c_c";
250			};
251		};
252
253		eth_pins: eth_c {
254			mux {
255				groups = "eth_mdio",
256				       "eth_mdc",
257				       "eth_clk_rx_clk",
258				       "eth_rx_dv",
259				       "eth_rxd0",
260				       "eth_rxd1",
261				       "eth_rxd2",
262				       "eth_rxd3",
263				       "eth_rgmii_tx_clk",
264				       "eth_tx_en",
265				       "eth_txd0",
266				       "eth_txd1",
267				       "eth_txd2",
268				       "eth_txd3";
269				function = "eth";
270			};
271		};
272
273		pwm_e_pins: pwm_e {
274			mux {
275				groups = "pwm_e";
276				function = "pwm_e";
277			};
278		};
279	};
280
281	eth-phy-mux {
282		compatible = "mdio-mux-mmioreg", "mdio-mux";
283		#address-cells = <1>;
284		#size-cells = <0>;
285		reg = <0x0 0x55c 0x0 0x4>;
286		mux-mask = <0xffffffff>;
287		mdio-parent-bus = <&mdio0>;
288
289		internal_mdio: mdio@e40908ff {
290			reg = <0xe40908ff>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293
294			internal_phy: ethernet-phy@8 {
295				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
296				reg = <8>;
297				max-speed = <100>;
298			};
299		};
300
301		external_mdio: mdio@2009087f {
302			reg = <0x2009087f>;
303			#address-cells = <1>;
304			#size-cells = <0>;
305		};
306	};
307};
308
309&hiubus {
310	clkc: clock-controller@0 {
311		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
312		#clock-cells = <1>;
313		reg = <0x0 0x0 0x0 0x3db>;
314	};
315};
316
317&i2c_A {
318	clocks = <&clkc CLKID_I2C>;
319};
320
321&i2c_B {
322	clocks = <&clkc CLKID_I2C>;
323};
324
325&i2c_C {
326	clocks = <&clkc CLKID_I2C>;
327};
328
329&sd_emmc_a {
330	clocks = <&clkc CLKID_SD_EMMC_A>,
331		 <&xtal>,
332		 <&clkc CLKID_FCLK_DIV2>;
333	clock-names = "core", "clkin0", "clkin1";
334};
335
336&sd_emmc_b {
337	clocks = <&clkc CLKID_SD_EMMC_B>,
338		 <&xtal>,
339		 <&clkc CLKID_FCLK_DIV2>;
340       clock-names = "core", "clkin0", "clkin1";
341};
342
343&sd_emmc_c {
344	clocks = <&clkc CLKID_SD_EMMC_C>,
345		 <&xtal>,
346		 <&clkc CLKID_FCLK_DIV2>;
347	clock-names = "core", "clkin0", "clkin1";
348};
349
350&vpu {
351	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
352};
353