1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * Copyright (c) 2016 Endless Computers, Inc. 9 * Author: Carlo Caione <carlo@endlessm.com> 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 /* 16 MiB reserved for Hardware ROM Firmware */ 27 hwrom_reserved: hwrom@0 { 28 reg = <0x0 0x0 0x0 0x1000000>; 29 no-map; 30 }; 31 32 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 33 secmon_reserved: secmon@10000000 { 34 reg = <0x0 0x10000000 0x0 0x200000>; 35 no-map; 36 }; 37 38 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 39 secmon_reserved_alt: secmon@5000000 { 40 reg = <0x0 0x05000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 linux,cma { 45 compatible = "shared-dma-pool"; 46 reusable; 47 size = <0x0 0x10000000>; 48 alignment = <0x0 0x400000>; 49 linux,cma-default; 50 }; 51 }; 52 53 chosen { 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 simplefb_cvbs: framebuffer-cvbs { 59 compatible = "amlogic,simple-framebuffer", 60 "simple-framebuffer"; 61 amlogic,pipeline = "vpu-cvbs"; 62 power-domains = <&pwrc_vpu>; 63 status = "disabled"; 64 }; 65 66 simplefb_hdmi: framebuffer-hdmi { 67 compatible = "amlogic,simple-framebuffer", 68 "simple-framebuffer"; 69 amlogic,pipeline = "vpu-hdmi"; 70 power-domains = <&pwrc_vpu>; 71 status = "disabled"; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <0x2>; 77 #size-cells = <0x0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x0>; 83 enable-method = "psci"; 84 next-level-cache = <&l2>; 85 clocks = <&scpi_dvfs 0>; 86 }; 87 88 cpu1: cpu@1 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x1>; 92 enable-method = "psci"; 93 next-level-cache = <&l2>; 94 clocks = <&scpi_dvfs 0>; 95 }; 96 97 cpu2: cpu@2 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x2>; 101 enable-method = "psci"; 102 next-level-cache = <&l2>; 103 clocks = <&scpi_dvfs 0>; 104 }; 105 106 cpu3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x3>; 110 enable-method = "psci"; 111 next-level-cache = <&l2>; 112 clocks = <&scpi_dvfs 0>; 113 }; 114 115 l2: l2-cache0 { 116 compatible = "cache"; 117 }; 118 }; 119 120 arm-pmu { 121 compatible = "arm,cortex-a53-pmu"; 122 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 127 }; 128 129 psci { 130 compatible = "arm,psci-0.2"; 131 method = "smc"; 132 }; 133 134 timer { 135 compatible = "arm,armv8-timer"; 136 interrupts = <GIC_PPI 13 137 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 138 <GIC_PPI 14 139 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 140 <GIC_PPI 11 141 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 142 <GIC_PPI 10 143 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 144 }; 145 146 xtal: xtal-clk { 147 compatible = "fixed-clock"; 148 clock-frequency = <24000000>; 149 clock-output-names = "xtal"; 150 #clock-cells = <0>; 151 }; 152 153 firmware { 154 sm: secure-monitor { 155 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 156 }; 157 }; 158 159 efuse: efuse { 160 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 read-only; 164 secure-monitor = <&sm>; 165 166 sn: sn@14 { 167 reg = <0x14 0x10>; 168 }; 169 170 eth_mac: eth_mac@34 { 171 reg = <0x34 0x10>; 172 }; 173 174 bid: bid@46 { 175 reg = <0x46 0x30>; 176 }; 177 }; 178 179 scpi { 180 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 181 mboxes = <&mailbox 1 &mailbox 2>; 182 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 183 184 scpi_clocks: clocks { 185 compatible = "arm,scpi-clocks"; 186 187 scpi_dvfs: scpi_clocks@0 { 188 compatible = "arm,scpi-dvfs-clocks"; 189 #clock-cells = <1>; 190 clock-indices = <0>; 191 clock-output-names = "vcpu"; 192 }; 193 }; 194 195 scpi_sensors: sensors { 196 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 197 #thermal-sensor-cells = <1>; 198 }; 199 }; 200 201 soc { 202 compatible = "simple-bus"; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges; 206 207 cbus: bus@c1100000 { 208 compatible = "simple-bus"; 209 reg = <0x0 0xc1100000 0x0 0x100000>; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 213 214 gpio_intc: interrupt-controller@9880 { 215 compatible = "amlogic,meson-gpio-intc"; 216 reg = <0x0 0x9880 0x0 0x10>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 220 status = "disabled"; 221 }; 222 223 reset: reset-controller@4404 { 224 compatible = "amlogic,meson-gxbb-reset"; 225 reg = <0x0 0x04404 0x0 0x9c>; 226 #reset-cells = <1>; 227 }; 228 229 uart_A: serial@84c0 { 230 compatible = "amlogic,meson-gx-uart"; 231 reg = <0x0 0x84c0 0x0 0x18>; 232 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 233 status = "disabled"; 234 }; 235 236 uart_B: serial@84dc { 237 compatible = "amlogic,meson-gx-uart"; 238 reg = <0x0 0x84dc 0x0 0x18>; 239 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 240 status = "disabled"; 241 }; 242 243 i2c_A: i2c@8500 { 244 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 245 reg = <0x0 0x08500 0x0 0x20>; 246 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 status = "disabled"; 250 }; 251 252 pwm_ab: pwm@8550 { 253 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 254 reg = <0x0 0x08550 0x0 0x10>; 255 #pwm-cells = <3>; 256 status = "disabled"; 257 }; 258 259 pwm_cd: pwm@8650 { 260 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 261 reg = <0x0 0x08650 0x0 0x10>; 262 #pwm-cells = <3>; 263 status = "disabled"; 264 }; 265 266 saradc: adc@8680 { 267 compatible = "amlogic,meson-saradc"; 268 reg = <0x0 0x8680 0x0 0x34>; 269 #io-channel-cells = <1>; 270 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 271 status = "disabled"; 272 }; 273 274 pwm_ef: pwm@86c0 { 275 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 276 reg = <0x0 0x086c0 0x0 0x10>; 277 #pwm-cells = <3>; 278 status = "disabled"; 279 }; 280 281 uart_C: serial@8700 { 282 compatible = "amlogic,meson-gx-uart"; 283 reg = <0x0 0x8700 0x0 0x18>; 284 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 285 status = "disabled"; 286 }; 287 288 clock-measure@8758 { 289 compatible = "amlogic,meson-gx-clk-measure"; 290 reg = <0x0 0x8758 0x0 0x10>; 291 }; 292 293 i2c_B: i2c@87c0 { 294 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 295 reg = <0x0 0x087c0 0x0 0x20>; 296 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 i2c_C: i2c@87e0 { 303 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 304 reg = <0x0 0x087e0 0x0 0x20>; 305 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 spicc: spi@8d80 { 312 compatible = "amlogic,meson-gx-spicc"; 313 reg = <0x0 0x08d80 0x0 0x80>; 314 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 spifc: spi@8c80 { 321 compatible = "amlogic,meson-gxbb-spifc"; 322 reg = <0x0 0x08c80 0x0 0x80>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 watchdog@98d0 { 329 compatible = "amlogic,meson-gxbb-wdt"; 330 reg = <0x0 0x098d0 0x0 0x10>; 331 clocks = <&xtal>; 332 }; 333 }; 334 335 gic: interrupt-controller@c4301000 { 336 compatible = "arm,gic-400"; 337 reg = <0x0 0xc4301000 0 0x1000>, 338 <0x0 0xc4302000 0 0x2000>, 339 <0x0 0xc4304000 0 0x2000>, 340 <0x0 0xc4306000 0 0x2000>; 341 interrupt-controller; 342 interrupts = <GIC_PPI 9 343 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 344 #interrupt-cells = <3>; 345 #address-cells = <0>; 346 }; 347 348 sram: sram@c8000000 { 349 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; 350 reg = <0x0 0xc8000000 0x0 0x14000>; 351 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0 0x0 0xc8000000 0x14000>; 355 356 cpu_scp_lpri: scp-shmem@0 { 357 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 358 reg = <0x13000 0x400>; 359 }; 360 361 cpu_scp_hpri: scp-shmem@200 { 362 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 363 reg = <0x13400 0x400>; 364 }; 365 }; 366 367 aobus: bus@c8100000 { 368 compatible = "simple-bus"; 369 reg = <0x0 0xc8100000 0x0 0x100000>; 370 #address-cells = <2>; 371 #size-cells = <2>; 372 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 373 374 sysctrl_AO: sys-ctrl@0 { 375 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; 376 reg = <0x0 0x0 0x0 0x100>; 377 378 pwrc_vpu: power-controller-vpu { 379 compatible = "amlogic,meson-gx-pwrc-vpu"; 380 #power-domain-cells = <0>; 381 amlogic,hhi-sysctrl = <&sysctrl>; 382 }; 383 384 clkc_AO: clock-controller { 385 compatible = "amlogic,meson-gx-aoclkc"; 386 #clock-cells = <1>; 387 #reset-cells = <1>; 388 }; 389 }; 390 391 cec_AO: cec@100 { 392 compatible = "amlogic,meson-gx-ao-cec"; 393 reg = <0x0 0x00100 0x0 0x14>; 394 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 395 }; 396 397 sec_AO: ao-secure@140 { 398 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 399 reg = <0x0 0x140 0x0 0x140>; 400 amlogic,has-chip-id; 401 }; 402 403 uart_AO: serial@4c0 { 404 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 405 reg = <0x0 0x004c0 0x0 0x18>; 406 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 407 status = "disabled"; 408 }; 409 410 uart_AO_B: serial@4e0 { 411 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 412 reg = <0x0 0x004e0 0x0 0x18>; 413 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 414 status = "disabled"; 415 }; 416 417 i2c_AO: i2c@500 { 418 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 419 reg = <0x0 0x500 0x0 0x20>; 420 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 pwm_AO_ab: pwm@550 { 427 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 428 reg = <0x0 0x00550 0x0 0x10>; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 ir: ir@580 { 434 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 435 reg = <0x0 0x00580 0x0 0x40>; 436 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 437 status = "disabled"; 438 }; 439 }; 440 441 vdec: video-codec@c8820000 { 442 compatible = "amlogic,gx-vdec"; 443 reg = <0x0 0xc8820000 0x0 0x10000>, 444 <0x0 0xc110a580 0x0 0xe4>; 445 reg-names = "dos", "esparser"; 446 447 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 449 interrupt-names = "vdec", "esparser"; 450 451 amlogic,ao-sysctrl = <&sysctrl_AO>; 452 amlogic,canvas = <&canvas>; 453 }; 454 455 periphs: bus@c8834000 { 456 compatible = "simple-bus"; 457 reg = <0x0 0xc8834000 0x0 0x2000>; 458 #address-cells = <2>; 459 #size-cells = <2>; 460 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 461 462 hwrng: rng { 463 compatible = "amlogic,meson-rng"; 464 reg = <0x0 0x0 0x0 0x4>; 465 }; 466 }; 467 468 dmcbus: bus@c8838000 { 469 compatible = "simple-bus"; 470 reg = <0x0 0xc8838000 0x0 0x400>; 471 #address-cells = <2>; 472 #size-cells = <2>; 473 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; 474 475 canvas: video-lut@48 { 476 compatible = "amlogic,canvas"; 477 reg = <0x0 0x48 0x0 0x14>; 478 }; 479 }; 480 481 hiubus: bus@c883c000 { 482 compatible = "simple-bus"; 483 reg = <0x0 0xc883c000 0x0 0x2000>; 484 #address-cells = <2>; 485 #size-cells = <2>; 486 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 487 488 sysctrl: system-controller@0 { 489 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; 490 reg = <0 0 0 0x400>; 491 }; 492 493 mailbox: mailbox@404 { 494 compatible = "amlogic,meson-gxbb-mhu"; 495 reg = <0 0x404 0 0x4c>; 496 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 497 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 498 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 499 #mbox-cells = <1>; 500 }; 501 }; 502 503 ethmac: ethernet@c9410000 { 504 compatible = "amlogic,meson-gxbb-dwmac", 505 "snps,dwmac-3.70a", 506 "snps,dwmac"; 507 reg = <0x0 0xc9410000 0x0 0x10000>, 508 <0x0 0xc8834540 0x0 0x4>; 509 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-names = "macirq"; 511 rx-fifo-depth = <4096>; 512 tx-fifo-depth = <2048>; 513 status = "disabled"; 514 }; 515 516 apb: apb@d0000000 { 517 compatible = "simple-bus"; 518 reg = <0x0 0xd0000000 0x0 0x200000>; 519 #address-cells = <2>; 520 #size-cells = <2>; 521 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 522 523 sd_emmc_a: mmc@70000 { 524 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 525 reg = <0x0 0x70000 0x0 0x800>; 526 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 527 status = "disabled"; 528 }; 529 530 sd_emmc_b: mmc@72000 { 531 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 532 reg = <0x0 0x72000 0x0 0x800>; 533 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 534 status = "disabled"; 535 }; 536 537 sd_emmc_c: mmc@74000 { 538 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 539 reg = <0x0 0x74000 0x0 0x800>; 540 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 541 status = "disabled"; 542 }; 543 }; 544 545 vpu: vpu@d0100000 { 546 compatible = "amlogic,meson-gx-vpu"; 547 reg = <0x0 0xd0100000 0x0 0x100000>, 548 <0x0 0xc883c000 0x0 0x1000>; 549 reg-names = "vpu", "hhi"; 550 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 amlogic,canvas = <&canvas>; 554 555 /* CVBS VDAC output port */ 556 cvbs_vdac_port: port@0 { 557 reg = <0>; 558 }; 559 560 /* HDMI-TX output port */ 561 hdmi_tx_port: port@1 { 562 reg = <1>; 563 564 hdmi_tx_out: endpoint { 565 remote-endpoint = <&hdmi_tx_in>; 566 }; 567 }; 568 }; 569 570 hdmi_tx: hdmi-tx@c883a000 { 571 compatible = "amlogic,meson-gx-dw-hdmi"; 572 reg = <0x0 0xc883a000 0x0 0x1c>; 573 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 578 /* VPU VENC Input */ 579 hdmi_tx_venc_port: port@0 { 580 reg = <0>; 581 582 hdmi_tx_in: endpoint { 583 remote-endpoint = <&hdmi_tx_out>; 584 }; 585 }; 586 587 /* TMDS Output */ 588 hdmi_tx_tmds_port: port@1 { 589 reg = <1>; 590 }; 591 }; 592 }; 593}; 594