1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * Copyright (c) 2016 Endless Computers, Inc. 8 * Author: Carlo Caione <carlo@endlessm.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This library is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This library is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively, 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use, 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49#include <dt-bindings/gpio/gpio.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51#include <dt-bindings/interrupt-controller/arm-gic.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 cpus { 59 #address-cells = <0x2>; 60 #size-cells = <0x0>; 61 62 cpu0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <0x0 0x0>; 66 enable-method = "psci"; 67 next-level-cache = <&l2>; 68 clocks = <&scpi_dvfs 0>; 69 }; 70 71 cpu1: cpu@1 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 reg = <0x0 0x1>; 75 enable-method = "psci"; 76 next-level-cache = <&l2>; 77 clocks = <&scpi_dvfs 0>; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 reg = <0x0 0x2>; 84 enable-method = "psci"; 85 next-level-cache = <&l2>; 86 clocks = <&scpi_dvfs 0>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53", "arm,armv8"; 92 reg = <0x0 0x3>; 93 enable-method = "psci"; 94 next-level-cache = <&l2>; 95 clocks = <&scpi_dvfs 0>; 96 }; 97 98 l2: l2-cache0 { 99 compatible = "cache"; 100 }; 101 }; 102 103 arm-pmu { 104 compatible = "arm,cortex-a53-pmu"; 105 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 110 }; 111 112 psci { 113 compatible = "arm,psci-0.2"; 114 method = "smc"; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <GIC_PPI 13 120 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 14 122 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 123 <GIC_PPI 11 124 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 125 <GIC_PPI 10 126 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 127 }; 128 129 xtal: xtal-clk { 130 compatible = "fixed-clock"; 131 clock-frequency = <24000000>; 132 clock-output-names = "xtal"; 133 #clock-cells = <0>; 134 }; 135 136 firmware { 137 sm: secure-monitor { 138 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 139 }; 140 }; 141 142 efuse: efuse { 143 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 147 sn: sn@14 { 148 reg = <0x14 0x10>; 149 }; 150 151 eth_mac: eth_mac@34 { 152 reg = <0x34 0x10>; 153 }; 154 155 bid: bid@46 { 156 reg = <0x46 0x30>; 157 }; 158 }; 159 160 scpi { 161 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 162 mboxes = <&mailbox 1 &mailbox 2>; 163 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 164 165 scpi_clocks: clocks { 166 compatible = "arm,scpi-clocks"; 167 168 scpi_dvfs: scpi_clocks@0 { 169 compatible = "arm,scpi-dvfs-clocks"; 170 #clock-cells = <1>; 171 clock-indices = <0>; 172 clock-output-names = "vcpu"; 173 }; 174 }; 175 176 scpi_sensors: sensors { 177 compatible = "arm,scpi-sensors"; 178 #thermal-sensor-cells = <1>; 179 }; 180 }; 181 182 soc { 183 compatible = "simple-bus"; 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges; 187 188 cbus: cbus@c1100000 { 189 compatible = "simple-bus"; 190 reg = <0x0 0xc1100000 0x0 0x100000>; 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 194 195 reset: reset-controller@4404 { 196 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; 197 reg = <0x0 0x04404 0x0 0x20>; 198 #reset-cells = <1>; 199 }; 200 201 uart_A: serial@84c0 { 202 compatible = "amlogic,meson-uart"; 203 reg = <0x0 0x84c0 0x0 0x14>; 204 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 205 clocks = <&xtal>; 206 status = "disabled"; 207 }; 208 209 uart_B: serial@84dc { 210 compatible = "amlogic,meson-uart"; 211 reg = <0x0 0x84dc 0x0 0x14>; 212 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 213 clocks = <&xtal>; 214 status = "disabled"; 215 }; 216 217 i2c_A: i2c@8500 { 218 compatible = "amlogic,meson-gxbb-i2c"; 219 reg = <0x0 0x08500 0x0 0x20>; 220 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 pwm_ab: pwm@8550 { 227 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 228 reg = <0x0 0x08550 0x0 0x10>; 229 #pwm-cells = <3>; 230 status = "disabled"; 231 }; 232 233 pwm_cd: pwm@8650 { 234 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 235 reg = <0x0 0x08650 0x0 0x10>; 236 #pwm-cells = <3>; 237 status = "disabled"; 238 }; 239 240 saradc: adc@8680 { 241 compatible = "amlogic,meson-saradc"; 242 reg = <0x0 0x8680 0x0 0x34>; 243 #io-channel-cells = <1>; 244 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 245 status = "disabled"; 246 }; 247 248 pwm_ef: pwm@86c0 { 249 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 250 reg = <0x0 0x086c0 0x0 0x10>; 251 #pwm-cells = <3>; 252 status = "disabled"; 253 }; 254 255 uart_C: serial@8700 { 256 compatible = "amlogic,meson-uart"; 257 reg = <0x0 0x8700 0x0 0x14>; 258 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 259 clocks = <&xtal>; 260 status = "disabled"; 261 }; 262 263 i2c_B: i2c@87c0 { 264 compatible = "amlogic,meson-gxbb-i2c"; 265 reg = <0x0 0x087c0 0x0 0x20>; 266 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 status = "disabled"; 270 }; 271 272 i2c_C: i2c@87e0 { 273 compatible = "amlogic,meson-gxbb-i2c"; 274 reg = <0x0 0x087e0 0x0 0x20>; 275 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 watchdog@98d0 { 282 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; 283 reg = <0x0 0x098d0 0x0 0x10>; 284 clocks = <&xtal>; 285 }; 286 }; 287 288 gic: interrupt-controller@c4301000 { 289 compatible = "arm,gic-400"; 290 reg = <0x0 0xc4301000 0 0x1000>, 291 <0x0 0xc4302000 0 0x2000>, 292 <0x0 0xc4304000 0 0x2000>, 293 <0x0 0xc4306000 0 0x2000>; 294 interrupt-controller; 295 interrupts = <GIC_PPI 9 296 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 297 #interrupt-cells = <3>; 298 #address-cells = <0>; 299 }; 300 301 sram: sram@c8000000 { 302 compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; 303 reg = <0x0 0xc8000000 0x0 0x14000>; 304 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges = <0 0x0 0xc8000000 0x14000>; 308 309 cpu_scp_lpri: scp-shmem@0 { 310 compatible = "amlogic,meson-gxbb-scp-shmem"; 311 reg = <0x13000 0x400>; 312 }; 313 314 cpu_scp_hpri: scp-shmem@200 { 315 compatible = "amlogic,meson-gxbb-scp-shmem"; 316 reg = <0x13400 0x400>; 317 }; 318 }; 319 320 aobus: aobus@c8100000 { 321 compatible = "simple-bus"; 322 reg = <0x0 0xc8100000 0x0 0x100000>; 323 #address-cells = <2>; 324 #size-cells = <2>; 325 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 326 327 uart_AO: serial@4c0 { 328 compatible = "amlogic,meson-uart"; 329 reg = <0x0 0x004c0 0x0 0x14>; 330 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 331 clocks = <&xtal>; 332 status = "disabled"; 333 }; 334 335 uart_AO_B: serial@4e0 { 336 compatible = "amlogic,meson-uart"; 337 reg = <0x0 0x004e0 0x0 0x14>; 338 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 339 clocks = <&xtal>; 340 status = "disabled"; 341 }; 342 343 pwm_AO_ab: pwm@550 { 344 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 345 reg = <0x0 0x00550 0x0 0x10>; 346 #pwm-cells = <3>; 347 status = "disabled"; 348 }; 349 350 ir: ir@580 { 351 compatible = "amlogic,meson-gxbb-ir"; 352 reg = <0x0 0x00580 0x0 0x40>; 353 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 354 status = "disabled"; 355 }; 356 }; 357 358 periphs: periphs@c8834000 { 359 compatible = "simple-bus"; 360 reg = <0x0 0xc8834000 0x0 0x2000>; 361 #address-cells = <2>; 362 #size-cells = <2>; 363 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 364 365 rng { 366 compatible = "amlogic,meson-rng"; 367 reg = <0x0 0x0 0x0 0x4>; 368 }; 369 }; 370 371 372 hiubus: hiubus@c883c000 { 373 compatible = "simple-bus"; 374 reg = <0x0 0xc883c000 0x0 0x2000>; 375 #address-cells = <2>; 376 #size-cells = <2>; 377 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 378 379 mailbox: mailbox@404 { 380 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 381 reg = <0 0x404 0 0x4c>; 382 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, 383 <0 209 IRQ_TYPE_EDGE_RISING>, 384 <0 210 IRQ_TYPE_EDGE_RISING>; 385 #mbox-cells = <1>; 386 }; 387 }; 388 389 ethmac: ethernet@c9410000 { 390 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 391 reg = <0x0 0xc9410000 0x0 0x10000 392 0x0 0xc8834540 0x0 0x4>; 393 interrupts = <0 8 1>; 394 interrupt-names = "macirq"; 395 phy-mode = "rgmii"; 396 status = "disabled"; 397 }; 398 399 apb: apb@d0000000 { 400 compatible = "simple-bus"; 401 reg = <0x0 0xd0000000 0x0 0x200000>; 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 405 406 sd_emmc_a: mmc@70000 { 407 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 408 reg = <0x0 0x70000 0x0 0x2000>; 409 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 410 status = "disabled"; 411 }; 412 413 sd_emmc_b: mmc@72000 { 414 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 415 reg = <0x0 0x72000 0x0 0x2000>; 416 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 417 status = "disabled"; 418 }; 419 420 sd_emmc_c: mmc@74000 { 421 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 422 reg = <0x0 0x74000 0x0 0x2000>; 423 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 424 status = "disabled"; 425 }; 426 }; 427 428 vpu: vpu@d0100000 { 429 compatible = "amlogic,meson-gx-vpu"; 430 reg = <0x0 0xd0100000 0x0 0x100000>, 431 <0x0 0xc883c000 0x0 0x1000>, 432 <0x0 0xc8838000 0x0 0x1000>; 433 reg-names = "vpu", "hhi", "dmc"; 434 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 /* CVBS VDAC output port */ 439 cvbs_vdac_port: port@0 { 440 reg = <0>; 441 }; 442 }; 443 }; 444}; 445