1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * Copyright (c) 2016 Endless Computers, Inc. 8 * Author: Carlo Caione <carlo@endlessm.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This library is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This library is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively, 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use, 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49#include <dt-bindings/gpio/gpio.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51#include <dt-bindings/interrupt-controller/arm-gic.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 reserved-memory { 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 63 /* 16 MiB reserved for Hardware ROM Firmware */ 64 hwrom_reserved: hwrom@0 { 65 reg = <0x0 0x0 0x0 0x1000000>; 66 no-map; 67 }; 68 69 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 70 secmon_reserved: secmon@10000000 { 71 reg = <0x0 0x10000000 0x0 0x200000>; 72 no-map; 73 }; 74 75 linux,cma { 76 compatible = "shared-dma-pool"; 77 reusable; 78 size = <0x0 0xbc00000>; 79 alignment = <0x0 0x400000>; 80 linux,cma-default; 81 }; 82 }; 83 84 cpus { 85 #address-cells = <0x2>; 86 #size-cells = <0x0>; 87 88 cpu0: cpu@0 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53", "arm,armv8"; 91 reg = <0x0 0x0>; 92 enable-method = "psci"; 93 next-level-cache = <&l2>; 94 clocks = <&scpi_dvfs 0>; 95 }; 96 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 reg = <0x0 0x1>; 101 enable-method = "psci"; 102 next-level-cache = <&l2>; 103 clocks = <&scpi_dvfs 0>; 104 }; 105 106 cpu2: cpu@2 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x2>; 110 enable-method = "psci"; 111 next-level-cache = <&l2>; 112 clocks = <&scpi_dvfs 0>; 113 }; 114 115 cpu3: cpu@3 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53", "arm,armv8"; 118 reg = <0x0 0x3>; 119 enable-method = "psci"; 120 next-level-cache = <&l2>; 121 clocks = <&scpi_dvfs 0>; 122 }; 123 124 l2: l2-cache0 { 125 compatible = "cache"; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a53-pmu"; 131 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 psci { 139 compatible = "arm,psci-0.2"; 140 method = "smc"; 141 }; 142 143 timer { 144 compatible = "arm,armv8-timer"; 145 interrupts = <GIC_PPI 13 146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 147 <GIC_PPI 14 148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 11 150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 152 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 153 }; 154 155 xtal: xtal-clk { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xtal"; 159 #clock-cells = <0>; 160 }; 161 162 firmware { 163 sm: secure-monitor { 164 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 165 }; 166 }; 167 168 efuse: efuse { 169 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 173 sn: sn@14 { 174 reg = <0x14 0x10>; 175 }; 176 177 eth_mac: eth_mac@34 { 178 reg = <0x34 0x10>; 179 }; 180 181 bid: bid@46 { 182 reg = <0x46 0x30>; 183 }; 184 }; 185 186 scpi { 187 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 188 mboxes = <&mailbox 1 &mailbox 2>; 189 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 190 191 scpi_clocks: clocks { 192 compatible = "arm,scpi-clocks"; 193 194 scpi_dvfs: scpi_clocks@0 { 195 compatible = "arm,scpi-dvfs-clocks"; 196 #clock-cells = <1>; 197 clock-indices = <0>; 198 clock-output-names = "vcpu"; 199 }; 200 }; 201 202 scpi_sensors: sensors { 203 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 204 #thermal-sensor-cells = <1>; 205 }; 206 }; 207 208 soc { 209 compatible = "simple-bus"; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges; 213 214 cbus: cbus@c1100000 { 215 compatible = "simple-bus"; 216 reg = <0x0 0xc1100000 0x0 0x100000>; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 220 221 reset: reset-controller@4404 { 222 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; 223 reg = <0x0 0x04404 0x0 0x20>; 224 #reset-cells = <1>; 225 }; 226 227 uart_A: serial@84c0 { 228 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 229 reg = <0x0 0x84c0 0x0 0x14>; 230 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 231 status = "disabled"; 232 }; 233 234 uart_B: serial@84dc { 235 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 236 reg = <0x0 0x84dc 0x0 0x14>; 237 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 238 status = "disabled"; 239 }; 240 241 i2c_A: i2c@8500 { 242 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 243 reg = <0x0 0x08500 0x0 0x20>; 244 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 }; 249 250 pwm_ab: pwm@8550 { 251 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 252 reg = <0x0 0x08550 0x0 0x10>; 253 #pwm-cells = <3>; 254 status = "disabled"; 255 }; 256 257 pwm_cd: pwm@8650 { 258 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 259 reg = <0x0 0x08650 0x0 0x10>; 260 #pwm-cells = <3>; 261 status = "disabled"; 262 }; 263 264 saradc: adc@8680 { 265 compatible = "amlogic,meson-saradc"; 266 reg = <0x0 0x8680 0x0 0x34>; 267 #io-channel-cells = <1>; 268 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 269 status = "disabled"; 270 }; 271 272 pwm_ef: pwm@86c0 { 273 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 274 reg = <0x0 0x086c0 0x0 0x10>; 275 #pwm-cells = <3>; 276 status = "disabled"; 277 }; 278 279 uart_C: serial@8700 { 280 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 281 reg = <0x0 0x8700 0x0 0x14>; 282 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 283 status = "disabled"; 284 }; 285 286 i2c_B: i2c@87c0 { 287 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 288 reg = <0x0 0x087c0 0x0 0x20>; 289 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 status = "disabled"; 293 }; 294 295 i2c_C: i2c@87e0 { 296 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 297 reg = <0x0 0x087e0 0x0 0x20>; 298 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 spicc: spi@8d80 { 305 compatible = "amlogic,meson-gx-spicc"; 306 reg = <0x0 0x08d80 0x0 0x80>; 307 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 spifc: spi@8c80 { 314 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; 315 reg = <0x0 0x08c80 0x0 0x80>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 321 watchdog@98d0 { 322 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; 323 reg = <0x0 0x098d0 0x0 0x10>; 324 clocks = <&xtal>; 325 }; 326 }; 327 328 gic: interrupt-controller@c4301000 { 329 compatible = "arm,gic-400"; 330 reg = <0x0 0xc4301000 0 0x1000>, 331 <0x0 0xc4302000 0 0x2000>, 332 <0x0 0xc4304000 0 0x2000>, 333 <0x0 0xc4306000 0 0x2000>; 334 interrupt-controller; 335 interrupts = <GIC_PPI 9 336 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 337 #interrupt-cells = <3>; 338 #address-cells = <0>; 339 }; 340 341 sram: sram@c8000000 { 342 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; 343 reg = <0x0 0xc8000000 0x0 0x14000>; 344 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges = <0 0x0 0xc8000000 0x14000>; 348 349 cpu_scp_lpri: scp-shmem@0 { 350 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 351 reg = <0x13000 0x400>; 352 }; 353 354 cpu_scp_hpri: scp-shmem@200 { 355 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 356 reg = <0x13400 0x400>; 357 }; 358 }; 359 360 aobus: aobus@c8100000 { 361 compatible = "simple-bus"; 362 reg = <0x0 0xc8100000 0x0 0x100000>; 363 #address-cells = <2>; 364 #size-cells = <2>; 365 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 366 367 sysctrl_AO: sys-ctrl@0 { 368 compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 369 reg = <0x0 0x0 0x0 0x100>; 370 371 clkc_AO: clock-controller { 372 compatible = "amlogic,meson-gx-aoclkc"; 373 #clock-cells = <1>; 374 #reset-cells = <1>; 375 }; 376 }; 377 378 cec_AO: cec@100 { 379 compatible = "amlogic,meson-gx-ao-cec"; 380 reg = <0x0 0x00100 0x0 0x14>; 381 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 382 }; 383 384 sec_AO: ao-secure@140 { 385 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 386 reg = <0x0 0x140 0x0 0x140>; 387 amlogic,has-chip-id; 388 }; 389 390 uart_AO: serial@4c0 { 391 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; 392 reg = <0x0 0x004c0 0x0 0x14>; 393 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 394 status = "disabled"; 395 }; 396 397 uart_AO_B: serial@4e0 { 398 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; 399 reg = <0x0 0x004e0 0x0 0x14>; 400 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 401 status = "disabled"; 402 }; 403 404 i2c_AO: i2c@500 { 405 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 406 reg = <0x0 0x500 0x0 0x20>; 407 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 pwm_AO_ab: pwm@550 { 414 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 415 reg = <0x0 0x00550 0x0 0x10>; 416 #pwm-cells = <3>; 417 status = "disabled"; 418 }; 419 420 ir: ir@580 { 421 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 422 reg = <0x0 0x00580 0x0 0x40>; 423 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 424 status = "disabled"; 425 }; 426 }; 427 428 periphs: periphs@c8834000 { 429 compatible = "simple-bus"; 430 reg = <0x0 0xc8834000 0x0 0x2000>; 431 #address-cells = <2>; 432 #size-cells = <2>; 433 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 434 435 hwrng: rng { 436 compatible = "amlogic,meson-rng"; 437 reg = <0x0 0x0 0x0 0x4>; 438 }; 439 }; 440 441 hiubus: hiubus@c883c000 { 442 compatible = "simple-bus"; 443 reg = <0x0 0xc883c000 0x0 0x2000>; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 447 448 mailbox: mailbox@404 { 449 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 450 reg = <0 0x404 0 0x4c>; 451 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 454 #mbox-cells = <1>; 455 }; 456 }; 457 458 ethmac: ethernet@c9410000 { 459 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 460 reg = <0x0 0xc9410000 0x0 0x10000 461 0x0 0xc8834540 0x0 0x4>; 462 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 463 interrupt-names = "macirq"; 464 status = "disabled"; 465 }; 466 467 apb: apb@d0000000 { 468 compatible = "simple-bus"; 469 reg = <0x0 0xd0000000 0x0 0x200000>; 470 #address-cells = <2>; 471 #size-cells = <2>; 472 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 473 474 sd_emmc_a: mmc@70000 { 475 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 476 reg = <0x0 0x70000 0x0 0x2000>; 477 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 478 status = "disabled"; 479 }; 480 481 sd_emmc_b: mmc@72000 { 482 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 483 reg = <0x0 0x72000 0x0 0x2000>; 484 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 485 status = "disabled"; 486 }; 487 488 sd_emmc_c: mmc@74000 { 489 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 490 reg = <0x0 0x74000 0x0 0x2000>; 491 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 492 status = "disabled"; 493 }; 494 }; 495 496 vpu: vpu@d0100000 { 497 compatible = "amlogic,meson-gx-vpu"; 498 reg = <0x0 0xd0100000 0x0 0x100000>, 499 <0x0 0xc883c000 0x0 0x1000>, 500 <0x0 0xc8838000 0x0 0x1000>; 501 reg-names = "vpu", "hhi", "dmc"; 502 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 /* CVBS VDAC output port */ 507 cvbs_vdac_port: port@0 { 508 reg = <0>; 509 }; 510 511 /* HDMI-TX output port */ 512 hdmi_tx_port: port@1 { 513 reg = <1>; 514 515 hdmi_tx_out: endpoint { 516 remote-endpoint = <&hdmi_tx_in>; 517 }; 518 }; 519 }; 520 521 hdmi_tx: hdmi-tx@c883a000 { 522 compatible = "amlogic,meson-gx-dw-hdmi"; 523 reg = <0x0 0xc883a000 0x0 0x1c>; 524 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 529 /* VPU VENC Input */ 530 hdmi_tx_venc_port: port@0 { 531 reg = <0>; 532 533 hdmi_tx_in: endpoint { 534 remote-endpoint = <&hdmi_tx_out>; 535 }; 536 }; 537 538 /* TMDS Output */ 539 hdmi_tx_tmds_port: port@1 { 540 reg = <1>; 541 }; 542 }; 543 }; 544}; 545