1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * Copyright (c) 2016 Endless Computers, Inc. 8 * Author: Carlo Caione <carlo@endlessm.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This library is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This library is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively, 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use, 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49#include <dt-bindings/gpio/gpio.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51#include <dt-bindings/interrupt-controller/arm-gic.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 reserved-memory { 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 63 /* 16 MiB reserved for Hardware ROM Firmware */ 64 hwrom_reserved: hwrom@0 { 65 reg = <0x0 0x0 0x0 0x1000000>; 66 no-map; 67 }; 68 69 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 70 secmon_reserved: secmon@10000000 { 71 reg = <0x0 0x10000000 0x0 0x200000>; 72 no-map; 73 }; 74 75 linux,cma { 76 compatible = "shared-dma-pool"; 77 reusable; 78 size = <0x0 0xbc00000>; 79 alignment = <0x0 0x400000>; 80 linux,cma-default; 81 }; 82 }; 83 84 cpus { 85 #address-cells = <0x2>; 86 #size-cells = <0x0>; 87 88 cpu0: cpu@0 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53", "arm,armv8"; 91 reg = <0x0 0x0>; 92 enable-method = "psci"; 93 next-level-cache = <&l2>; 94 clocks = <&scpi_dvfs 0>; 95 }; 96 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 reg = <0x0 0x1>; 101 enable-method = "psci"; 102 next-level-cache = <&l2>; 103 clocks = <&scpi_dvfs 0>; 104 }; 105 106 cpu2: cpu@2 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x2>; 110 enable-method = "psci"; 111 next-level-cache = <&l2>; 112 clocks = <&scpi_dvfs 0>; 113 }; 114 115 cpu3: cpu@3 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53", "arm,armv8"; 118 reg = <0x0 0x3>; 119 enable-method = "psci"; 120 next-level-cache = <&l2>; 121 clocks = <&scpi_dvfs 0>; 122 }; 123 124 l2: l2-cache0 { 125 compatible = "cache"; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a53-pmu"; 131 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 psci { 139 compatible = "arm,psci-0.2"; 140 method = "smc"; 141 }; 142 143 timer { 144 compatible = "arm,armv8-timer"; 145 interrupts = <GIC_PPI 13 146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 147 <GIC_PPI 14 148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 11 150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 152 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 153 }; 154 155 xtal: xtal-clk { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xtal"; 159 #clock-cells = <0>; 160 }; 161 162 firmware { 163 sm: secure-monitor { 164 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 165 }; 166 }; 167 168 efuse: efuse { 169 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 173 sn: sn@14 { 174 reg = <0x14 0x10>; 175 }; 176 177 eth_mac: eth_mac@34 { 178 reg = <0x34 0x10>; 179 }; 180 181 bid: bid@46 { 182 reg = <0x46 0x30>; 183 }; 184 }; 185 186 scpi { 187 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 188 mboxes = <&mailbox 1 &mailbox 2>; 189 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 190 191 scpi_clocks: clocks { 192 compatible = "arm,scpi-clocks"; 193 194 scpi_dvfs: scpi_clocks@0 { 195 compatible = "arm,scpi-dvfs-clocks"; 196 #clock-cells = <1>; 197 clock-indices = <0>; 198 clock-output-names = "vcpu"; 199 }; 200 }; 201 202 scpi_sensors: sensors { 203 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 204 #thermal-sensor-cells = <1>; 205 }; 206 }; 207 208 soc { 209 compatible = "simple-bus"; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges; 213 214 cbus: cbus@c1100000 { 215 compatible = "simple-bus"; 216 reg = <0x0 0xc1100000 0x0 0x100000>; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 220 221 gpio_intc: interrupt-controller@9880 { 222 compatible = "amlogic,meson-gpio-intc"; 223 reg = <0x0 0x9880 0x0 0x10>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 227 status = "disabled"; 228 }; 229 230 reset: reset-controller@4404 { 231 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; 232 reg = <0x0 0x04404 0x0 0x20>; 233 #reset-cells = <1>; 234 }; 235 236 uart_A: serial@84c0 { 237 compatible = "amlogic,meson-gx-uart"; 238 reg = <0x0 0x84c0 0x0 0x14>; 239 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 240 status = "disabled"; 241 }; 242 243 uart_B: serial@84dc { 244 compatible = "amlogic,meson-gx-uart"; 245 reg = <0x0 0x84dc 0x0 0x14>; 246 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 247 status = "disabled"; 248 }; 249 250 i2c_A: i2c@8500 { 251 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 252 reg = <0x0 0x08500 0x0 0x20>; 253 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 status = "disabled"; 257 }; 258 259 pwm_ab: pwm@8550 { 260 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 261 reg = <0x0 0x08550 0x0 0x10>; 262 #pwm-cells = <3>; 263 status = "disabled"; 264 }; 265 266 pwm_cd: pwm@8650 { 267 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 268 reg = <0x0 0x08650 0x0 0x10>; 269 #pwm-cells = <3>; 270 status = "disabled"; 271 }; 272 273 saradc: adc@8680 { 274 compatible = "amlogic,meson-saradc"; 275 reg = <0x0 0x8680 0x0 0x34>; 276 #io-channel-cells = <1>; 277 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 278 status = "disabled"; 279 }; 280 281 pwm_ef: pwm@86c0 { 282 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 283 reg = <0x0 0x086c0 0x0 0x10>; 284 #pwm-cells = <3>; 285 status = "disabled"; 286 }; 287 288 uart_C: serial@8700 { 289 compatible = "amlogic,meson-gx-uart"; 290 reg = <0x0 0x8700 0x0 0x14>; 291 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 292 status = "disabled"; 293 }; 294 295 i2c_B: i2c@87c0 { 296 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 297 reg = <0x0 0x087c0 0x0 0x20>; 298 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 i2c_C: i2c@87e0 { 305 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 306 reg = <0x0 0x087e0 0x0 0x20>; 307 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 spicc: spi@8d80 { 314 compatible = "amlogic,meson-gx-spicc"; 315 reg = <0x0 0x08d80 0x0 0x80>; 316 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 status = "disabled"; 320 }; 321 322 spifc: spi@8c80 { 323 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; 324 reg = <0x0 0x08c80 0x0 0x80>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 watchdog@98d0 { 331 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; 332 reg = <0x0 0x098d0 0x0 0x10>; 333 clocks = <&xtal>; 334 }; 335 }; 336 337 gic: interrupt-controller@c4301000 { 338 compatible = "arm,gic-400"; 339 reg = <0x0 0xc4301000 0 0x1000>, 340 <0x0 0xc4302000 0 0x2000>, 341 <0x0 0xc4304000 0 0x2000>, 342 <0x0 0xc4306000 0 0x2000>; 343 interrupt-controller; 344 interrupts = <GIC_PPI 9 345 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 346 #interrupt-cells = <3>; 347 #address-cells = <0>; 348 }; 349 350 sram: sram@c8000000 { 351 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; 352 reg = <0x0 0xc8000000 0x0 0x14000>; 353 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0 0x0 0xc8000000 0x14000>; 357 358 cpu_scp_lpri: scp-shmem@0 { 359 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 360 reg = <0x13000 0x400>; 361 }; 362 363 cpu_scp_hpri: scp-shmem@200 { 364 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 365 reg = <0x13400 0x400>; 366 }; 367 }; 368 369 aobus: aobus@c8100000 { 370 compatible = "simple-bus"; 371 reg = <0x0 0xc8100000 0x0 0x100000>; 372 #address-cells = <2>; 373 #size-cells = <2>; 374 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 375 376 sysctrl_AO: sys-ctrl@0 { 377 compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 378 reg = <0x0 0x0 0x0 0x100>; 379 380 clkc_AO: clock-controller { 381 compatible = "amlogic,meson-gx-aoclkc"; 382 #clock-cells = <1>; 383 #reset-cells = <1>; 384 }; 385 }; 386 387 cec_AO: cec@100 { 388 compatible = "amlogic,meson-gx-ao-cec"; 389 reg = <0x0 0x00100 0x0 0x14>; 390 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 391 }; 392 393 sec_AO: ao-secure@140 { 394 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 395 reg = <0x0 0x140 0x0 0x140>; 396 amlogic,has-chip-id; 397 }; 398 399 uart_AO: serial@4c0 { 400 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 401 reg = <0x0 0x004c0 0x0 0x14>; 402 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 403 status = "disabled"; 404 }; 405 406 uart_AO_B: serial@4e0 { 407 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 408 reg = <0x0 0x004e0 0x0 0x14>; 409 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 410 status = "disabled"; 411 }; 412 413 i2c_AO: i2c@500 { 414 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 415 reg = <0x0 0x500 0x0 0x20>; 416 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 pwm_AO_ab: pwm@550 { 423 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 424 reg = <0x0 0x00550 0x0 0x10>; 425 #pwm-cells = <3>; 426 status = "disabled"; 427 }; 428 429 ir: ir@580 { 430 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 431 reg = <0x0 0x00580 0x0 0x40>; 432 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 433 status = "disabled"; 434 }; 435 }; 436 437 periphs: periphs@c8834000 { 438 compatible = "simple-bus"; 439 reg = <0x0 0xc8834000 0x0 0x2000>; 440 #address-cells = <2>; 441 #size-cells = <2>; 442 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 443 444 hwrng: rng { 445 compatible = "amlogic,meson-rng"; 446 reg = <0x0 0x0 0x0 0x4>; 447 }; 448 }; 449 450 hiubus: hiubus@c883c000 { 451 compatible = "simple-bus"; 452 reg = <0x0 0xc883c000 0x0 0x2000>; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 456 457 mailbox: mailbox@404 { 458 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 459 reg = <0 0x404 0 0x4c>; 460 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 461 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 463 #mbox-cells = <1>; 464 }; 465 }; 466 467 ethmac: ethernet@c9410000 { 468 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 469 reg = <0x0 0xc9410000 0x0 0x10000 470 0x0 0xc8834540 0x0 0x4>; 471 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 472 interrupt-names = "macirq"; 473 status = "disabled"; 474 }; 475 476 apb: apb@d0000000 { 477 compatible = "simple-bus"; 478 reg = <0x0 0xd0000000 0x0 0x200000>; 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 482 483 sd_emmc_a: mmc@70000 { 484 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 485 reg = <0x0 0x70000 0x0 0x2000>; 486 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 487 status = "disabled"; 488 }; 489 490 sd_emmc_b: mmc@72000 { 491 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 492 reg = <0x0 0x72000 0x0 0x2000>; 493 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 494 status = "disabled"; 495 }; 496 497 sd_emmc_c: mmc@74000 { 498 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 499 reg = <0x0 0x74000 0x0 0x2000>; 500 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 501 status = "disabled"; 502 }; 503 }; 504 505 vpu: vpu@d0100000 { 506 compatible = "amlogic,meson-gx-vpu"; 507 reg = <0x0 0xd0100000 0x0 0x100000>, 508 <0x0 0xc883c000 0x0 0x1000>, 509 <0x0 0xc8838000 0x0 0x1000>; 510 reg-names = "vpu", "hhi", "dmc"; 511 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 /* CVBS VDAC output port */ 516 cvbs_vdac_port: port@0 { 517 reg = <0>; 518 }; 519 520 /* HDMI-TX output port */ 521 hdmi_tx_port: port@1 { 522 reg = <1>; 523 524 hdmi_tx_out: endpoint { 525 remote-endpoint = <&hdmi_tx_in>; 526 }; 527 }; 528 }; 529 530 hdmi_tx: hdmi-tx@c883a000 { 531 compatible = "amlogic,meson-gx-dw-hdmi"; 532 reg = <0x0 0xc883a000 0x0 0x1c>; 533 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 538 /* VPU VENC Input */ 539 hdmi_tx_venc_port: port@0 { 540 reg = <0>; 541 542 hdmi_tx_in: endpoint { 543 remote-endpoint = <&hdmi_tx_out>; 544 }; 545 }; 546 547 /* TMDS Output */ 548 hdmi_tx_tmds_port: port@1 { 549 reg = <1>; 550 }; 551 }; 552 }; 553}; 554