1/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Copyright (c) 2016 Endless Computers, Inc.
8 * Author: Carlo Caione <carlo@endlessm.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 *  a) This library is free software; you can redistribute it and/or
16 *     modify it under the terms of the GNU General Public License as
17 *     published by the Free Software Foundation; either version 2 of the
18 *     License, or (at your option) any later version.
19 *
20 *     This library is distributed in the hope that it will be useful,
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively,
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use,
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include <dt-bindings/gpio/gpio.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/interrupt-controller/arm-gic.h>
52
53/ {
54	interrupt-parent = <&gic>;
55	#address-cells = <2>;
56	#size-cells = <2>;
57
58	reserved-memory {
59		#address-cells = <2>;
60		#size-cells = <2>;
61		ranges;
62
63		/* 16 MiB reserved for Hardware ROM Firmware */
64		hwrom_reserved: hwrom@0 {
65			reg = <0x0 0x0 0x0 0x1000000>;
66			no-map;
67		};
68
69		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
70		secmon_reserved: secmon@10000000 {
71			reg = <0x0 0x10000000 0x0 0x200000>;
72			no-map;
73		};
74
75		linux,cma {
76			compatible = "shared-dma-pool";
77			reusable;
78			size = <0x0 0xbc00000>;
79			alignment = <0x0 0x400000>;
80			linux,cma-default;
81		};
82	};
83
84	cpus {
85		#address-cells = <0x2>;
86		#size-cells = <0x0>;
87
88		cpu0: cpu@0 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53", "arm,armv8";
91			reg = <0x0 0x0>;
92			enable-method = "psci";
93			next-level-cache = <&l2>;
94			clocks = <&scpi_dvfs 0>;
95		};
96
97		cpu1: cpu@1 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53", "arm,armv8";
100			reg = <0x0 0x1>;
101			enable-method = "psci";
102			next-level-cache = <&l2>;
103			clocks = <&scpi_dvfs 0>;
104		};
105
106		cpu2: cpu@2 {
107			device_type = "cpu";
108			compatible = "arm,cortex-a53", "arm,armv8";
109			reg = <0x0 0x2>;
110			enable-method = "psci";
111			next-level-cache = <&l2>;
112			clocks = <&scpi_dvfs 0>;
113		};
114
115		cpu3: cpu@3 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a53", "arm,armv8";
118			reg = <0x0 0x3>;
119			enable-method = "psci";
120			next-level-cache = <&l2>;
121			clocks = <&scpi_dvfs 0>;
122		};
123
124		l2: l2-cache0 {
125			compatible = "cache";
126		};
127	};
128
129	arm-pmu {
130		compatible = "arm,cortex-a53-pmu";
131		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
132			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
133			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
134			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
135		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
136	};
137
138	psci {
139		compatible = "arm,psci-0.2";
140		method = "smc";
141	};
142
143	timer {
144		compatible = "arm,armv8-timer";
145		interrupts = <GIC_PPI 13
146			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
147			     <GIC_PPI 14
148			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
149			     <GIC_PPI 11
150			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
151			     <GIC_PPI 10
152			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
153	};
154
155	xtal: xtal-clk {
156		compatible = "fixed-clock";
157		clock-frequency = <24000000>;
158		clock-output-names = "xtal";
159		#clock-cells = <0>;
160	};
161
162	firmware {
163		sm: secure-monitor {
164			compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
165		};
166	};
167
168	efuse: efuse {
169		compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
170		#address-cells = <1>;
171		#size-cells = <1>;
172
173		sn: sn@14 {
174			reg = <0x14 0x10>;
175		};
176
177		eth_mac: eth_mac@34 {
178			reg = <0x34 0x10>;
179		};
180
181		bid: bid@46 {
182			reg = <0x46 0x30>;
183		};
184	};
185
186	scpi {
187		compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
188		mboxes = <&mailbox 1 &mailbox 2>;
189		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
190
191		scpi_clocks: clocks {
192			compatible = "arm,scpi-clocks";
193
194			scpi_dvfs: scpi_clocks@0 {
195				compatible = "arm,scpi-dvfs-clocks";
196				#clock-cells = <1>;
197				clock-indices = <0>;
198				clock-output-names = "vcpu";
199			};
200		};
201
202		scpi_sensors: sensors {
203			compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
204			#thermal-sensor-cells = <1>;
205		};
206	};
207
208	soc {
209		compatible = "simple-bus";
210		#address-cells = <2>;
211		#size-cells = <2>;
212		ranges;
213
214		cbus: cbus@c1100000 {
215			compatible = "simple-bus";
216			reg = <0x0 0xc1100000 0x0 0x100000>;
217			#address-cells = <2>;
218			#size-cells = <2>;
219			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
220
221			reset: reset-controller@4404 {
222				compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
223				reg = <0x0 0x04404 0x0 0x20>;
224				#reset-cells = <1>;
225			};
226
227			uart_A: serial@84c0 {
228				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
229				reg = <0x0 0x84c0 0x0 0x14>;
230				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
231				clocks = <&xtal>;
232				status = "disabled";
233			};
234
235			uart_B: serial@84dc {
236				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
237				reg = <0x0 0x84dc 0x0 0x14>;
238				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
239				clocks = <&xtal>;
240				status = "disabled";
241			};
242
243			i2c_A: i2c@8500 {
244				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
245				reg = <0x0 0x08500 0x0 0x20>;
246				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
247				#address-cells = <1>;
248				#size-cells = <0>;
249				status = "disabled";
250			};
251
252			pwm_ab: pwm@8550 {
253				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
254				reg = <0x0 0x08550 0x0 0x10>;
255				#pwm-cells = <3>;
256				status = "disabled";
257			};
258
259			pwm_cd: pwm@8650 {
260				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
261				reg = <0x0 0x08650 0x0 0x10>;
262				#pwm-cells = <3>;
263				status = "disabled";
264			};
265
266			saradc: adc@8680 {
267				compatible = "amlogic,meson-saradc";
268				reg = <0x0 0x8680 0x0 0x34>;
269				#io-channel-cells = <1>;
270				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
271				status = "disabled";
272			};
273
274			pwm_ef: pwm@86c0 {
275				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
276				reg = <0x0 0x086c0 0x0 0x10>;
277				#pwm-cells = <3>;
278				status = "disabled";
279			};
280
281			uart_C: serial@8700 {
282				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
283				reg = <0x0 0x8700 0x0 0x14>;
284				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
285				clocks = <&xtal>;
286				status = "disabled";
287			};
288
289			i2c_B: i2c@87c0 {
290				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
291				reg = <0x0 0x087c0 0x0 0x20>;
292				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
293				#address-cells = <1>;
294				#size-cells = <0>;
295				status = "disabled";
296			};
297
298			i2c_C: i2c@87e0 {
299				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
300				reg = <0x0 0x087e0 0x0 0x20>;
301				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
302				#address-cells = <1>;
303				#size-cells = <0>;
304				status = "disabled";
305			};
306
307			spicc: spi@8d80 {
308				compatible = "amlogic,meson-gx-spicc";
309				reg = <0x0 0x08d80 0x0 0x80>;
310				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
311				#address-cells = <1>;
312				#size-cells = <0>;
313				status = "disabled";
314			};
315
316			spifc: spi@8c80 {
317				compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
318				reg = <0x0 0x08c80 0x0 0x80>;
319				#address-cells = <1>;
320				#size-cells = <0>;
321				status = "disabled";
322			};
323
324			watchdog@98d0 {
325				compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
326				reg = <0x0 0x098d0 0x0 0x10>;
327				clocks = <&xtal>;
328			};
329		};
330
331		gic: interrupt-controller@c4301000 {
332			compatible = "arm,gic-400";
333			reg = <0x0 0xc4301000 0 0x1000>,
334			      <0x0 0xc4302000 0 0x2000>,
335			      <0x0 0xc4304000 0 0x2000>,
336			      <0x0 0xc4306000 0 0x2000>;
337			interrupt-controller;
338			interrupts = <GIC_PPI 9
339				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
340			#interrupt-cells = <3>;
341			#address-cells = <0>;
342		};
343
344		sram: sram@c8000000 {
345			compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
346			reg = <0x0 0xc8000000 0x0 0x14000>;
347
348			#address-cells = <1>;
349			#size-cells = <1>;
350			ranges = <0 0x0 0xc8000000 0x14000>;
351
352			cpu_scp_lpri: scp-shmem@0 {
353				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
354				reg = <0x13000 0x400>;
355			};
356
357			cpu_scp_hpri: scp-shmem@200 {
358				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
359				reg = <0x13400 0x400>;
360			};
361		};
362
363		aobus: aobus@c8100000 {
364			compatible = "simple-bus";
365			reg = <0x0 0xc8100000 0x0 0x100000>;
366			#address-cells = <2>;
367			#size-cells = <2>;
368			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
369
370			sysctrl_AO: sys-ctrl@0 {
371				compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
372				reg =  <0x0 0x0 0x0 0x100>;
373
374				clkc_AO: clock-controller {
375					compatible = "amlogic,meson-gx-aoclkc";
376					#clock-cells = <1>;
377					#reset-cells = <1>;
378				};
379			};
380
381			cec_AO: cec@100 {
382				compatible = "amlogic,meson-gx-ao-cec";
383				reg = <0x0 0x00100 0x0 0x14>;
384				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
385			};
386
387			sec_AO: ao-secure@140 {
388				compatible = "amlogic,meson-gx-ao-secure", "syscon";
389				reg = <0x0 0x140 0x0 0x140>;
390				amlogic,has-chip-id;
391			};
392
393			uart_AO: serial@4c0 {
394				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
395				reg = <0x0 0x004c0 0x0 0x14>;
396				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
397				status = "disabled";
398			};
399
400			uart_AO_B: serial@4e0 {
401				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
402				reg = <0x0 0x004e0 0x0 0x14>;
403				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
404				status = "disabled";
405			};
406
407			i2c_AO: i2c@500 {
408				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
409				reg = <0x0 0x500 0x0 0x20>;
410				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
411				#address-cells = <1>;
412				#size-cells = <0>;
413				status = "disabled";
414			};
415
416			pwm_AO_ab: pwm@550 {
417				compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
418				reg = <0x0 0x00550 0x0 0x10>;
419				#pwm-cells = <3>;
420				status = "disabled";
421			};
422
423			ir: ir@580 {
424				compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
425				reg = <0x0 0x00580 0x0 0x40>;
426				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
427				status = "disabled";
428			};
429		};
430
431		periphs: periphs@c8834000 {
432			compatible = "simple-bus";
433			reg = <0x0 0xc8834000 0x0 0x2000>;
434			#address-cells = <2>;
435			#size-cells = <2>;
436			ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
437
438			hwrng: rng {
439				compatible = "amlogic,meson-rng";
440				reg = <0x0 0x0 0x0 0x4>;
441			};
442		};
443
444		hiubus: hiubus@c883c000 {
445			compatible = "simple-bus";
446			reg = <0x0 0xc883c000 0x0 0x2000>;
447			#address-cells = <2>;
448			#size-cells = <2>;
449			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
450
451			mailbox: mailbox@404 {
452				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
453				reg = <0 0x404 0 0x4c>;
454				interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
455					     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
456					     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
457				#mbox-cells = <1>;
458			};
459		};
460
461		ethmac: ethernet@c9410000 {
462			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
463			reg = <0x0 0xc9410000 0x0 0x10000
464			       0x0 0xc8834540 0x0 0x4>;
465			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
466			interrupt-names = "macirq";
467			status = "disabled";
468		};
469
470		apb: apb@d0000000 {
471			compatible = "simple-bus";
472			reg = <0x0 0xd0000000 0x0 0x200000>;
473			#address-cells = <2>;
474			#size-cells = <2>;
475			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
476
477			sd_emmc_a: mmc@70000 {
478				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
479				reg = <0x0 0x70000 0x0 0x2000>;
480				interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
481				status = "disabled";
482			};
483
484			sd_emmc_b: mmc@72000 {
485				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
486				reg = <0x0 0x72000 0x0 0x2000>;
487				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
488				status = "disabled";
489			};
490
491			sd_emmc_c: mmc@74000 {
492				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
493				reg = <0x0 0x74000 0x0 0x2000>;
494				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
495				status = "disabled";
496			};
497		};
498
499		vpu: vpu@d0100000 {
500			compatible = "amlogic,meson-gx-vpu";
501			reg = <0x0 0xd0100000 0x0 0x100000>,
502			      <0x0 0xc883c000 0x0 0x1000>,
503			      <0x0 0xc8838000 0x0 0x1000>;
504			reg-names = "vpu", "hhi", "dmc";
505			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
506			#address-cells = <1>;
507			#size-cells = <0>;
508
509			/* CVBS VDAC output port */
510			cvbs_vdac_port: port@0 {
511				reg = <0>;
512			};
513
514			/* HDMI-TX output port */
515			hdmi_tx_port: port@1 {
516				reg = <1>;
517
518				hdmi_tx_out: endpoint {
519					remote-endpoint = <&hdmi_tx_in>;
520				};
521			};
522		};
523
524		hdmi_tx: hdmi-tx@c883a000 {
525			compatible = "amlogic,meson-gx-dw-hdmi";
526			reg = <0x0 0xc883a000 0x0 0x1c>;
527			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
528			#address-cells = <1>;
529			#size-cells = <0>;
530			status = "disabled";
531
532			/* VPU VENC Input */
533			hdmi_tx_venc_port: port@0 {
534				reg = <0>;
535
536				hdmi_tx_in: endpoint {
537					remote-endpoint = <&hdmi_tx_out>;
538				};
539			};
540
541			/* TMDS Output */
542			hdmi_tx_tmds_port: port@1 {
543				reg = <1>;
544			};
545		};
546	};
547};
548