1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * Copyright (c) 2016 Endless Computers, Inc. 9 * Author: Carlo Caione <carlo@endlessm.com> 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 /* 16 MiB reserved for Hardware ROM Firmware */ 27 hwrom_reserved: hwrom@0 { 28 reg = <0x0 0x0 0x0 0x1000000>; 29 no-map; 30 }; 31 32 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 33 secmon_reserved: secmon@10000000 { 34 reg = <0x0 0x10000000 0x0 0x200000>; 35 no-map; 36 }; 37 38 linux,cma { 39 compatible = "shared-dma-pool"; 40 reusable; 41 size = <0x0 0xbc00000>; 42 alignment = <0x0 0x400000>; 43 linux,cma-default; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <0x2>; 49 #size-cells = <0x0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&l2>; 57 clocks = <&scpi_dvfs 0>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0x0 0x1>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 clocks = <&scpi_dvfs 0>; 67 }; 68 69 cpu2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0x0 0x2>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 l2: l2-cache0 { 88 compatible = "cache"; 89 }; 90 }; 91 92 arm-pmu { 93 compatible = "arm,cortex-a53-pmu"; 94 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 99 }; 100 101 psci { 102 compatible = "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 116 }; 117 118 xtal: xtal-clk { 119 compatible = "fixed-clock"; 120 clock-frequency = <24000000>; 121 clock-output-names = "xtal"; 122 #clock-cells = <0>; 123 }; 124 125 firmware { 126 sm: secure-monitor { 127 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 128 }; 129 }; 130 131 efuse: efuse { 132 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 136 sn: sn@14 { 137 reg = <0x14 0x10>; 138 }; 139 140 eth_mac: eth_mac@34 { 141 reg = <0x34 0x10>; 142 }; 143 144 bid: bid@46 { 145 reg = <0x46 0x30>; 146 }; 147 }; 148 149 scpi { 150 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 151 mboxes = <&mailbox 1 &mailbox 2>; 152 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 153 154 scpi_clocks: clocks { 155 compatible = "arm,scpi-clocks"; 156 157 scpi_dvfs: scpi_clocks@0 { 158 compatible = "arm,scpi-dvfs-clocks"; 159 #clock-cells = <1>; 160 clock-indices = <0>; 161 clock-output-names = "vcpu"; 162 }; 163 }; 164 165 scpi_sensors: sensors { 166 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 167 #thermal-sensor-cells = <1>; 168 }; 169 }; 170 171 soc { 172 compatible = "simple-bus"; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 177 cbus: bus@c1100000 { 178 compatible = "simple-bus"; 179 reg = <0x0 0xc1100000 0x0 0x100000>; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 183 184 gpio_intc: interrupt-controller@9880 { 185 compatible = "amlogic,meson-gpio-intc"; 186 reg = <0x0 0x9880 0x0 0x10>; 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 190 status = "disabled"; 191 }; 192 193 reset: reset-controller@4404 { 194 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; 195 reg = <0x0 0x04404 0x0 0x9c>; 196 #reset-cells = <1>; 197 }; 198 199 uart_A: serial@84c0 { 200 compatible = "amlogic,meson-gx-uart"; 201 reg = <0x0 0x84c0 0x0 0x18>; 202 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 203 status = "disabled"; 204 }; 205 206 uart_B: serial@84dc { 207 compatible = "amlogic,meson-gx-uart"; 208 reg = <0x0 0x84dc 0x0 0x18>; 209 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 210 status = "disabled"; 211 }; 212 213 i2c_A: i2c@8500 { 214 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 215 reg = <0x0 0x08500 0x0 0x20>; 216 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 status = "disabled"; 220 }; 221 222 pwm_ab: pwm@8550 { 223 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 224 reg = <0x0 0x08550 0x0 0x10>; 225 #pwm-cells = <3>; 226 status = "disabled"; 227 }; 228 229 pwm_cd: pwm@8650 { 230 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 231 reg = <0x0 0x08650 0x0 0x10>; 232 #pwm-cells = <3>; 233 status = "disabled"; 234 }; 235 236 saradc: adc@8680 { 237 compatible = "amlogic,meson-saradc"; 238 reg = <0x0 0x8680 0x0 0x34>; 239 #io-channel-cells = <1>; 240 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 241 status = "disabled"; 242 }; 243 244 pwm_ef: pwm@86c0 { 245 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 246 reg = <0x0 0x086c0 0x0 0x10>; 247 #pwm-cells = <3>; 248 status = "disabled"; 249 }; 250 251 uart_C: serial@8700 { 252 compatible = "amlogic,meson-gx-uart"; 253 reg = <0x0 0x8700 0x0 0x18>; 254 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 255 status = "disabled"; 256 }; 257 258 i2c_B: i2c@87c0 { 259 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 260 reg = <0x0 0x087c0 0x0 0x20>; 261 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 i2c_C: i2c@87e0 { 268 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 269 reg = <0x0 0x087e0 0x0 0x20>; 270 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 status = "disabled"; 274 }; 275 276 spicc: spi@8d80 { 277 compatible = "amlogic,meson-gx-spicc"; 278 reg = <0x0 0x08d80 0x0 0x80>; 279 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 status = "disabled"; 283 }; 284 285 spifc: spi@8c80 { 286 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; 287 reg = <0x0 0x08c80 0x0 0x80>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 watchdog@98d0 { 294 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; 295 reg = <0x0 0x098d0 0x0 0x10>; 296 clocks = <&xtal>; 297 }; 298 }; 299 300 gic: interrupt-controller@c4301000 { 301 compatible = "arm,gic-400"; 302 reg = <0x0 0xc4301000 0 0x1000>, 303 <0x0 0xc4302000 0 0x2000>, 304 <0x0 0xc4304000 0 0x2000>, 305 <0x0 0xc4306000 0 0x2000>; 306 interrupt-controller; 307 interrupts = <GIC_PPI 9 308 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 309 #interrupt-cells = <3>; 310 #address-cells = <0>; 311 }; 312 313 sram: sram@c8000000 { 314 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; 315 reg = <0x0 0xc8000000 0x0 0x14000>; 316 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0 0x0 0xc8000000 0x14000>; 320 321 cpu_scp_lpri: scp-shmem@0 { 322 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 323 reg = <0x13000 0x400>; 324 }; 325 326 cpu_scp_hpri: scp-shmem@200 { 327 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 328 reg = <0x13400 0x400>; 329 }; 330 }; 331 332 aobus: bus@c8100000 { 333 compatible = "simple-bus"; 334 reg = <0x0 0xc8100000 0x0 0x100000>; 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 338 339 sysctrl_AO: sys-ctrl@0 { 340 compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 341 reg = <0x0 0x0 0x0 0x100>; 342 343 pwrc_vpu: power-controller-vpu { 344 compatible = "amlogic,meson-gx-pwrc-vpu"; 345 #power-domain-cells = <0>; 346 amlogic,hhi-sysctrl = <&sysctrl>; 347 }; 348 349 clkc_AO: clock-controller { 350 compatible = "amlogic,meson-gx-aoclkc"; 351 #clock-cells = <1>; 352 #reset-cells = <1>; 353 }; 354 }; 355 356 cec_AO: cec@100 { 357 compatible = "amlogic,meson-gx-ao-cec"; 358 reg = <0x0 0x00100 0x0 0x14>; 359 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 360 }; 361 362 sec_AO: ao-secure@140 { 363 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 364 reg = <0x0 0x140 0x0 0x140>; 365 amlogic,has-chip-id; 366 }; 367 368 uart_AO: serial@4c0 { 369 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 370 reg = <0x0 0x004c0 0x0 0x18>; 371 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 372 status = "disabled"; 373 }; 374 375 uart_AO_B: serial@4e0 { 376 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 377 reg = <0x0 0x004e0 0x0 0x18>; 378 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 379 status = "disabled"; 380 }; 381 382 i2c_AO: i2c@500 { 383 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 384 reg = <0x0 0x500 0x0 0x20>; 385 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 status = "disabled"; 389 }; 390 391 pwm_AO_ab: pwm@550 { 392 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 393 reg = <0x0 0x00550 0x0 0x10>; 394 #pwm-cells = <3>; 395 status = "disabled"; 396 }; 397 398 ir: ir@580 { 399 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 400 reg = <0x0 0x00580 0x0 0x40>; 401 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 402 status = "disabled"; 403 }; 404 }; 405 406 periphs: periphs@c8834000 { 407 compatible = "simple-bus"; 408 reg = <0x0 0xc8834000 0x0 0x2000>; 409 #address-cells = <2>; 410 #size-cells = <2>; 411 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 412 413 hwrng: rng { 414 compatible = "amlogic,meson-rng"; 415 reg = <0x0 0x0 0x0 0x4>; 416 }; 417 }; 418 419 hiubus: bus@c883c000 { 420 compatible = "simple-bus"; 421 reg = <0x0 0xc883c000 0x0 0x2000>; 422 #address-cells = <2>; 423 #size-cells = <2>; 424 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 425 426 sysctrl: system-controller@0 { 427 compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; 428 reg = <0 0 0 0x400>; 429 }; 430 431 mailbox: mailbox@404 { 432 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 433 reg = <0 0x404 0 0x4c>; 434 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 435 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 436 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 437 #mbox-cells = <1>; 438 }; 439 }; 440 441 ethmac: ethernet@c9410000 { 442 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 443 reg = <0x0 0xc9410000 0x0 0x10000 444 0x0 0xc8834540 0x0 0x4>; 445 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 446 interrupt-names = "macirq"; 447 status = "disabled"; 448 }; 449 450 apb: apb@d0000000 { 451 compatible = "simple-bus"; 452 reg = <0x0 0xd0000000 0x0 0x200000>; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 456 457 sd_emmc_a: mmc@70000 { 458 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 459 reg = <0x0 0x70000 0x0 0x2000>; 460 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 461 status = "disabled"; 462 }; 463 464 sd_emmc_b: mmc@72000 { 465 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 466 reg = <0x0 0x72000 0x0 0x2000>; 467 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 468 status = "disabled"; 469 }; 470 471 sd_emmc_c: mmc@74000 { 472 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 473 reg = <0x0 0x74000 0x0 0x2000>; 474 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 475 status = "disabled"; 476 }; 477 }; 478 479 vpu: vpu@d0100000 { 480 compatible = "amlogic,meson-gx-vpu"; 481 reg = <0x0 0xd0100000 0x0 0x100000>, 482 <0x0 0xc883c000 0x0 0x1000>, 483 <0x0 0xc8838000 0x0 0x1000>; 484 reg-names = "vpu", "hhi", "dmc"; 485 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 489 /* CVBS VDAC output port */ 490 cvbs_vdac_port: port@0 { 491 reg = <0>; 492 }; 493 494 /* HDMI-TX output port */ 495 hdmi_tx_port: port@1 { 496 reg = <1>; 497 498 hdmi_tx_out: endpoint { 499 remote-endpoint = <&hdmi_tx_in>; 500 }; 501 }; 502 }; 503 504 hdmi_tx: hdmi-tx@c883a000 { 505 compatible = "amlogic,meson-gx-dw-hdmi"; 506 reg = <0x0 0xc883a000 0x0 0x1c>; 507 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 512 /* VPU VENC Input */ 513 hdmi_tx_venc_port: port@0 { 514 reg = <0>; 515 516 hdmi_tx_in: endpoint { 517 remote-endpoint = <&hdmi_tx_out>; 518 }; 519 }; 520 521 /* TMDS Output */ 522 hdmi_tx_tmds_port: port@1 { 523 reg = <1>; 524 }; 525 }; 526 }; 527}; 528