1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/clock/g12a-clkc.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "amlogic,g12a";
13
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <0x2>;
20		#size-cells = <0x0>;
21
22		cpu0: cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a53";
25			reg = <0x0 0x0>;
26			enable-method = "psci";
27			next-level-cache = <&l2>;
28		};
29
30		cpu1: cpu@1 {
31			device_type = "cpu";
32			compatible = "arm,cortex-a53";
33			reg = <0x0 0x1>;
34			enable-method = "psci";
35			next-level-cache = <&l2>;
36		};
37
38		cpu2: cpu@2 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a53";
41			reg = <0x0 0x2>;
42			enable-method = "psci";
43			next-level-cache = <&l2>;
44		};
45
46		cpu3: cpu@3 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			reg = <0x0 0x3>;
50			enable-method = "psci";
51			next-level-cache = <&l2>;
52		};
53
54		l2: l2-cache0 {
55			compatible = "cache";
56		};
57	};
58
59	efuse: efuse {
60		compatible = "amlogic,meson-gxbb-efuse";
61		clocks = <&clkc CLKID_EFUSE>;
62		#address-cells = <1>;
63		#size-cells = <1>;
64		read-only;
65	};
66
67	psci {
68		compatible = "arm,psci-1.0";
69		method = "smc";
70	};
71
72	reserved-memory {
73		#address-cells = <2>;
74		#size-cells = <2>;
75		ranges;
76
77		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
78		secmon_reserved: secmon@5000000 {
79			reg = <0x0 0x05000000 0x0 0x300000>;
80			no-map;
81		};
82	};
83
84	sm: secure-monitor {
85		compatible = "amlogic,meson-gxbb-sm";
86	};
87
88	soc {
89		compatible = "simple-bus";
90		#address-cells = <2>;
91		#size-cells = <2>;
92		ranges;
93
94		apb: bus@ff600000 {
95			compatible = "simple-bus";
96			reg = <0x0 0xff600000 0x0 0x200000>;
97			#address-cells = <2>;
98			#size-cells = <2>;
99			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
100
101			periphs: bus@34400 {
102				compatible = "simple-bus";
103				reg = <0x0 0x34400 0x0 0x400>;
104				#address-cells = <2>;
105				#size-cells = <2>;
106				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
107
108				periphs_pinctrl: pinctrl@40 {
109					compatible = "amlogic,meson-g12a-periphs-pinctrl";
110					#address-cells = <2>;
111					#size-cells = <2>;
112					ranges;
113
114					gpio: bank@40 {
115						reg = <0x0 0x40  0x0 0x4c>,
116						      <0x0 0xe8  0x0 0x18>,
117						      <0x0 0x120 0x0 0x18>,
118						      <0x0 0x2c0 0x0 0x40>,
119						      <0x0 0x340 0x0 0x1c>;
120						reg-names = "gpio",
121							    "pull",
122							    "pull-enable",
123							    "mux",
124							    "ds";
125						gpio-controller;
126						#gpio-cells = <2>;
127						gpio-ranges = <&periphs_pinctrl 0 0 86>;
128					};
129
130					uart_a_pins: uart-a {
131						mux {
132							groups = "uart_a_tx",
133								 "uart_a_rx";
134							function = "uart_a";
135							bias-disable;
136						};
137					};
138
139					uart_a_cts_rts_pins: uart-a-cts-rts {
140						mux {
141							groups = "uart_a_cts",
142								 "uart_a_rts";
143							function = "uart_a";
144							bias-disable;
145						};
146					};
147
148					uart_b_pins: uart-b {
149						mux {
150							groups = "uart_b_tx",
151								 "uart_b_rx";
152							function = "uart_b";
153							bias-disable;
154						};
155					};
156
157					uart_c_pins: uart-c {
158						mux {
159							groups = "uart_c_tx",
160								 "uart_c_rx";
161							function = "uart_c";
162							bias-disable;
163						};
164					};
165
166					uart_c_cts_rts_pins: uart-c-cts-rts {
167						mux {
168							groups = "uart_c_cts",
169								 "uart_c_rts";
170							function = "uart_c";
171							bias-disable;
172						};
173					};
174				};
175			};
176
177			hiu: bus@3c000 {
178				compatible = "simple-bus";
179				reg = <0x0 0x3c000 0x0 0x1400>;
180				#address-cells = <2>;
181				#size-cells = <2>;
182				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
183
184				hhi: system-controller@0 {
185					compatible = "amlogic,meson-gx-hhi-sysctrl",
186						     "simple-mfd", "syscon";
187					reg = <0 0 0 0x400>;
188
189					clkc: clock-controller {
190						compatible = "amlogic,g12a-clkc";
191						#clock-cells = <1>;
192						clocks = <&xtal>;
193						clock-names = "xtal";
194					};
195				};
196			};
197		};
198
199		aobus: bus@ff800000 {
200			compatible = "simple-bus";
201			reg = <0x0 0xff800000 0x0 0x100000>;
202			#address-cells = <2>;
203			#size-cells = <2>;
204			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
205
206			rti: sys-ctrl@0 {
207				compatible = "amlogic,meson-gx-ao-sysctrl",
208					     "simple-mfd", "syscon";
209				reg = <0x0 0x0 0x0 0x100>;
210				#address-cells = <2>;
211				#size-cells = <2>;
212				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
213
214				clkc_AO: clock-controller {
215					compatible = "amlogic,meson-g12a-aoclkc";
216					#clock-cells = <1>;
217					#reset-cells = <1>;
218					clocks = <&xtal>, <&clkc CLKID_CLK81>;
219					clock-names = "xtal", "mpeg-clk";
220				};
221
222				ao_pinctrl: pinctrl@14 {
223					compatible = "amlogic,meson-g12a-aobus-pinctrl";
224					#address-cells = <2>;
225					#size-cells = <2>;
226					ranges;
227
228					gpio_ao: bank@14 {
229						reg = <0x0 0x14 0x0 0x8>,
230						      <0x0 0x1c 0x0 0x8>,
231						      <0x0 0x24 0x0 0x14>;
232						reg-names = "mux",
233							    "ds",
234							    "gpio";
235						gpio-controller;
236						#gpio-cells = <2>;
237						gpio-ranges = <&ao_pinctrl 0 0 15>;
238					};
239
240					uart_ao_a_pins: uart-a-ao {
241						mux {
242							groups = "uart_ao_a_tx",
243								 "uart_ao_a_rx";
244							function = "uart_ao_a";
245							bias-disable;
246						};
247					};
248
249					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
250						mux {
251							groups = "uart_ao_a_cts",
252								 "uart_ao_a_rts";
253							function = "uart_ao_a";
254							bias-disable;
255						};
256					};
257				};
258			};
259
260			sec_AO: ao-secure@140 {
261				compatible = "amlogic,meson-gx-ao-secure", "syscon";
262				reg = <0x0 0x140 0x0 0x140>;
263				amlogic,has-chip-id;
264			};
265
266			uart_AO: serial@3000 {
267				compatible = "amlogic,meson-gx-uart",
268					     "amlogic,meson-ao-uart";
269				reg = <0x0 0x3000 0x0 0x18>;
270				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
271				clocks = <&xtal>, <&xtal>, <&xtal>;
272				clock-names = "xtal", "pclk", "baud";
273				status = "disabled";
274			};
275
276			uart_AO_B: serial@4000 {
277				compatible = "amlogic,meson-gx-uart",
278					     "amlogic,meson-ao-uart";
279				reg = <0x0 0x4000 0x0 0x18>;
280				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
281				clocks = <&xtal>, <&xtal>, <&xtal>;
282				clock-names = "xtal", "pclk", "baud";
283				status = "disabled";
284			};
285		};
286
287		gic: interrupt-controller@ffc01000 {
288			compatible = "arm,gic-400";
289			reg = <0x0 0xffc01000 0 0x1000>,
290			      <0x0 0xffc02000 0 0x2000>,
291			      <0x0 0xffc04000 0 0x2000>,
292			      <0x0 0xffc06000 0 0x2000>;
293			interrupt-controller;
294			interrupts = <GIC_PPI 9
295				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
296			#interrupt-cells = <3>;
297			#address-cells = <0>;
298		};
299
300		cbus: bus@ffd00000 {
301			compatible = "simple-bus";
302			reg = <0x0 0xffd00000 0x0 0x100000>;
303			#address-cells = <2>;
304			#size-cells = <2>;
305			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
306
307			reset: reset-controller@1004 {
308				compatible = "amlogic,meson-g12a-reset",
309					     "amlogic,meson-axg-reset";
310				reg = <0x0 0x1004 0x0 0x9c>;
311				#reset-cells = <1>;
312			};
313
314			clk_msr: clock-measure@18000 {
315				compatible = "amlogic,meson-g12a-clk-measure";
316				reg = <0x0 0x18000 0x0 0x10>;
317			};
318
319			uart_C: serial@22000 {
320				compatible = "amlogic,meson-gx-uart";
321				reg = <0x0 0x22000 0x0 0x18>;
322				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
323				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
324				clock-names = "xtal", "pclk", "baud";
325				status = "disabled";
326			};
327
328			uart_B: serial@23000 {
329				compatible = "amlogic,meson-gx-uart";
330				reg = <0x0 0x23000 0x0 0x18>;
331				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
332				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
333				clock-names = "xtal", "pclk", "baud";
334				status = "disabled";
335			};
336
337			uart_A: serial@24000 {
338				compatible = "amlogic,meson-gx-uart";
339				reg = <0x0 0x24000 0x0 0x18>;
340				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
341				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
342				clock-names = "xtal", "pclk", "baud";
343				status = "disabled";
344			};
345		};
346	};
347
348	timer {
349		compatible = "arm,armv8-timer";
350		interrupts = <GIC_PPI 13
351			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
352			     <GIC_PPI 14
353			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
354			     <GIC_PPI 11
355			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
356			     <GIC_PPI 10
357			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
358	};
359
360	xtal: xtal-clk {
361		compatible = "fixed-clock";
362		clock-frequency = <24000000>;
363		clock-output-names = "xtal";
364		#clock-cells = <0>;
365	};
366
367};
368