1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/clock/g12a-clkc.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "amlogic,g12a"; 13 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <0x2>; 20 #size-cells = <0x0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53"; 25 reg = <0x0 0x0>; 26 enable-method = "psci"; 27 next-level-cache = <&l2>; 28 }; 29 30 cpu1: cpu@1 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53"; 33 reg = <0x0 0x1>; 34 enable-method = "psci"; 35 next-level-cache = <&l2>; 36 }; 37 38 cpu2: cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x2>; 42 enable-method = "psci"; 43 next-level-cache = <&l2>; 44 }; 45 46 cpu3: cpu@3 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x3>; 50 enable-method = "psci"; 51 next-level-cache = <&l2>; 52 }; 53 54 l2: l2-cache0 { 55 compatible = "cache"; 56 }; 57 }; 58 59 efuse: efuse { 60 compatible = "amlogic,meson-gxbb-efuse"; 61 clocks = <&clkc CLKID_EFUSE>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 read-only; 65 }; 66 67 psci { 68 compatible = "arm,psci-1.0"; 69 method = "smc"; 70 }; 71 72 reserved-memory { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 78 secmon_reserved: secmon@5000000 { 79 reg = <0x0 0x05000000 0x0 0x300000>; 80 no-map; 81 }; 82 83 linux,cma { 84 compatible = "shared-dma-pool"; 85 reusable; 86 size = <0x0 0x10000000>; 87 alignment = <0x0 0x400000>; 88 linux,cma-default; 89 }; 90 }; 91 92 sm: secure-monitor { 93 compatible = "amlogic,meson-gxbb-sm"; 94 }; 95 96 soc { 97 compatible = "simple-bus"; 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 102 apb: bus@ff600000 { 103 compatible = "simple-bus"; 104 reg = <0x0 0xff600000 0x0 0x200000>; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 108 109 periphs: bus@34400 { 110 compatible = "simple-bus"; 111 reg = <0x0 0x34400 0x0 0x400>; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 115 116 periphs_pinctrl: pinctrl@40 { 117 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 118 #address-cells = <2>; 119 #size-cells = <2>; 120 ranges; 121 122 gpio: bank@40 { 123 reg = <0x0 0x40 0x0 0x4c>, 124 <0x0 0xe8 0x0 0x18>, 125 <0x0 0x120 0x0 0x18>, 126 <0x0 0x2c0 0x0 0x40>, 127 <0x0 0x340 0x0 0x1c>; 128 reg-names = "gpio", 129 "pull", 130 "pull-enable", 131 "mux", 132 "ds"; 133 gpio-controller; 134 #gpio-cells = <2>; 135 gpio-ranges = <&periphs_pinctrl 0 0 86>; 136 }; 137 138 uart_a_pins: uart-a { 139 mux { 140 groups = "uart_a_tx", 141 "uart_a_rx"; 142 function = "uart_a"; 143 bias-disable; 144 }; 145 }; 146 147 uart_a_cts_rts_pins: uart-a-cts-rts { 148 mux { 149 groups = "uart_a_cts", 150 "uart_a_rts"; 151 function = "uart_a"; 152 bias-disable; 153 }; 154 }; 155 156 uart_b_pins: uart-b { 157 mux { 158 groups = "uart_b_tx", 159 "uart_b_rx"; 160 function = "uart_b"; 161 bias-disable; 162 }; 163 }; 164 165 uart_c_pins: uart-c { 166 mux { 167 groups = "uart_c_tx", 168 "uart_c_rx"; 169 function = "uart_c"; 170 bias-disable; 171 }; 172 }; 173 174 uart_c_cts_rts_pins: uart-c-cts-rts { 175 mux { 176 groups = "uart_c_cts", 177 "uart_c_rts"; 178 function = "uart_c"; 179 bias-disable; 180 }; 181 }; 182 }; 183 }; 184 185 hiu: bus@3c000 { 186 compatible = "simple-bus"; 187 reg = <0x0 0x3c000 0x0 0x1400>; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 191 192 hhi: system-controller@0 { 193 compatible = "amlogic,meson-gx-hhi-sysctrl", 194 "simple-mfd", "syscon"; 195 reg = <0 0 0 0x400>; 196 197 clkc: clock-controller { 198 compatible = "amlogic,g12a-clkc"; 199 #clock-cells = <1>; 200 clocks = <&xtal>; 201 clock-names = "xtal"; 202 }; 203 }; 204 }; 205 }; 206 207 aobus: bus@ff800000 { 208 compatible = "simple-bus"; 209 reg = <0x0 0xff800000 0x0 0x100000>; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 213 214 rti: sys-ctrl@0 { 215 compatible = "amlogic,meson-gx-ao-sysctrl", 216 "simple-mfd", "syscon"; 217 reg = <0x0 0x0 0x0 0x100>; 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 221 222 clkc_AO: clock-controller { 223 compatible = "amlogic,meson-g12a-aoclkc"; 224 #clock-cells = <1>; 225 #reset-cells = <1>; 226 clocks = <&xtal>, <&clkc CLKID_CLK81>; 227 clock-names = "xtal", "mpeg-clk"; 228 }; 229 230 ao_pinctrl: pinctrl@14 { 231 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 232 #address-cells = <2>; 233 #size-cells = <2>; 234 ranges; 235 236 gpio_ao: bank@14 { 237 reg = <0x0 0x14 0x0 0x8>, 238 <0x0 0x1c 0x0 0x8>, 239 <0x0 0x24 0x0 0x14>; 240 reg-names = "mux", 241 "ds", 242 "gpio"; 243 gpio-controller; 244 #gpio-cells = <2>; 245 gpio-ranges = <&ao_pinctrl 0 0 15>; 246 }; 247 248 uart_ao_a_pins: uart-a-ao { 249 mux { 250 groups = "uart_ao_a_tx", 251 "uart_ao_a_rx"; 252 function = "uart_ao_a"; 253 bias-disable; 254 }; 255 }; 256 257 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 258 mux { 259 groups = "uart_ao_a_cts", 260 "uart_ao_a_rts"; 261 function = "uart_ao_a"; 262 bias-disable; 263 }; 264 }; 265 }; 266 }; 267 268 sec_AO: ao-secure@140 { 269 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 270 reg = <0x0 0x140 0x0 0x140>; 271 amlogic,has-chip-id; 272 }; 273 274 uart_AO: serial@3000 { 275 compatible = "amlogic,meson-gx-uart", 276 "amlogic,meson-ao-uart"; 277 reg = <0x0 0x3000 0x0 0x18>; 278 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 279 clocks = <&xtal>, <&xtal>, <&xtal>; 280 clock-names = "xtal", "pclk", "baud"; 281 status = "disabled"; 282 }; 283 284 uart_AO_B: serial@4000 { 285 compatible = "amlogic,meson-gx-uart", 286 "amlogic,meson-ao-uart"; 287 reg = <0x0 0x4000 0x0 0x18>; 288 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 289 clocks = <&xtal>, <&xtal>, <&xtal>; 290 clock-names = "xtal", "pclk", "baud"; 291 status = "disabled"; 292 }; 293 }; 294 295 gic: interrupt-controller@ffc01000 { 296 compatible = "arm,gic-400"; 297 reg = <0x0 0xffc01000 0 0x1000>, 298 <0x0 0xffc02000 0 0x2000>, 299 <0x0 0xffc04000 0 0x2000>, 300 <0x0 0xffc06000 0 0x2000>; 301 interrupt-controller; 302 interrupts = <GIC_PPI 9 303 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 304 #interrupt-cells = <3>; 305 #address-cells = <0>; 306 }; 307 308 cbus: bus@ffd00000 { 309 compatible = "simple-bus"; 310 reg = <0x0 0xffd00000 0x0 0x100000>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 314 315 reset: reset-controller@1004 { 316 compatible = "amlogic,meson-g12a-reset", 317 "amlogic,meson-axg-reset"; 318 reg = <0x0 0x1004 0x0 0x9c>; 319 #reset-cells = <1>; 320 }; 321 322 clk_msr: clock-measure@18000 { 323 compatible = "amlogic,meson-g12a-clk-measure"; 324 reg = <0x0 0x18000 0x0 0x10>; 325 }; 326 327 uart_C: serial@22000 { 328 compatible = "amlogic,meson-gx-uart"; 329 reg = <0x0 0x22000 0x0 0x18>; 330 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 331 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 332 clock-names = "xtal", "pclk", "baud"; 333 status = "disabled"; 334 }; 335 336 uart_B: serial@23000 { 337 compatible = "amlogic,meson-gx-uart"; 338 reg = <0x0 0x23000 0x0 0x18>; 339 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 340 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 341 clock-names = "xtal", "pclk", "baud"; 342 status = "disabled"; 343 }; 344 345 uart_A: serial@24000 { 346 compatible = "amlogic,meson-gx-uart"; 347 reg = <0x0 0x24000 0x0 0x18>; 348 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 349 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 350 clock-names = "xtal", "pclk", "baud"; 351 status = "disabled"; 352 }; 353 }; 354 }; 355 356 timer { 357 compatible = "arm,armv8-timer"; 358 interrupts = <GIC_PPI 13 359 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 360 <GIC_PPI 14 361 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 362 <GIC_PPI 11 363 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 364 <GIC_PPI 10 365 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 366 }; 367 368 xtal: xtal-clk { 369 compatible = "fixed-clock"; 370 clock-frequency = <24000000>; 371 clock-output-names = "xtal"; 372 #clock-cells = <0>; 373 }; 374 375}; 376