1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "amlogic,g12a"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <0x2>; 19 #size-cells = <0x0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a53"; 24 reg = <0x0 0x0>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0 0x1>; 33 enable-method = "psci"; 34 next-level-cache = <&l2>; 35 }; 36 37 cpu2: cpu@2 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0 0x2>; 41 enable-method = "psci"; 42 next-level-cache = <&l2>; 43 }; 44 45 cpu3: cpu@3 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0 0x3>; 49 enable-method = "psci"; 50 next-level-cache = <&l2>; 51 }; 52 53 l2: l2-cache0 { 54 compatible = "cache"; 55 }; 56 }; 57 58 psci { 59 compatible = "arm,psci-1.0"; 60 method = "smc"; 61 }; 62 63 reserved-memory { 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges; 67 68 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 69 secmon_reserved: secmon@5000000 { 70 reg = <0x0 0x05000000 0x0 0x300000>; 71 no-map; 72 }; 73 }; 74 75 sm: secure-monitor { 76 compatible = "amlogic,meson-gxbb-sm"; 77 }; 78 79 soc { 80 compatible = "simple-bus"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 apb: bus@ff600000 { 86 compatible = "simple-bus"; 87 reg = <0x0 0xff600000 0x0 0x200000>; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 91 92 periphs: bus@34400 { 93 compatible = "simple-bus"; 94 reg = <0x0 0x34400 0x0 0x400>; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 98 }; 99 100 hiu: bus@3c000 { 101 compatible = "simple-bus"; 102 reg = <0x0 0x3c000 0x0 0x1400>; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 106 107 hhi: system-controller@0 { 108 compatible = "amlogic,meson-gx-hhi-sysctrl", 109 "simple-mfd", "syscon"; 110 reg = <0 0 0 0x400>; 111 112 clkc: clock-controller { 113 compatible = "amlogic,g12a-clkc"; 114 #clock-cells = <1>; 115 clocks = <&xtal>; 116 clock-names = "xtal"; 117 }; 118 }; 119 }; 120 }; 121 122 aobus: bus@ff800000 { 123 compatible = "simple-bus"; 124 reg = <0x0 0xff800000 0x0 0x100000>; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 128 129 sec_AO: ao-secure@140 { 130 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 131 reg = <0x0 0x140 0x0 0x140>; 132 amlogic,has-chip-id; 133 }; 134 135 uart_AO: serial@3000 { 136 compatible = "amlogic,meson-gx-uart", 137 "amlogic,meson-ao-uart"; 138 reg = <0x0 0x3000 0x0 0x18>; 139 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 140 clocks = <&xtal>, <&xtal>, <&xtal>; 141 clock-names = "xtal", "pclk", "baud"; 142 status = "disabled"; 143 }; 144 145 uart_AO_B: serial@4000 { 146 compatible = "amlogic,meson-gx-uart", 147 "amlogic,meson-ao-uart"; 148 reg = <0x0 0x4000 0x0 0x18>; 149 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 150 clocks = <&xtal>, <&xtal>, <&xtal>; 151 clock-names = "xtal", "pclk", "baud"; 152 status = "disabled"; 153 }; 154 }; 155 156 gic: interrupt-controller@ffc01000 { 157 compatible = "arm,gic-400"; 158 reg = <0x0 0xffc01000 0 0x1000>, 159 <0x0 0xffc02000 0 0x2000>, 160 <0x0 0xffc04000 0 0x2000>, 161 <0x0 0xffc06000 0 0x2000>; 162 interrupt-controller; 163 interrupts = <GIC_PPI 9 164 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 165 #interrupt-cells = <3>; 166 #address-cells = <0>; 167 }; 168 169 cbus: bus@ffd00000 { 170 compatible = "simple-bus"; 171 reg = <0x0 0xffd00000 0x0 0x100000>; 172 #address-cells = <2>; 173 #size-cells = <2>; 174 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 175 176 clk_msr: clock-measure@18000 { 177 compatible = "amlogic,meson-g12a-clk-measure"; 178 reg = <0x0 0x18000 0x0 0x10>; 179 }; 180 }; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 186 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 187 <GIC_PPI 14 188 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 189 <GIC_PPI 11 190 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 191 <GIC_PPI 10 192 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 193 }; 194 195 xtal: xtal-clk { 196 compatible = "fixed-clock"; 197 clock-frequency = <24000000>; 198 clock-output-names = "xtal"; 199 #clock-cells = <0>; 200 }; 201 202}; 203