1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 14/ { 15 compatible = "amlogic,g12a"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <0x2>; 23 #size-cells = <0x0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0 0x1>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x2>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x3>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 l2: l2-cache0 { 58 compatible = "cache"; 59 }; 60 }; 61 62 efuse: efuse { 63 compatible = "amlogic,meson-gxbb-efuse"; 64 clocks = <&clkc CLKID_EFUSE>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 read-only; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 81 secmon_reserved: secmon@5000000 { 82 reg = <0x0 0x05000000 0x0 0x300000>; 83 no-map; 84 }; 85 86 linux,cma { 87 compatible = "shared-dma-pool"; 88 reusable; 89 size = <0x0 0x10000000>; 90 alignment = <0x0 0x400000>; 91 linux,cma-default; 92 }; 93 }; 94 95 sm: secure-monitor { 96 compatible = "amlogic,meson-gxbb-sm"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 apb: bus@ff600000 { 106 compatible = "simple-bus"; 107 reg = <0x0 0xff600000 0x0 0x200000>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111 112 hdmi_tx: hdmi-tx@0 { 113 compatible = "amlogic,meson-g12a-dw-hdmi"; 114 reg = <0x0 0x0 0x0 0x10000>; 115 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 116 resets = <&reset RESET_HDMITX_CAPB3>, 117 <&reset RESET_HDMITX_PHY>, 118 <&reset RESET_HDMITX>; 119 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 120 clocks = <&clkc CLKID_HDMI>, 121 <&clkc CLKID_HTX_PCLK>, 122 <&clkc CLKID_VPU_INTR>; 123 clock-names = "isfr", "iahb", "venci"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* VPU VENC Input */ 129 hdmi_tx_venc_port: port@0 { 130 reg = <0>; 131 132 hdmi_tx_in: endpoint { 133 remote-endpoint = <&hdmi_tx_out>; 134 }; 135 }; 136 137 /* TMDS Output */ 138 hdmi_tx_tmds_port: port@1 { 139 reg = <1>; 140 }; 141 }; 142 143 periphs: bus@34400 { 144 compatible = "simple-bus"; 145 reg = <0x0 0x34400 0x0 0x400>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 149 150 periphs_pinctrl: pinctrl@40 { 151 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 gpio: bank@40 { 157 reg = <0x0 0x40 0x0 0x4c>, 158 <0x0 0xe8 0x0 0x18>, 159 <0x0 0x120 0x0 0x18>, 160 <0x0 0x2c0 0x0 0x40>, 161 <0x0 0x340 0x0 0x1c>; 162 reg-names = "gpio", 163 "pull", 164 "pull-enable", 165 "mux", 166 "ds"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 0 86>; 170 }; 171 172 cec_ao_a_h_pins: cec_ao_a_h { 173 mux { 174 groups = "cec_ao_a_h"; 175 function = "cec_ao_a_h"; 176 bias-disable; 177 }; 178 }; 179 180 cec_ao_b_h_pins: cec_ao_b_h { 181 mux { 182 groups = "cec_ao_b_h"; 183 function = "cec_ao_b_h"; 184 bias-disable; 185 }; 186 }; 187 188 hdmitx_ddc_pins: hdmitx_ddc { 189 mux { 190 groups = "hdmitx_sda", 191 "hdmitx_sck"; 192 function = "hdmitx"; 193 bias-disable; 194 }; 195 }; 196 197 hdmitx_hpd_pins: hdmitx_hpd { 198 mux { 199 groups = "hdmitx_hpd_in"; 200 function = "hdmitx"; 201 bias-disable; 202 }; 203 }; 204 205 pwm_a_pins: pwm-a { 206 mux { 207 groups = "pwm_a"; 208 function = "pwm_a"; 209 bias-disable; 210 }; 211 }; 212 213 pwm_b_x7_pins: pwm-b-x7 { 214 mux { 215 groups = "pwm_b_x7"; 216 function = "pwm_b"; 217 bias-disable; 218 }; 219 }; 220 221 pwm_b_x19_pins: pwm-b-x19 { 222 mux { 223 groups = "pwm_b_x19"; 224 function = "pwm_b"; 225 bias-disable; 226 }; 227 }; 228 229 pwm_c_c_pins: pwm-c-c { 230 mux { 231 groups = "pwm_c_c"; 232 function = "pwm_c"; 233 bias-disable; 234 }; 235 }; 236 237 pwm_c_x5_pins: pwm-c-x5 { 238 mux { 239 groups = "pwm_c_x5"; 240 function = "pwm_c"; 241 bias-disable; 242 }; 243 }; 244 245 pwm_c_x8_pins: pwm-c-x8 { 246 mux { 247 groups = "pwm_c_x8"; 248 function = "pwm_c"; 249 bias-disable; 250 }; 251 }; 252 253 pwm_d_x3_pins: pwm-d-x3 { 254 mux { 255 groups = "pwm_d_x3"; 256 function = "pwm_d"; 257 bias-disable; 258 }; 259 }; 260 261 pwm_d_x6_pins: pwm-d-x6 { 262 mux { 263 groups = "pwm_d_x6"; 264 function = "pwm_d"; 265 bias-disable; 266 }; 267 }; 268 269 pwm_e_pins: pwm-e { 270 mux { 271 groups = "pwm_e"; 272 function = "pwm_e"; 273 bias-disable; 274 }; 275 }; 276 277 pwm_f_x_pins: pwm-f-x { 278 mux { 279 groups = "pwm_f_x"; 280 function = "pwm_f"; 281 bias-disable; 282 }; 283 }; 284 285 pwm_f_h_pins: pwm-f-h { 286 mux { 287 groups = "pwm_f_h"; 288 function = "pwm_f"; 289 bias-disable; 290 }; 291 }; 292 293 uart_a_pins: uart-a { 294 mux { 295 groups = "uart_a_tx", 296 "uart_a_rx"; 297 function = "uart_a"; 298 bias-disable; 299 }; 300 }; 301 302 uart_a_cts_rts_pins: uart-a-cts-rts { 303 mux { 304 groups = "uart_a_cts", 305 "uart_a_rts"; 306 function = "uart_a"; 307 bias-disable; 308 }; 309 }; 310 311 uart_b_pins: uart-b { 312 mux { 313 groups = "uart_b_tx", 314 "uart_b_rx"; 315 function = "uart_b"; 316 bias-disable; 317 }; 318 }; 319 320 uart_c_pins: uart-c { 321 mux { 322 groups = "uart_c_tx", 323 "uart_c_rx"; 324 function = "uart_c"; 325 bias-disable; 326 }; 327 }; 328 329 uart_c_cts_rts_pins: uart-c-cts-rts { 330 mux { 331 groups = "uart_c_cts", 332 "uart_c_rts"; 333 function = "uart_c"; 334 bias-disable; 335 }; 336 }; 337 }; 338 }; 339 340 usb2_phy0: phy@36000 { 341 compatible = "amlogic,g12a-usb2-phy"; 342 reg = <0x0 0x36000 0x0 0x2000>; 343 clocks = <&xtal>; 344 clock-names = "xtal"; 345 resets = <&reset RESET_USB_PHY20>; 346 reset-names = "phy"; 347 #phy-cells = <0>; 348 }; 349 350 dmc: bus@38000 { 351 compatible = "simple-bus"; 352 reg = <0x0 0x38000 0x0 0x400>; 353 #address-cells = <2>; 354 #size-cells = <2>; 355 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 356 357 canvas: video-lut@48 { 358 compatible = "amlogic,canvas"; 359 reg = <0x0 0x48 0x0 0x14>; 360 }; 361 }; 362 363 usb2_phy1: phy@3a000 { 364 compatible = "amlogic,g12a-usb2-phy"; 365 reg = <0x0 0x3a000 0x0 0x2000>; 366 clocks = <&xtal>; 367 clock-names = "xtal"; 368 resets = <&reset RESET_USB_PHY21>; 369 reset-names = "phy"; 370 #phy-cells = <0>; 371 }; 372 373 hiu: bus@3c000 { 374 compatible = "simple-bus"; 375 reg = <0x0 0x3c000 0x0 0x1400>; 376 #address-cells = <2>; 377 #size-cells = <2>; 378 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 379 380 hhi: system-controller@0 { 381 compatible = "amlogic,meson-gx-hhi-sysctrl", 382 "simple-mfd", "syscon"; 383 reg = <0 0 0 0x400>; 384 385 clkc: clock-controller { 386 compatible = "amlogic,g12a-clkc"; 387 #clock-cells = <1>; 388 clocks = <&xtal>; 389 clock-names = "xtal"; 390 }; 391 }; 392 }; 393 394 usb3_pcie_phy: phy@46000 { 395 compatible = "amlogic,g12a-usb3-pcie-phy"; 396 reg = <0x0 0x46000 0x0 0x2000>; 397 clocks = <&clkc CLKID_PCIE_PLL>; 398 clock-names = "ref_clk"; 399 resets = <&reset RESET_PCIE_PHY>; 400 reset-names = "phy"; 401 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 402 assigned-clock-rates = <100000000>; 403 #phy-cells = <1>; 404 }; 405 }; 406 407 aobus: bus@ff800000 { 408 compatible = "simple-bus"; 409 reg = <0x0 0xff800000 0x0 0x100000>; 410 #address-cells = <2>; 411 #size-cells = <2>; 412 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 413 414 rti: sys-ctrl@0 { 415 compatible = "amlogic,meson-gx-ao-sysctrl", 416 "simple-mfd", "syscon"; 417 reg = <0x0 0x0 0x0 0x100>; 418 #address-cells = <2>; 419 #size-cells = <2>; 420 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 421 422 clkc_AO: clock-controller { 423 compatible = "amlogic,meson-g12a-aoclkc"; 424 #clock-cells = <1>; 425 #reset-cells = <1>; 426 clocks = <&xtal>, <&clkc CLKID_CLK81>; 427 clock-names = "xtal", "mpeg-clk"; 428 }; 429 430 pwrc_vpu: power-controller-vpu { 431 compatible = "amlogic,meson-g12a-pwrc-vpu"; 432 #power-domain-cells = <0>; 433 amlogic,hhi-sysctrl = <&hhi>; 434 resets = <&reset RESET_VIU>, 435 <&reset RESET_VENC>, 436 <&reset RESET_VCBUS>, 437 <&reset RESET_BT656>, 438 <&reset RESET_RDMA>, 439 <&reset RESET_VENCI>, 440 <&reset RESET_VENCP>, 441 <&reset RESET_VDAC>, 442 <&reset RESET_VDI6>, 443 <&reset RESET_VENCL>, 444 <&reset RESET_VID_LOCK>; 445 clocks = <&clkc CLKID_VPU>, 446 <&clkc CLKID_VAPB>; 447 clock-names = "vpu", "vapb"; 448 /* 449 * VPU clocking is provided by two identical clock paths 450 * VPU_0 and VPU_1 muxed to a single clock by a glitch 451 * free mux to safely change frequency while running. 452 * Same for VAPB but with a final gate after the glitch free mux. 453 */ 454 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 455 <&clkc CLKID_VPU_0>, 456 <&clkc CLKID_VPU>, /* Glitch free mux */ 457 <&clkc CLKID_VAPB_0_SEL>, 458 <&clkc CLKID_VAPB_0>, 459 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 460 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 461 <0>, /* Do Nothing */ 462 <&clkc CLKID_VPU_0>, 463 <&clkc CLKID_FCLK_DIV4>, 464 <0>, /* Do Nothing */ 465 <&clkc CLKID_VAPB_0>; 466 assigned-clock-rates = <0>, /* Do Nothing */ 467 <666666666>, 468 <0>, /* Do Nothing */ 469 <0>, /* Do Nothing */ 470 <250000000>, 471 <0>; /* Do Nothing */ 472 }; 473 474 ao_pinctrl: pinctrl@14 { 475 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 476 #address-cells = <2>; 477 #size-cells = <2>; 478 ranges; 479 480 gpio_ao: bank@14 { 481 reg = <0x0 0x14 0x0 0x8>, 482 <0x0 0x1c 0x0 0x8>, 483 <0x0 0x24 0x0 0x14>; 484 reg-names = "mux", 485 "ds", 486 "gpio"; 487 gpio-controller; 488 #gpio-cells = <2>; 489 gpio-ranges = <&ao_pinctrl 0 0 15>; 490 }; 491 492 uart_ao_a_pins: uart-a-ao { 493 mux { 494 groups = "uart_ao_a_tx", 495 "uart_ao_a_rx"; 496 function = "uart_ao_a"; 497 bias-disable; 498 }; 499 }; 500 501 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 502 mux { 503 groups = "uart_ao_a_cts", 504 "uart_ao_a_rts"; 505 function = "uart_ao_a"; 506 bias-disable; 507 }; 508 }; 509 510 pwm_ao_a_pins: pwm-ao-a { 511 mux { 512 groups = "pwm_ao_a"; 513 function = "pwm_ao_a"; 514 bias-disable; 515 }; 516 }; 517 518 pwm_ao_b_pins: pwm-ao-b { 519 mux { 520 groups = "pwm_ao_b"; 521 function = "pwm_ao_b"; 522 bias-disable; 523 }; 524 }; 525 526 pwm_ao_c_4_pins: pwm-ao-c-4 { 527 mux { 528 groups = "pwm_ao_c_4"; 529 function = "pwm_ao_c"; 530 bias-disable; 531 }; 532 }; 533 534 pwm_ao_c_6_pins: pwm-ao-c-6 { 535 mux { 536 groups = "pwm_ao_c_6"; 537 function = "pwm_ao_c"; 538 bias-disable; 539 }; 540 }; 541 542 pwm_ao_d_5_pins: pwm-ao-d-5 { 543 mux { 544 groups = "pwm_ao_d_5"; 545 function = "pwm_ao_d"; 546 bias-disable; 547 }; 548 }; 549 550 pwm_ao_d_10_pins: pwm-ao-d-10 { 551 mux { 552 groups = "pwm_ao_d_10"; 553 function = "pwm_ao_d"; 554 bias-disable; 555 }; 556 }; 557 558 pwm_ao_d_e_pins: pwm-ao-d-e { 559 mux { 560 groups = "pwm_ao_d_e"; 561 function = "pwm_ao_d"; 562 bias-disable; 563 }; 564 }; 565 }; 566 }; 567 568 cec_AO: cec@100 { 569 compatible = "amlogic,meson-gx-ao-cec"; 570 reg = <0x0 0x00100 0x0 0x14>; 571 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 572 clocks = <&clkc_AO CLKID_AO_CEC>; 573 clock-names = "core"; 574 status = "disabled"; 575 }; 576 577 sec_AO: ao-secure@140 { 578 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 579 reg = <0x0 0x140 0x0 0x140>; 580 amlogic,has-chip-id; 581 }; 582 583 cecb_AO: cec@280 { 584 compatible = "amlogic,meson-g12a-ao-cec"; 585 reg = <0x0 0x00280 0x0 0x1c>; 586 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 587 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 588 clock-names = "oscin"; 589 status = "disabled"; 590 }; 591 592 pwm_AO_cd: pwm@2000 { 593 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 594 reg = <0x0 0x2000 0x0 0x20>; 595 #pwm-cells = <3>; 596 status = "disabled"; 597 }; 598 599 uart_AO: serial@3000 { 600 compatible = "amlogic,meson-gx-uart", 601 "amlogic,meson-ao-uart"; 602 reg = <0x0 0x3000 0x0 0x18>; 603 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 604 clocks = <&xtal>, <&xtal>, <&xtal>; 605 clock-names = "xtal", "pclk", "baud"; 606 status = "disabled"; 607 }; 608 609 uart_AO_B: serial@4000 { 610 compatible = "amlogic,meson-gx-uart", 611 "amlogic,meson-ao-uart"; 612 reg = <0x0 0x4000 0x0 0x18>; 613 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 614 clocks = <&xtal>, <&xtal>, <&xtal>; 615 clock-names = "xtal", "pclk", "baud"; 616 status = "disabled"; 617 }; 618 619 pwm_AO_ab: pwm@7000 { 620 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 621 reg = <0x0 0x7000 0x0 0x20>; 622 #pwm-cells = <3>; 623 status = "disabled"; 624 }; 625 626 saradc: adc@9000 { 627 compatible = "amlogic,meson-g12a-saradc", 628 "amlogic,meson-saradc"; 629 reg = <0x0 0x9000 0x0 0x48>; 630 #io-channel-cells = <1>; 631 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 632 clocks = <&xtal>, 633 <&clkc_AO CLKID_AO_SAR_ADC>, 634 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 635 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 636 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 637 status = "disabled"; 638 }; 639 }; 640 641 vpu: vpu@ff900000 { 642 compatible = "amlogic,meson-g12a-vpu"; 643 reg = <0x0 0xff900000 0x0 0x100000>, 644 <0x0 0xff63c000 0x0 0x1000>; 645 reg-names = "vpu", "hhi"; 646 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 amlogic,canvas = <&canvas>; 650 power-domains = <&pwrc_vpu>; 651 652 /* CVBS VDAC output port */ 653 cvbs_vdac_port: port@0 { 654 reg = <0>; 655 }; 656 657 /* HDMI-TX output port */ 658 hdmi_tx_port: port@1 { 659 reg = <1>; 660 661 hdmi_tx_out: endpoint { 662 remote-endpoint = <&hdmi_tx_in>; 663 }; 664 }; 665 }; 666 667 gic: interrupt-controller@ffc01000 { 668 compatible = "arm,gic-400"; 669 reg = <0x0 0xffc01000 0 0x1000>, 670 <0x0 0xffc02000 0 0x2000>, 671 <0x0 0xffc04000 0 0x2000>, 672 <0x0 0xffc06000 0 0x2000>; 673 interrupt-controller; 674 interrupts = <GIC_PPI 9 675 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 676 #interrupt-cells = <3>; 677 #address-cells = <0>; 678 }; 679 680 cbus: bus@ffd00000 { 681 compatible = "simple-bus"; 682 reg = <0x0 0xffd00000 0x0 0x100000>; 683 #address-cells = <2>; 684 #size-cells = <2>; 685 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 686 687 reset: reset-controller@1004 { 688 compatible = "amlogic,meson-g12a-reset", 689 "amlogic,meson-axg-reset"; 690 reg = <0x0 0x1004 0x0 0x9c>; 691 #reset-cells = <1>; 692 }; 693 694 pwm_ef: pwm@19000 { 695 compatible = "amlogic,meson-g12a-ee-pwm"; 696 reg = <0x0 0x19000 0x0 0x20>; 697 #pwm-cells = <3>; 698 status = "disabled"; 699 }; 700 701 pwm_cd: pwm@1a000 { 702 compatible = "amlogic,meson-g12a-ee-pwm"; 703 reg = <0x0 0x1a000 0x0 0x20>; 704 #pwm-cells = <3>; 705 status = "disabled"; 706 }; 707 708 pwm_ab: pwm@1b000 { 709 compatible = "amlogic,meson-g12a-ee-pwm"; 710 reg = <0x0 0x1b000 0x0 0x20>; 711 #pwm-cells = <3>; 712 status = "disabled"; 713 }; 714 715 clk_msr: clock-measure@18000 { 716 compatible = "amlogic,meson-g12a-clk-measure"; 717 reg = <0x0 0x18000 0x0 0x10>; 718 }; 719 720 uart_C: serial@22000 { 721 compatible = "amlogic,meson-gx-uart"; 722 reg = <0x0 0x22000 0x0 0x18>; 723 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 724 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 725 clock-names = "xtal", "pclk", "baud"; 726 status = "disabled"; 727 }; 728 729 uart_B: serial@23000 { 730 compatible = "amlogic,meson-gx-uart"; 731 reg = <0x0 0x23000 0x0 0x18>; 732 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 733 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 734 clock-names = "xtal", "pclk", "baud"; 735 status = "disabled"; 736 }; 737 738 uart_A: serial@24000 { 739 compatible = "amlogic,meson-gx-uart"; 740 reg = <0x0 0x24000 0x0 0x18>; 741 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 742 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 743 clock-names = "xtal", "pclk", "baud"; 744 status = "disabled"; 745 }; 746 }; 747 748 usb: usb@ffe09000 { 749 status = "disabled"; 750 compatible = "amlogic,meson-g12a-usb-ctrl"; 751 reg = <0x0 0xffe09000 0x0 0xa0>; 752 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <2>; 754 #size-cells = <2>; 755 ranges; 756 757 clocks = <&clkc CLKID_USB>; 758 resets = <&reset RESET_USB>; 759 760 dr_mode = "otg"; 761 762 phys = <&usb2_phy0>, <&usb2_phy1>, 763 <&usb3_pcie_phy PHY_TYPE_USB3>; 764 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 765 766 dwc2: usb@ff400000 { 767 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 768 reg = <0x0 0xff400000 0x0 0x40000>; 769 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 771 clock-names = "ddr"; 772 phys = <&usb2_phy1>; 773 dr_mode = "peripheral"; 774 g-rx-fifo-size = <192>; 775 g-np-tx-fifo-size = <128>; 776 g-tx-fifo-size = <128 128 16 16 16>; 777 }; 778 779 dwc3: usb@ff500000 { 780 compatible = "snps,dwc3"; 781 reg = <0x0 0xff500000 0x0 0x100000>; 782 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 783 dr_mode = "host"; 784 snps,dis_u2_susphy_quirk; 785 snps,quirk-frame-length-adjustment; 786 }; 787 }; 788 789 mali: gpu@ffe40000 { 790 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 791 reg = <0x0 0xffe40000 0x0 0x40000>; 792 interrupt-parent = <&gic>; 793 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 796 interrupt-names = "gpu", "mmu", "job"; 797 clocks = <&clkc CLKID_MALI>; 798 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 799 800 /* 801 * Mali clocking is provided by two identical clock paths 802 * MALI_0 and MALI_1 muxed to a single clock by a glitch 803 * free mux to safely change frequency while running. 804 */ 805 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 806 <&clkc CLKID_MALI_0>, 807 <&clkc CLKID_MALI>; /* Glitch free mux */ 808 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 809 <0>, /* Do Nothing */ 810 <&clkc CLKID_MALI_0>; 811 assigned-clock-rates = <0>, /* Do Nothing */ 812 <800000000>, 813 <0>; /* Do Nothing */ 814 }; 815 }; 816 817 timer { 818 compatible = "arm,armv8-timer"; 819 interrupts = <GIC_PPI 13 820 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 821 <GIC_PPI 14 822 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 823 <GIC_PPI 11 824 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 825 <GIC_PPI 10 826 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 827 }; 828 829 xtal: xtal-clk { 830 compatible = "fixed-clock"; 831 clock-frequency = <24000000>; 832 clock-output-names = "xtal"; 833 #clock-cells = <0>; 834 }; 835 836}; 837