1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 14/ { 15 compatible = "amlogic,g12a"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <0x2>; 23 #size-cells = <0x0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0 0x1>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x2>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x3>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 l2: l2-cache0 { 58 compatible = "cache"; 59 }; 60 }; 61 62 efuse: efuse { 63 compatible = "amlogic,meson-gxbb-efuse"; 64 clocks = <&clkc CLKID_EFUSE>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 read-only; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 81 secmon_reserved: secmon@5000000 { 82 reg = <0x0 0x05000000 0x0 0x300000>; 83 no-map; 84 }; 85 86 linux,cma { 87 compatible = "shared-dma-pool"; 88 reusable; 89 size = <0x0 0x10000000>; 90 alignment = <0x0 0x400000>; 91 linux,cma-default; 92 }; 93 }; 94 95 sm: secure-monitor { 96 compatible = "amlogic,meson-gxbb-sm"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 apb: bus@ff600000 { 106 compatible = "simple-bus"; 107 reg = <0x0 0xff600000 0x0 0x200000>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111 112 hdmi_tx: hdmi-tx@0 { 113 compatible = "amlogic,meson-g12a-dw-hdmi"; 114 reg = <0x0 0x0 0x0 0x10000>; 115 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 116 resets = <&reset RESET_HDMITX_CAPB3>, 117 <&reset RESET_HDMITX_PHY>, 118 <&reset RESET_HDMITX>; 119 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 120 clocks = <&clkc CLKID_HDMI>, 121 <&clkc CLKID_HTX_PCLK>, 122 <&clkc CLKID_VPU_INTR>; 123 clock-names = "isfr", "iahb", "venci"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* VPU VENC Input */ 129 hdmi_tx_venc_port: port@0 { 130 reg = <0>; 131 132 hdmi_tx_in: endpoint { 133 remote-endpoint = <&hdmi_tx_out>; 134 }; 135 }; 136 137 /* TMDS Output */ 138 hdmi_tx_tmds_port: port@1 { 139 reg = <1>; 140 }; 141 }; 142 143 periphs: bus@34400 { 144 compatible = "simple-bus"; 145 reg = <0x0 0x34400 0x0 0x400>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 149 150 periphs_pinctrl: pinctrl@40 { 151 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 gpio: bank@40 { 157 reg = <0x0 0x40 0x0 0x4c>, 158 <0x0 0xe8 0x0 0x18>, 159 <0x0 0x120 0x0 0x18>, 160 <0x0 0x2c0 0x0 0x40>, 161 <0x0 0x340 0x0 0x1c>; 162 reg-names = "gpio", 163 "pull", 164 "pull-enable", 165 "mux", 166 "ds"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 0 86>; 170 }; 171 172 cec_ao_a_h_pins: cec_ao_a_h { 173 mux { 174 groups = "cec_ao_a_h"; 175 function = "cec_ao_a_h"; 176 bias-disable; 177 }; 178 }; 179 180 cec_ao_b_h_pins: cec_ao_b_h { 181 mux { 182 groups = "cec_ao_b_h"; 183 function = "cec_ao_b_h"; 184 bias-disable; 185 }; 186 }; 187 188 emmc_pins: emmc { 189 mux-0 { 190 groups = "emmc_nand_d0", 191 "emmc_nand_d1", 192 "emmc_nand_d2", 193 "emmc_nand_d3", 194 "emmc_nand_d4", 195 "emmc_nand_d5", 196 "emmc_nand_d6", 197 "emmc_nand_d7", 198 "emmc_cmd"; 199 function = "emmc"; 200 bias-pull-up; 201 drive-strength-microamp = <4000>; 202 }; 203 204 mux-1 { 205 groups = "emmc_clk"; 206 function = "emmc"; 207 bias-disable; 208 drive-strength-microamp = <4000>; 209 }; 210 }; 211 212 emmc_ds_pins: emmc-ds { 213 mux { 214 groups = "emmc_nand_ds"; 215 function = "emmc"; 216 bias-pull-down; 217 drive-strength-microamp = <4000>; 218 }; 219 }; 220 221 emmc_clk_gate_pins: emmc_clk_gate { 222 mux { 223 groups = "BOOT_8"; 224 function = "gpio_periphs"; 225 bias-pull-down; 226 drive-strength-microamp = <4000>; 227 }; 228 }; 229 230 hdmitx_ddc_pins: hdmitx_ddc { 231 mux { 232 groups = "hdmitx_sda", 233 "hdmitx_sck"; 234 function = "hdmitx"; 235 bias-disable; 236 }; 237 }; 238 239 hdmitx_hpd_pins: hdmitx_hpd { 240 mux { 241 groups = "hdmitx_hpd_in"; 242 function = "hdmitx"; 243 bias-disable; 244 }; 245 }; 246 247 248 i2c0_sda_c_pins: i2c0-sda-c { 249 mux { 250 groups = "i2c0_sda_c"; 251 function = "i2c0"; 252 bias-disable; 253 drive-strength-microamp = <3000>; 254 255 }; 256 }; 257 258 i2c0_sck_c_pins: i2c0-sck-c { 259 mux { 260 groups = "i2c0_sck_c"; 261 function = "i2c0"; 262 bias-disable; 263 drive-strength-microamp = <3000>; 264 }; 265 }; 266 267 i2c0_sda_z0_pins: i2c0-sda-z0 { 268 mux { 269 groups = "i2c0_sda_z0"; 270 function = "i2c0"; 271 bias-disable; 272 drive-strength-microamp = <3000>; 273 }; 274 }; 275 276 i2c0_sck_z1_pins: i2c0-sck-z1 { 277 mux { 278 groups = "i2c0_sck_z1"; 279 function = "i2c0"; 280 bias-disable; 281 drive-strength-microamp = <3000>; 282 }; 283 }; 284 285 i2c0_sda_z7_pins: i2c0-sda-z7 { 286 mux { 287 groups = "i2c0_sda_z7"; 288 function = "i2c0"; 289 bias-disable; 290 drive-strength-microamp = <3000>; 291 }; 292 }; 293 294 i2c0_sda_z8_pins: i2c0-sda-z8 { 295 mux { 296 groups = "i2c0_sda_z8"; 297 function = "i2c0"; 298 bias-disable; 299 drive-strength-microamp = <3000>; 300 }; 301 }; 302 303 i2c1_sda_x_pins: i2c1-sda-x { 304 mux { 305 groups = "i2c1_sda_x"; 306 function = "i2c1"; 307 bias-disable; 308 drive-strength-microamp = <3000>; 309 }; 310 }; 311 312 i2c1_sck_x_pins: i2c1-sck-x { 313 mux { 314 groups = "i2c1_sck_x"; 315 function = "i2c1"; 316 bias-disable; 317 drive-strength-microamp = <3000>; 318 }; 319 }; 320 321 i2c1_sda_h2_pins: i2c1-sda-h2 { 322 mux { 323 groups = "i2c1_sda_h2"; 324 function = "i2c1"; 325 bias-disable; 326 drive-strength-microamp = <3000>; 327 }; 328 }; 329 330 i2c1_sck_h3_pins: i2c1-sck-h3 { 331 mux { 332 groups = "i2c1_sck_h3"; 333 function = "i2c1"; 334 bias-disable; 335 drive-strength-microamp = <3000>; 336 }; 337 }; 338 339 i2c1_sda_h6_pins: i2c1-sda-h6 { 340 mux { 341 groups = "i2c1_sda_h6"; 342 function = "i2c1"; 343 bias-disable; 344 drive-strength-microamp = <3000>; 345 }; 346 }; 347 348 i2c1_sck_h7_pins: i2c1-sck-h7 { 349 mux { 350 groups = "i2c1_sck_h7"; 351 function = "i2c1"; 352 bias-disable; 353 drive-strength-microamp = <3000>; 354 }; 355 }; 356 357 i2c2_sda_x_pins: i2c2-sda-x { 358 mux { 359 groups = "i2c2_sda_x"; 360 function = "i2c2"; 361 bias-disable; 362 drive-strength-microamp = <3000>; 363 }; 364 }; 365 366 i2c2_sck_x_pins: i2c2-sck-x { 367 mux { 368 groups = "i2c2_sck_x"; 369 function = "i2c2"; 370 bias-disable; 371 drive-strength-microamp = <3000>; 372 }; 373 }; 374 375 i2c2_sda_z_pins: i2c2-sda-z { 376 mux { 377 groups = "i2c2_sda_z"; 378 function = "i2c2"; 379 bias-disable; 380 drive-strength-microamp = <3000>; 381 }; 382 }; 383 384 i2c2_sck_z_pins: i2c2-sck-z { 385 mux { 386 groups = "i2c2_sck_z"; 387 function = "i2c2"; 388 bias-disable; 389 drive-strength-microamp = <3000>; 390 }; 391 }; 392 393 i2c3_sda_h_pins: i2c3-sda-h { 394 mux { 395 groups = "i2c3_sda_h"; 396 function = "i2c3"; 397 bias-disable; 398 drive-strength-microamp = <3000>; 399 }; 400 }; 401 402 i2c3_sck_h_pins: i2c3-sck-h { 403 mux { 404 groups = "i2c3_sck_h"; 405 function = "i2c3"; 406 bias-disable; 407 drive-strength-microamp = <3000>; 408 }; 409 }; 410 411 i2c3_sda_a_pins: i2c3-sda-a { 412 mux { 413 groups = "i2c3_sda_a"; 414 function = "i2c3"; 415 bias-disable; 416 drive-strength-microamp = <3000>; 417 }; 418 }; 419 420 i2c3_sck_a_pins: i2c3-sck-a { 421 mux { 422 groups = "i2c3_sck_a"; 423 function = "i2c3"; 424 bias-disable; 425 drive-strength-microamp = <3000>; 426 }; 427 }; 428 429 pwm_a_pins: pwm-a { 430 mux { 431 groups = "pwm_a"; 432 function = "pwm_a"; 433 bias-disable; 434 }; 435 }; 436 437 pwm_b_x7_pins: pwm-b-x7 { 438 mux { 439 groups = "pwm_b_x7"; 440 function = "pwm_b"; 441 bias-disable; 442 }; 443 }; 444 445 pwm_b_x19_pins: pwm-b-x19 { 446 mux { 447 groups = "pwm_b_x19"; 448 function = "pwm_b"; 449 bias-disable; 450 }; 451 }; 452 453 pwm_c_c_pins: pwm-c-c { 454 mux { 455 groups = "pwm_c_c"; 456 function = "pwm_c"; 457 bias-disable; 458 }; 459 }; 460 461 pwm_c_x5_pins: pwm-c-x5 { 462 mux { 463 groups = "pwm_c_x5"; 464 function = "pwm_c"; 465 bias-disable; 466 }; 467 }; 468 469 pwm_c_x8_pins: pwm-c-x8 { 470 mux { 471 groups = "pwm_c_x8"; 472 function = "pwm_c"; 473 bias-disable; 474 }; 475 }; 476 477 pwm_d_x3_pins: pwm-d-x3 { 478 mux { 479 groups = "pwm_d_x3"; 480 function = "pwm_d"; 481 bias-disable; 482 }; 483 }; 484 485 pwm_d_x6_pins: pwm-d-x6 { 486 mux { 487 groups = "pwm_d_x6"; 488 function = "pwm_d"; 489 bias-disable; 490 }; 491 }; 492 493 pwm_e_pins: pwm-e { 494 mux { 495 groups = "pwm_e"; 496 function = "pwm_e"; 497 bias-disable; 498 }; 499 }; 500 501 pwm_f_x_pins: pwm-f-x { 502 mux { 503 groups = "pwm_f_x"; 504 function = "pwm_f"; 505 bias-disable; 506 }; 507 }; 508 509 pwm_f_h_pins: pwm-f-h { 510 mux { 511 groups = "pwm_f_h"; 512 function = "pwm_f"; 513 bias-disable; 514 }; 515 }; 516 517 sdcard_c_pins: sdcard_c { 518 mux-0 { 519 groups = "sdcard_d0_c", 520 "sdcard_d1_c", 521 "sdcard_d2_c", 522 "sdcard_d3_c", 523 "sdcard_cmd_c"; 524 function = "sdcard"; 525 bias-pull-up; 526 drive-strength-microamp = <4000>; 527 }; 528 529 mux-1 { 530 groups = "sdcard_clk_c"; 531 function = "sdcard"; 532 bias-disable; 533 drive-strength-microamp = <4000>; 534 }; 535 }; 536 537 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 538 mux { 539 groups = "GPIOC_4"; 540 function = "gpio_periphs"; 541 bias-pull-down; 542 drive-strength-microamp = <4000>; 543 }; 544 }; 545 546 sdcard_z_pins: sdcard_z { 547 mux-0 { 548 groups = "sdcard_d0_z", 549 "sdcard_d1_z", 550 "sdcard_d2_z", 551 "sdcard_d3_z", 552 "sdcard_cmd_z"; 553 function = "sdcard"; 554 bias-pull-up; 555 drive-strength-microamp = <4000>; 556 }; 557 558 mux-1 { 559 groups = "sdcard_clk_z"; 560 function = "sdcard"; 561 bias-disable; 562 drive-strength-microamp = <4000>; 563 }; 564 }; 565 566 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 567 mux { 568 groups = "GPIOZ_6"; 569 function = "gpio_periphs"; 570 bias-pull-down; 571 drive-strength-microamp = <4000>; 572 }; 573 }; 574 575 uart_a_pins: uart-a { 576 mux { 577 groups = "uart_a_tx", 578 "uart_a_rx"; 579 function = "uart_a"; 580 bias-disable; 581 }; 582 }; 583 584 uart_a_cts_rts_pins: uart-a-cts-rts { 585 mux { 586 groups = "uart_a_cts", 587 "uart_a_rts"; 588 function = "uart_a"; 589 bias-disable; 590 }; 591 }; 592 593 uart_b_pins: uart-b { 594 mux { 595 groups = "uart_b_tx", 596 "uart_b_rx"; 597 function = "uart_b"; 598 bias-disable; 599 }; 600 }; 601 602 uart_c_pins: uart-c { 603 mux { 604 groups = "uart_c_tx", 605 "uart_c_rx"; 606 function = "uart_c"; 607 bias-disable; 608 }; 609 }; 610 611 uart_c_cts_rts_pins: uart-c-cts-rts { 612 mux { 613 groups = "uart_c_cts", 614 "uart_c_rts"; 615 function = "uart_c"; 616 bias-disable; 617 }; 618 }; 619 }; 620 }; 621 622 usb2_phy0: phy@36000 { 623 compatible = "amlogic,g12a-usb2-phy"; 624 reg = <0x0 0x36000 0x0 0x2000>; 625 clocks = <&xtal>; 626 clock-names = "xtal"; 627 resets = <&reset RESET_USB_PHY20>; 628 reset-names = "phy"; 629 #phy-cells = <0>; 630 }; 631 632 dmc: bus@38000 { 633 compatible = "simple-bus"; 634 reg = <0x0 0x38000 0x0 0x400>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 638 639 canvas: video-lut@48 { 640 compatible = "amlogic,canvas"; 641 reg = <0x0 0x48 0x0 0x14>; 642 }; 643 }; 644 645 usb2_phy1: phy@3a000 { 646 compatible = "amlogic,g12a-usb2-phy"; 647 reg = <0x0 0x3a000 0x0 0x2000>; 648 clocks = <&xtal>; 649 clock-names = "xtal"; 650 resets = <&reset RESET_USB_PHY21>; 651 reset-names = "phy"; 652 #phy-cells = <0>; 653 }; 654 655 hiu: bus@3c000 { 656 compatible = "simple-bus"; 657 reg = <0x0 0x3c000 0x0 0x1400>; 658 #address-cells = <2>; 659 #size-cells = <2>; 660 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 661 662 hhi: system-controller@0 { 663 compatible = "amlogic,meson-gx-hhi-sysctrl", 664 "simple-mfd", "syscon"; 665 reg = <0 0 0 0x400>; 666 667 clkc: clock-controller { 668 compatible = "amlogic,g12a-clkc"; 669 #clock-cells = <1>; 670 clocks = <&xtal>; 671 clock-names = "xtal"; 672 }; 673 }; 674 }; 675 676 usb3_pcie_phy: phy@46000 { 677 compatible = "amlogic,g12a-usb3-pcie-phy"; 678 reg = <0x0 0x46000 0x0 0x2000>; 679 clocks = <&clkc CLKID_PCIE_PLL>; 680 clock-names = "ref_clk"; 681 resets = <&reset RESET_PCIE_PHY>; 682 reset-names = "phy"; 683 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 684 assigned-clock-rates = <100000000>; 685 #phy-cells = <1>; 686 }; 687 }; 688 689 aobus: bus@ff800000 { 690 compatible = "simple-bus"; 691 reg = <0x0 0xff800000 0x0 0x100000>; 692 #address-cells = <2>; 693 #size-cells = <2>; 694 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 695 696 rti: sys-ctrl@0 { 697 compatible = "amlogic,meson-gx-ao-sysctrl", 698 "simple-mfd", "syscon"; 699 reg = <0x0 0x0 0x0 0x100>; 700 #address-cells = <2>; 701 #size-cells = <2>; 702 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 703 704 clkc_AO: clock-controller { 705 compatible = "amlogic,meson-g12a-aoclkc"; 706 #clock-cells = <1>; 707 #reset-cells = <1>; 708 clocks = <&xtal>, <&clkc CLKID_CLK81>; 709 clock-names = "xtal", "mpeg-clk"; 710 }; 711 712 pwrc_vpu: power-controller-vpu { 713 compatible = "amlogic,meson-g12a-pwrc-vpu"; 714 #power-domain-cells = <0>; 715 amlogic,hhi-sysctrl = <&hhi>; 716 resets = <&reset RESET_VIU>, 717 <&reset RESET_VENC>, 718 <&reset RESET_VCBUS>, 719 <&reset RESET_BT656>, 720 <&reset RESET_RDMA>, 721 <&reset RESET_VENCI>, 722 <&reset RESET_VENCP>, 723 <&reset RESET_VDAC>, 724 <&reset RESET_VDI6>, 725 <&reset RESET_VENCL>, 726 <&reset RESET_VID_LOCK>; 727 clocks = <&clkc CLKID_VPU>, 728 <&clkc CLKID_VAPB>; 729 clock-names = "vpu", "vapb"; 730 /* 731 * VPU clocking is provided by two identical clock paths 732 * VPU_0 and VPU_1 muxed to a single clock by a glitch 733 * free mux to safely change frequency while running. 734 * Same for VAPB but with a final gate after the glitch free mux. 735 */ 736 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 737 <&clkc CLKID_VPU_0>, 738 <&clkc CLKID_VPU>, /* Glitch free mux */ 739 <&clkc CLKID_VAPB_0_SEL>, 740 <&clkc CLKID_VAPB_0>, 741 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 742 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 743 <0>, /* Do Nothing */ 744 <&clkc CLKID_VPU_0>, 745 <&clkc CLKID_FCLK_DIV4>, 746 <0>, /* Do Nothing */ 747 <&clkc CLKID_VAPB_0>; 748 assigned-clock-rates = <0>, /* Do Nothing */ 749 <666666666>, 750 <0>, /* Do Nothing */ 751 <0>, /* Do Nothing */ 752 <250000000>, 753 <0>; /* Do Nothing */ 754 }; 755 756 ao_pinctrl: pinctrl@14 { 757 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 758 #address-cells = <2>; 759 #size-cells = <2>; 760 ranges; 761 762 gpio_ao: bank@14 { 763 reg = <0x0 0x14 0x0 0x8>, 764 <0x0 0x1c 0x0 0x8>, 765 <0x0 0x24 0x0 0x14>; 766 reg-names = "mux", 767 "ds", 768 "gpio"; 769 gpio-controller; 770 #gpio-cells = <2>; 771 gpio-ranges = <&ao_pinctrl 0 0 15>; 772 }; 773 774 i2c_ao_sck_pins: i2c_ao_sck_pins { 775 mux { 776 groups = "i2c_ao_sck"; 777 function = "i2c_ao"; 778 bias-disable; 779 drive-strength-microamp = <3000>; 780 }; 781 }; 782 783 i2c_ao_sda_pins: i2c_ao_sda { 784 mux { 785 groups = "i2c_ao_sda"; 786 function = "i2c_ao"; 787 bias-disable; 788 drive-strength-microamp = <3000>; 789 }; 790 }; 791 792 i2c_ao_sck_e_pins: i2c_ao_sck_e { 793 mux { 794 groups = "i2c_ao_sck_e"; 795 function = "i2c_ao"; 796 bias-disable; 797 drive-strength-microamp = <3000>; 798 }; 799 }; 800 801 i2c_ao_sda_e_pins: i2c_ao_sda_e { 802 mux { 803 groups = "i2c_ao_sda_e"; 804 function = "i2c_ao"; 805 bias-disable; 806 drive-strength-microamp = <3000>; 807 }; 808 }; 809 810 uart_ao_a_pins: uart-a-ao { 811 mux { 812 groups = "uart_ao_a_tx", 813 "uart_ao_a_rx"; 814 function = "uart_ao_a"; 815 bias-disable; 816 }; 817 }; 818 819 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 820 mux { 821 groups = "uart_ao_a_cts", 822 "uart_ao_a_rts"; 823 function = "uart_ao_a"; 824 bias-disable; 825 }; 826 }; 827 828 pwm_ao_a_pins: pwm-ao-a { 829 mux { 830 groups = "pwm_ao_a"; 831 function = "pwm_ao_a"; 832 bias-disable; 833 }; 834 }; 835 836 pwm_ao_b_pins: pwm-ao-b { 837 mux { 838 groups = "pwm_ao_b"; 839 function = "pwm_ao_b"; 840 bias-disable; 841 }; 842 }; 843 844 pwm_ao_c_4_pins: pwm-ao-c-4 { 845 mux { 846 groups = "pwm_ao_c_4"; 847 function = "pwm_ao_c"; 848 bias-disable; 849 }; 850 }; 851 852 pwm_ao_c_6_pins: pwm-ao-c-6 { 853 mux { 854 groups = "pwm_ao_c_6"; 855 function = "pwm_ao_c"; 856 bias-disable; 857 }; 858 }; 859 860 pwm_ao_d_5_pins: pwm-ao-d-5 { 861 mux { 862 groups = "pwm_ao_d_5"; 863 function = "pwm_ao_d"; 864 bias-disable; 865 }; 866 }; 867 868 pwm_ao_d_10_pins: pwm-ao-d-10 { 869 mux { 870 groups = "pwm_ao_d_10"; 871 function = "pwm_ao_d"; 872 bias-disable; 873 }; 874 }; 875 876 pwm_ao_d_e_pins: pwm-ao-d-e { 877 mux { 878 groups = "pwm_ao_d_e"; 879 function = "pwm_ao_d"; 880 }; 881 }; 882 883 remote_input_ao_pins: remote-input-ao { 884 mux { 885 groups = "remote_ao_input"; 886 function = "remote_ao_input"; 887 bias-disable; 888 }; 889 }; 890 }; 891 }; 892 893 cec_AO: cec@100 { 894 compatible = "amlogic,meson-gx-ao-cec"; 895 reg = <0x0 0x00100 0x0 0x14>; 896 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 897 clocks = <&clkc_AO CLKID_AO_CEC>; 898 clock-names = "core"; 899 status = "disabled"; 900 }; 901 902 sec_AO: ao-secure@140 { 903 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 904 reg = <0x0 0x140 0x0 0x140>; 905 amlogic,has-chip-id; 906 }; 907 908 cecb_AO: cec@280 { 909 compatible = "amlogic,meson-g12a-ao-cec"; 910 reg = <0x0 0x00280 0x0 0x1c>; 911 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 912 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 913 clock-names = "oscin"; 914 status = "disabled"; 915 }; 916 917 pwm_AO_cd: pwm@2000 { 918 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 919 reg = <0x0 0x2000 0x0 0x20>; 920 #pwm-cells = <3>; 921 status = "disabled"; 922 }; 923 924 uart_AO: serial@3000 { 925 compatible = "amlogic,meson-gx-uart", 926 "amlogic,meson-ao-uart"; 927 reg = <0x0 0x3000 0x0 0x18>; 928 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 929 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 930 clock-names = "xtal", "pclk", "baud"; 931 status = "disabled"; 932 }; 933 934 uart_AO_B: serial@4000 { 935 compatible = "amlogic,meson-gx-uart", 936 "amlogic,meson-ao-uart"; 937 reg = <0x0 0x4000 0x0 0x18>; 938 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 939 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 940 clock-names = "xtal", "pclk", "baud"; 941 status = "disabled"; 942 }; 943 944 i2c_AO: i2c@5000 { 945 compatible = "amlogic,meson-axg-i2c"; 946 status = "disabled"; 947 reg = <0x0 0x05000 0x0 0x20>; 948 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 clocks = <&clkc CLKID_I2C>; 952 }; 953 954 pwm_AO_ab: pwm@7000 { 955 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 956 reg = <0x0 0x7000 0x0 0x20>; 957 #pwm-cells = <3>; 958 status = "disabled"; 959 }; 960 961 ir: ir@8000 { 962 compatible = "amlogic,meson-gxbb-ir"; 963 reg = <0x0 0x8000 0x0 0x20>; 964 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 965 status = "disabled"; 966 }; 967 968 saradc: adc@9000 { 969 compatible = "amlogic,meson-g12a-saradc", 970 "amlogic,meson-saradc"; 971 reg = <0x0 0x9000 0x0 0x48>; 972 #io-channel-cells = <1>; 973 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 974 clocks = <&xtal>, 975 <&clkc_AO CLKID_AO_SAR_ADC>, 976 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 977 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 978 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 979 status = "disabled"; 980 }; 981 }; 982 983 vpu: vpu@ff900000 { 984 compatible = "amlogic,meson-g12a-vpu"; 985 reg = <0x0 0xff900000 0x0 0x100000>, 986 <0x0 0xff63c000 0x0 0x1000>; 987 reg-names = "vpu", "hhi"; 988 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 amlogic,canvas = <&canvas>; 992 power-domains = <&pwrc_vpu>; 993 994 /* CVBS VDAC output port */ 995 cvbs_vdac_port: port@0 { 996 reg = <0>; 997 }; 998 999 /* HDMI-TX output port */ 1000 hdmi_tx_port: port@1 { 1001 reg = <1>; 1002 1003 hdmi_tx_out: endpoint { 1004 remote-endpoint = <&hdmi_tx_in>; 1005 }; 1006 }; 1007 }; 1008 1009 gic: interrupt-controller@ffc01000 { 1010 compatible = "arm,gic-400"; 1011 reg = <0x0 0xffc01000 0 0x1000>, 1012 <0x0 0xffc02000 0 0x2000>, 1013 <0x0 0xffc04000 0 0x2000>, 1014 <0x0 0xffc06000 0 0x2000>; 1015 interrupt-controller; 1016 interrupts = <GIC_PPI 9 1017 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1018 #interrupt-cells = <3>; 1019 #address-cells = <0>; 1020 }; 1021 1022 cbus: bus@ffd00000 { 1023 compatible = "simple-bus"; 1024 reg = <0x0 0xffd00000 0x0 0x100000>; 1025 #address-cells = <2>; 1026 #size-cells = <2>; 1027 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 1028 1029 reset: reset-controller@1004 { 1030 compatible = "amlogic,meson-g12a-reset", 1031 "amlogic,meson-axg-reset"; 1032 reg = <0x0 0x1004 0x0 0x9c>; 1033 #reset-cells = <1>; 1034 }; 1035 1036 pwm_ef: pwm@19000 { 1037 compatible = "amlogic,meson-g12a-ee-pwm"; 1038 reg = <0x0 0x19000 0x0 0x20>; 1039 #pwm-cells = <3>; 1040 status = "disabled"; 1041 }; 1042 1043 pwm_cd: pwm@1a000 { 1044 compatible = "amlogic,meson-g12a-ee-pwm"; 1045 reg = <0x0 0x1a000 0x0 0x20>; 1046 #pwm-cells = <3>; 1047 status = "disabled"; 1048 }; 1049 1050 pwm_ab: pwm@1b000 { 1051 compatible = "amlogic,meson-g12a-ee-pwm"; 1052 reg = <0x0 0x1b000 0x0 0x20>; 1053 #pwm-cells = <3>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c3: i2c@1c000 { 1058 compatible = "amlogic,meson-axg-i2c"; 1059 status = "disabled"; 1060 reg = <0x0 0x1c000 0x0 0x20>; 1061 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 clocks = <&clkc CLKID_I2C>; 1065 }; 1066 1067 i2c2: i2c@1d000 { 1068 compatible = "amlogic,meson-axg-i2c"; 1069 status = "disabled"; 1070 reg = <0x0 0x1d000 0x0 0x20>; 1071 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 clocks = <&clkc CLKID_I2C>; 1075 }; 1076 1077 i2c1: i2c@1e000 { 1078 compatible = "amlogic,meson-axg-i2c"; 1079 status = "disabled"; 1080 reg = <0x0 0x1e000 0x0 0x20>; 1081 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 clocks = <&clkc CLKID_I2C>; 1085 }; 1086 1087 i2c0: i2c@1f000 { 1088 compatible = "amlogic,meson-axg-i2c"; 1089 status = "disabled"; 1090 reg = <0x0 0x1f000 0x0 0x20>; 1091 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 clocks = <&clkc CLKID_I2C>; 1095 }; 1096 1097 clk_msr: clock-measure@18000 { 1098 compatible = "amlogic,meson-g12a-clk-measure"; 1099 reg = <0x0 0x18000 0x0 0x10>; 1100 }; 1101 1102 uart_C: serial@22000 { 1103 compatible = "amlogic,meson-gx-uart"; 1104 reg = <0x0 0x22000 0x0 0x18>; 1105 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 1106 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 1107 clock-names = "xtal", "pclk", "baud"; 1108 status = "disabled"; 1109 }; 1110 1111 uart_B: serial@23000 { 1112 compatible = "amlogic,meson-gx-uart"; 1113 reg = <0x0 0x23000 0x0 0x18>; 1114 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1115 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1116 clock-names = "xtal", "pclk", "baud"; 1117 status = "disabled"; 1118 }; 1119 1120 uart_A: serial@24000 { 1121 compatible = "amlogic,meson-gx-uart"; 1122 reg = <0x0 0x24000 0x0 0x18>; 1123 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1124 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1125 clock-names = "xtal", "pclk", "baud"; 1126 status = "disabled"; 1127 }; 1128 }; 1129 1130 sd_emmc_b: sd@ffe05000 { 1131 compatible = "amlogic,meson-axg-mmc"; 1132 reg = <0x0 0xffe05000 0x0 0x800>; 1133 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 1134 status = "disabled"; 1135 clocks = <&clkc CLKID_SD_EMMC_B>, 1136 <&clkc CLKID_SD_EMMC_B_CLK0>, 1137 <&clkc CLKID_FCLK_DIV2>; 1138 clock-names = "core", "clkin0", "clkin1"; 1139 resets = <&reset RESET_SD_EMMC_B>; 1140 }; 1141 1142 sd_emmc_c: mmc@ffe07000 { 1143 compatible = "amlogic,meson-axg-mmc"; 1144 reg = <0x0 0xffe07000 0x0 0x800>; 1145 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 1146 status = "disabled"; 1147 clocks = <&clkc CLKID_SD_EMMC_C>, 1148 <&clkc CLKID_SD_EMMC_C_CLK0>, 1149 <&clkc CLKID_FCLK_DIV2>; 1150 clock-names = "core", "clkin0", "clkin1"; 1151 resets = <&reset RESET_SD_EMMC_C>; 1152 }; 1153 1154 usb: usb@ffe09000 { 1155 status = "disabled"; 1156 compatible = "amlogic,meson-g12a-usb-ctrl"; 1157 reg = <0x0 0xffe09000 0x0 0xa0>; 1158 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <2>; 1160 #size-cells = <2>; 1161 ranges; 1162 1163 clocks = <&clkc CLKID_USB>; 1164 resets = <&reset RESET_USB>; 1165 1166 dr_mode = "otg"; 1167 1168 phys = <&usb2_phy0>, <&usb2_phy1>, 1169 <&usb3_pcie_phy PHY_TYPE_USB3>; 1170 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 1171 1172 dwc2: usb@ff400000 { 1173 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 1174 reg = <0x0 0xff400000 0x0 0x40000>; 1175 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 1177 clock-names = "ddr"; 1178 phys = <&usb2_phy1>; 1179 dr_mode = "peripheral"; 1180 g-rx-fifo-size = <192>; 1181 g-np-tx-fifo-size = <128>; 1182 g-tx-fifo-size = <128 128 16 16 16>; 1183 }; 1184 1185 dwc3: usb@ff500000 { 1186 compatible = "snps,dwc3"; 1187 reg = <0x0 0xff500000 0x0 0x100000>; 1188 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1189 dr_mode = "host"; 1190 snps,dis_u2_susphy_quirk; 1191 snps,quirk-frame-length-adjustment; 1192 }; 1193 }; 1194 1195 mali: gpu@ffe40000 { 1196 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 1197 reg = <0x0 0xffe40000 0x0 0x40000>; 1198 interrupt-parent = <&gic>; 1199 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1202 interrupt-names = "gpu", "mmu", "job"; 1203 clocks = <&clkc CLKID_MALI>; 1204 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 1205 1206 /* 1207 * Mali clocking is provided by two identical clock paths 1208 * MALI_0 and MALI_1 muxed to a single clock by a glitch 1209 * free mux to safely change frequency while running. 1210 */ 1211 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 1212 <&clkc CLKID_MALI_0>, 1213 <&clkc CLKID_MALI>; /* Glitch free mux */ 1214 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 1215 <0>, /* Do Nothing */ 1216 <&clkc CLKID_MALI_0>; 1217 assigned-clock-rates = <0>, /* Do Nothing */ 1218 <800000000>, 1219 <0>; /* Do Nothing */ 1220 }; 1221 }; 1222 1223 timer { 1224 compatible = "arm,armv8-timer"; 1225 interrupts = <GIC_PPI 13 1226 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1227 <GIC_PPI 14 1228 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1229 <GIC_PPI 11 1230 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1231 <GIC_PPI 10 1232 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1233 }; 1234 1235 xtal: xtal-clk { 1236 compatible = "fixed-clock"; 1237 clock-frequency = <24000000>; 1238 clock-output-names = "xtal"; 1239 #clock-cells = <0>; 1240 }; 1241 1242}; 1243