1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 14 15/ { 16 compatible = "amlogic,g12a"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <0x2>; 24 #size-cells = <0x0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53"; 29 reg = <0x0 0x0>; 30 enable-method = "psci"; 31 next-level-cache = <&l2>; 32 }; 33 34 cpu1: cpu@1 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0 0x1>; 38 enable-method = "psci"; 39 next-level-cache = <&l2>; 40 }; 41 42 cpu2: cpu@2 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53"; 45 reg = <0x0 0x2>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 }; 49 50 cpu3: cpu@3 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x3>; 54 enable-method = "psci"; 55 next-level-cache = <&l2>; 56 }; 57 58 l2: l2-cache0 { 59 compatible = "cache"; 60 }; 61 }; 62 63 efuse: efuse { 64 compatible = "amlogic,meson-gxbb-efuse"; 65 clocks = <&clkc CLKID_EFUSE>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 read-only; 69 }; 70 71 psci { 72 compatible = "arm,psci-1.0"; 73 method = "smc"; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 82 secmon_reserved: secmon@5000000 { 83 reg = <0x0 0x05000000 0x0 0x300000>; 84 no-map; 85 }; 86 87 linux,cma { 88 compatible = "shared-dma-pool"; 89 reusable; 90 size = <0x0 0x10000000>; 91 alignment = <0x0 0x400000>; 92 linux,cma-default; 93 }; 94 }; 95 96 sm: secure-monitor { 97 compatible = "amlogic,meson-gxbb-sm"; 98 }; 99 100 soc { 101 compatible = "simple-bus"; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 106 apb: bus@ff600000 { 107 compatible = "simple-bus"; 108 reg = <0x0 0xff600000 0x0 0x200000>; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 112 113 hdmi_tx: hdmi-tx@0 { 114 compatible = "amlogic,meson-g12a-dw-hdmi"; 115 reg = <0x0 0x0 0x0 0x10000>; 116 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 117 resets = <&reset RESET_HDMITX_CAPB3>, 118 <&reset RESET_HDMITX_PHY>, 119 <&reset RESET_HDMITX>; 120 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 121 clocks = <&clkc CLKID_HDMI>, 122 <&clkc CLKID_HTX_PCLK>, 123 <&clkc CLKID_VPU_INTR>; 124 clock-names = "isfr", "iahb", "venci"; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 status = "disabled"; 128 129 /* VPU VENC Input */ 130 hdmi_tx_venc_port: port@0 { 131 reg = <0>; 132 133 hdmi_tx_in: endpoint { 134 remote-endpoint = <&hdmi_tx_out>; 135 }; 136 }; 137 138 /* TMDS Output */ 139 hdmi_tx_tmds_port: port@1 { 140 reg = <1>; 141 }; 142 }; 143 144 periphs: bus@34400 { 145 compatible = "simple-bus"; 146 reg = <0x0 0x34400 0x0 0x400>; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 150 151 periphs_pinctrl: pinctrl@40 { 152 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 153 #address-cells = <2>; 154 #size-cells = <2>; 155 ranges; 156 157 gpio: bank@40 { 158 reg = <0x0 0x40 0x0 0x4c>, 159 <0x0 0xe8 0x0 0x18>, 160 <0x0 0x120 0x0 0x18>, 161 <0x0 0x2c0 0x0 0x40>, 162 <0x0 0x340 0x0 0x1c>; 163 reg-names = "gpio", 164 "pull", 165 "pull-enable", 166 "mux", 167 "ds"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 gpio-ranges = <&periphs_pinctrl 0 0 86>; 171 }; 172 173 cec_ao_a_h_pins: cec_ao_a_h { 174 mux { 175 groups = "cec_ao_a_h"; 176 function = "cec_ao_a_h"; 177 bias-disable; 178 }; 179 }; 180 181 cec_ao_b_h_pins: cec_ao_b_h { 182 mux { 183 groups = "cec_ao_b_h"; 184 function = "cec_ao_b_h"; 185 bias-disable; 186 }; 187 }; 188 189 emmc_pins: emmc { 190 mux-0 { 191 groups = "emmc_nand_d0", 192 "emmc_nand_d1", 193 "emmc_nand_d2", 194 "emmc_nand_d3", 195 "emmc_nand_d4", 196 "emmc_nand_d5", 197 "emmc_nand_d6", 198 "emmc_nand_d7", 199 "emmc_cmd"; 200 function = "emmc"; 201 bias-pull-up; 202 drive-strength-microamp = <4000>; 203 }; 204 205 mux-1 { 206 groups = "emmc_clk"; 207 function = "emmc"; 208 bias-disable; 209 drive-strength-microamp = <4000>; 210 }; 211 }; 212 213 emmc_ds_pins: emmc-ds { 214 mux { 215 groups = "emmc_nand_ds"; 216 function = "emmc"; 217 bias-pull-down; 218 drive-strength-microamp = <4000>; 219 }; 220 }; 221 222 emmc_clk_gate_pins: emmc_clk_gate { 223 mux { 224 groups = "BOOT_8"; 225 function = "gpio_periphs"; 226 bias-pull-down; 227 drive-strength-microamp = <4000>; 228 }; 229 }; 230 231 hdmitx_ddc_pins: hdmitx_ddc { 232 mux { 233 groups = "hdmitx_sda", 234 "hdmitx_sck"; 235 function = "hdmitx"; 236 bias-disable; 237 }; 238 }; 239 240 hdmitx_hpd_pins: hdmitx_hpd { 241 mux { 242 groups = "hdmitx_hpd_in"; 243 function = "hdmitx"; 244 bias-disable; 245 }; 246 }; 247 248 249 i2c0_sda_c_pins: i2c0-sda-c { 250 mux { 251 groups = "i2c0_sda_c"; 252 function = "i2c0"; 253 bias-disable; 254 drive-strength-microamp = <3000>; 255 256 }; 257 }; 258 259 i2c0_sck_c_pins: i2c0-sck-c { 260 mux { 261 groups = "i2c0_sck_c"; 262 function = "i2c0"; 263 bias-disable; 264 drive-strength-microamp = <3000>; 265 }; 266 }; 267 268 i2c0_sda_z0_pins: i2c0-sda-z0 { 269 mux { 270 groups = "i2c0_sda_z0"; 271 function = "i2c0"; 272 bias-disable; 273 drive-strength-microamp = <3000>; 274 }; 275 }; 276 277 i2c0_sck_z1_pins: i2c0-sck-z1 { 278 mux { 279 groups = "i2c0_sck_z1"; 280 function = "i2c0"; 281 bias-disable; 282 drive-strength-microamp = <3000>; 283 }; 284 }; 285 286 i2c0_sda_z7_pins: i2c0-sda-z7 { 287 mux { 288 groups = "i2c0_sda_z7"; 289 function = "i2c0"; 290 bias-disable; 291 drive-strength-microamp = <3000>; 292 }; 293 }; 294 295 i2c0_sda_z8_pins: i2c0-sda-z8 { 296 mux { 297 groups = "i2c0_sda_z8"; 298 function = "i2c0"; 299 bias-disable; 300 drive-strength-microamp = <3000>; 301 }; 302 }; 303 304 i2c1_sda_x_pins: i2c1-sda-x { 305 mux { 306 groups = "i2c1_sda_x"; 307 function = "i2c1"; 308 bias-disable; 309 drive-strength-microamp = <3000>; 310 }; 311 }; 312 313 i2c1_sck_x_pins: i2c1-sck-x { 314 mux { 315 groups = "i2c1_sck_x"; 316 function = "i2c1"; 317 bias-disable; 318 drive-strength-microamp = <3000>; 319 }; 320 }; 321 322 i2c1_sda_h2_pins: i2c1-sda-h2 { 323 mux { 324 groups = "i2c1_sda_h2"; 325 function = "i2c1"; 326 bias-disable; 327 drive-strength-microamp = <3000>; 328 }; 329 }; 330 331 i2c1_sck_h3_pins: i2c1-sck-h3 { 332 mux { 333 groups = "i2c1_sck_h3"; 334 function = "i2c1"; 335 bias-disable; 336 drive-strength-microamp = <3000>; 337 }; 338 }; 339 340 i2c1_sda_h6_pins: i2c1-sda-h6 { 341 mux { 342 groups = "i2c1_sda_h6"; 343 function = "i2c1"; 344 bias-disable; 345 drive-strength-microamp = <3000>; 346 }; 347 }; 348 349 i2c1_sck_h7_pins: i2c1-sck-h7 { 350 mux { 351 groups = "i2c1_sck_h7"; 352 function = "i2c1"; 353 bias-disable; 354 drive-strength-microamp = <3000>; 355 }; 356 }; 357 358 i2c2_sda_x_pins: i2c2-sda-x { 359 mux { 360 groups = "i2c2_sda_x"; 361 function = "i2c2"; 362 bias-disable; 363 drive-strength-microamp = <3000>; 364 }; 365 }; 366 367 i2c2_sck_x_pins: i2c2-sck-x { 368 mux { 369 groups = "i2c2_sck_x"; 370 function = "i2c2"; 371 bias-disable; 372 drive-strength-microamp = <3000>; 373 }; 374 }; 375 376 i2c2_sda_z_pins: i2c2-sda-z { 377 mux { 378 groups = "i2c2_sda_z"; 379 function = "i2c2"; 380 bias-disable; 381 drive-strength-microamp = <3000>; 382 }; 383 }; 384 385 i2c2_sck_z_pins: i2c2-sck-z { 386 mux { 387 groups = "i2c2_sck_z"; 388 function = "i2c2"; 389 bias-disable; 390 drive-strength-microamp = <3000>; 391 }; 392 }; 393 394 i2c3_sda_h_pins: i2c3-sda-h { 395 mux { 396 groups = "i2c3_sda_h"; 397 function = "i2c3"; 398 bias-disable; 399 drive-strength-microamp = <3000>; 400 }; 401 }; 402 403 i2c3_sck_h_pins: i2c3-sck-h { 404 mux { 405 groups = "i2c3_sck_h"; 406 function = "i2c3"; 407 bias-disable; 408 drive-strength-microamp = <3000>; 409 }; 410 }; 411 412 i2c3_sda_a_pins: i2c3-sda-a { 413 mux { 414 groups = "i2c3_sda_a"; 415 function = "i2c3"; 416 bias-disable; 417 drive-strength-microamp = <3000>; 418 }; 419 }; 420 421 i2c3_sck_a_pins: i2c3-sck-a { 422 mux { 423 groups = "i2c3_sck_a"; 424 function = "i2c3"; 425 bias-disable; 426 drive-strength-microamp = <3000>; 427 }; 428 }; 429 430 pwm_a_pins: pwm-a { 431 mux { 432 groups = "pwm_a"; 433 function = "pwm_a"; 434 bias-disable; 435 }; 436 }; 437 438 pwm_b_x7_pins: pwm-b-x7 { 439 mux { 440 groups = "pwm_b_x7"; 441 function = "pwm_b"; 442 bias-disable; 443 }; 444 }; 445 446 pwm_b_x19_pins: pwm-b-x19 { 447 mux { 448 groups = "pwm_b_x19"; 449 function = "pwm_b"; 450 bias-disable; 451 }; 452 }; 453 454 pwm_c_c_pins: pwm-c-c { 455 mux { 456 groups = "pwm_c_c"; 457 function = "pwm_c"; 458 bias-disable; 459 }; 460 }; 461 462 pwm_c_x5_pins: pwm-c-x5 { 463 mux { 464 groups = "pwm_c_x5"; 465 function = "pwm_c"; 466 bias-disable; 467 }; 468 }; 469 470 pwm_c_x8_pins: pwm-c-x8 { 471 mux { 472 groups = "pwm_c_x8"; 473 function = "pwm_c"; 474 bias-disable; 475 }; 476 }; 477 478 pwm_d_x3_pins: pwm-d-x3 { 479 mux { 480 groups = "pwm_d_x3"; 481 function = "pwm_d"; 482 bias-disable; 483 }; 484 }; 485 486 pwm_d_x6_pins: pwm-d-x6 { 487 mux { 488 groups = "pwm_d_x6"; 489 function = "pwm_d"; 490 bias-disable; 491 }; 492 }; 493 494 pwm_e_pins: pwm-e { 495 mux { 496 groups = "pwm_e"; 497 function = "pwm_e"; 498 bias-disable; 499 }; 500 }; 501 502 pwm_f_x_pins: pwm-f-x { 503 mux { 504 groups = "pwm_f_x"; 505 function = "pwm_f"; 506 bias-disable; 507 }; 508 }; 509 510 pwm_f_h_pins: pwm-f-h { 511 mux { 512 groups = "pwm_f_h"; 513 function = "pwm_f"; 514 bias-disable; 515 }; 516 }; 517 518 sdcard_c_pins: sdcard_c { 519 mux-0 { 520 groups = "sdcard_d0_c", 521 "sdcard_d1_c", 522 "sdcard_d2_c", 523 "sdcard_d3_c", 524 "sdcard_cmd_c"; 525 function = "sdcard"; 526 bias-pull-up; 527 drive-strength-microamp = <4000>; 528 }; 529 530 mux-1 { 531 groups = "sdcard_clk_c"; 532 function = "sdcard"; 533 bias-disable; 534 drive-strength-microamp = <4000>; 535 }; 536 }; 537 538 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 539 mux { 540 groups = "GPIOC_4"; 541 function = "gpio_periphs"; 542 bias-pull-down; 543 drive-strength-microamp = <4000>; 544 }; 545 }; 546 547 sdcard_z_pins: sdcard_z { 548 mux-0 { 549 groups = "sdcard_d0_z", 550 "sdcard_d1_z", 551 "sdcard_d2_z", 552 "sdcard_d3_z", 553 "sdcard_cmd_z"; 554 function = "sdcard"; 555 bias-pull-up; 556 drive-strength-microamp = <4000>; 557 }; 558 559 mux-1 { 560 groups = "sdcard_clk_z"; 561 function = "sdcard"; 562 bias-disable; 563 drive-strength-microamp = <4000>; 564 }; 565 }; 566 567 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 568 mux { 569 groups = "GPIOZ_6"; 570 function = "gpio_periphs"; 571 bias-pull-down; 572 drive-strength-microamp = <4000>; 573 }; 574 }; 575 576 uart_a_pins: uart-a { 577 mux { 578 groups = "uart_a_tx", 579 "uart_a_rx"; 580 function = "uart_a"; 581 bias-disable; 582 }; 583 }; 584 585 uart_a_cts_rts_pins: uart-a-cts-rts { 586 mux { 587 groups = "uart_a_cts", 588 "uart_a_rts"; 589 function = "uart_a"; 590 bias-disable; 591 }; 592 }; 593 594 uart_b_pins: uart-b { 595 mux { 596 groups = "uart_b_tx", 597 "uart_b_rx"; 598 function = "uart_b"; 599 bias-disable; 600 }; 601 }; 602 603 uart_c_pins: uart-c { 604 mux { 605 groups = "uart_c_tx", 606 "uart_c_rx"; 607 function = "uart_c"; 608 bias-disable; 609 }; 610 }; 611 612 uart_c_cts_rts_pins: uart-c-cts-rts { 613 mux { 614 groups = "uart_c_cts", 615 "uart_c_rts"; 616 function = "uart_c"; 617 bias-disable; 618 }; 619 }; 620 }; 621 }; 622 623 usb2_phy0: phy@36000 { 624 compatible = "amlogic,g12a-usb2-phy"; 625 reg = <0x0 0x36000 0x0 0x2000>; 626 clocks = <&xtal>; 627 clock-names = "xtal"; 628 resets = <&reset RESET_USB_PHY20>; 629 reset-names = "phy"; 630 #phy-cells = <0>; 631 }; 632 633 dmc: bus@38000 { 634 compatible = "simple-bus"; 635 reg = <0x0 0x38000 0x0 0x400>; 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 639 640 canvas: video-lut@48 { 641 compatible = "amlogic,canvas"; 642 reg = <0x0 0x48 0x0 0x14>; 643 }; 644 }; 645 646 usb2_phy1: phy@3a000 { 647 compatible = "amlogic,g12a-usb2-phy"; 648 reg = <0x0 0x3a000 0x0 0x2000>; 649 clocks = <&xtal>; 650 clock-names = "xtal"; 651 resets = <&reset RESET_USB_PHY21>; 652 reset-names = "phy"; 653 #phy-cells = <0>; 654 }; 655 656 hiu: bus@3c000 { 657 compatible = "simple-bus"; 658 reg = <0x0 0x3c000 0x0 0x1400>; 659 #address-cells = <2>; 660 #size-cells = <2>; 661 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 662 663 hhi: system-controller@0 { 664 compatible = "amlogic,meson-gx-hhi-sysctrl", 665 "simple-mfd", "syscon"; 666 reg = <0 0 0 0x400>; 667 668 clkc: clock-controller { 669 compatible = "amlogic,g12a-clkc"; 670 #clock-cells = <1>; 671 clocks = <&xtal>; 672 clock-names = "xtal"; 673 }; 674 }; 675 }; 676 677 audio: bus@42000 { 678 compatible = "simple-bus"; 679 reg = <0x0 0x42000 0x0 0x2000>; 680 #address-cells = <2>; 681 #size-cells = <2>; 682 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 683 684 clkc_audio: clock-controller@0 { 685 status = "disabled"; 686 compatible = "amlogic,g12a-audio-clkc"; 687 reg = <0x0 0x0 0x0 0xb4>; 688 #clock-cells = <1>; 689 690 clocks = <&clkc CLKID_AUDIO>, 691 <&clkc CLKID_MPLL0>, 692 <&clkc CLKID_MPLL1>, 693 <&clkc CLKID_MPLL2>, 694 <&clkc CLKID_MPLL3>, 695 <&clkc CLKID_HIFI_PLL>, 696 <&clkc CLKID_FCLK_DIV3>, 697 <&clkc CLKID_FCLK_DIV4>, 698 <&clkc CLKID_GP0_PLL>; 699 clock-names = "pclk", 700 "mst_in0", 701 "mst_in1", 702 "mst_in2", 703 "mst_in3", 704 "mst_in4", 705 "mst_in5", 706 "mst_in6", 707 "mst_in7"; 708 709 resets = <&reset RESET_AUDIO>; 710 }; 711 712 arb: reset-controller@280 { 713 status = "disabled"; 714 compatible = "amlogic,meson-axg-audio-arb"; 715 reg = <0x0 0x280 0x0 0x4>; 716 #reset-cells = <1>; 717 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 718 }; 719 }; 720 721 usb3_pcie_phy: phy@46000 { 722 compatible = "amlogic,g12a-usb3-pcie-phy"; 723 reg = <0x0 0x46000 0x0 0x2000>; 724 clocks = <&clkc CLKID_PCIE_PLL>; 725 clock-names = "ref_clk"; 726 resets = <&reset RESET_PCIE_PHY>; 727 reset-names = "phy"; 728 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 729 assigned-clock-rates = <100000000>; 730 #phy-cells = <1>; 731 }; 732 }; 733 734 aobus: bus@ff800000 { 735 compatible = "simple-bus"; 736 reg = <0x0 0xff800000 0x0 0x100000>; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 740 741 rti: sys-ctrl@0 { 742 compatible = "amlogic,meson-gx-ao-sysctrl", 743 "simple-mfd", "syscon"; 744 reg = <0x0 0x0 0x0 0x100>; 745 #address-cells = <2>; 746 #size-cells = <2>; 747 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 748 749 clkc_AO: clock-controller { 750 compatible = "amlogic,meson-g12a-aoclkc"; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 clocks = <&xtal>, <&clkc CLKID_CLK81>; 754 clock-names = "xtal", "mpeg-clk"; 755 }; 756 757 pwrc_vpu: power-controller-vpu { 758 compatible = "amlogic,meson-g12a-pwrc-vpu"; 759 #power-domain-cells = <0>; 760 amlogic,hhi-sysctrl = <&hhi>; 761 resets = <&reset RESET_VIU>, 762 <&reset RESET_VENC>, 763 <&reset RESET_VCBUS>, 764 <&reset RESET_BT656>, 765 <&reset RESET_RDMA>, 766 <&reset RESET_VENCI>, 767 <&reset RESET_VENCP>, 768 <&reset RESET_VDAC>, 769 <&reset RESET_VDI6>, 770 <&reset RESET_VENCL>, 771 <&reset RESET_VID_LOCK>; 772 clocks = <&clkc CLKID_VPU>, 773 <&clkc CLKID_VAPB>; 774 clock-names = "vpu", "vapb"; 775 /* 776 * VPU clocking is provided by two identical clock paths 777 * VPU_0 and VPU_1 muxed to a single clock by a glitch 778 * free mux to safely change frequency while running. 779 * Same for VAPB but with a final gate after the glitch free mux. 780 */ 781 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 782 <&clkc CLKID_VPU_0>, 783 <&clkc CLKID_VPU>, /* Glitch free mux */ 784 <&clkc CLKID_VAPB_0_SEL>, 785 <&clkc CLKID_VAPB_0>, 786 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 787 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 788 <0>, /* Do Nothing */ 789 <&clkc CLKID_VPU_0>, 790 <&clkc CLKID_FCLK_DIV4>, 791 <0>, /* Do Nothing */ 792 <&clkc CLKID_VAPB_0>; 793 assigned-clock-rates = <0>, /* Do Nothing */ 794 <666666666>, 795 <0>, /* Do Nothing */ 796 <0>, /* Do Nothing */ 797 <250000000>, 798 <0>; /* Do Nothing */ 799 }; 800 801 ao_pinctrl: pinctrl@14 { 802 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 807 gpio_ao: bank@14 { 808 reg = <0x0 0x14 0x0 0x8>, 809 <0x0 0x1c 0x0 0x8>, 810 <0x0 0x24 0x0 0x14>; 811 reg-names = "mux", 812 "ds", 813 "gpio"; 814 gpio-controller; 815 #gpio-cells = <2>; 816 gpio-ranges = <&ao_pinctrl 0 0 15>; 817 }; 818 819 i2c_ao_sck_pins: i2c_ao_sck_pins { 820 mux { 821 groups = "i2c_ao_sck"; 822 function = "i2c_ao"; 823 bias-disable; 824 drive-strength-microamp = <3000>; 825 }; 826 }; 827 828 i2c_ao_sda_pins: i2c_ao_sda { 829 mux { 830 groups = "i2c_ao_sda"; 831 function = "i2c_ao"; 832 bias-disable; 833 drive-strength-microamp = <3000>; 834 }; 835 }; 836 837 i2c_ao_sck_e_pins: i2c_ao_sck_e { 838 mux { 839 groups = "i2c_ao_sck_e"; 840 function = "i2c_ao"; 841 bias-disable; 842 drive-strength-microamp = <3000>; 843 }; 844 }; 845 846 i2c_ao_sda_e_pins: i2c_ao_sda_e { 847 mux { 848 groups = "i2c_ao_sda_e"; 849 function = "i2c_ao"; 850 bias-disable; 851 drive-strength-microamp = <3000>; 852 }; 853 }; 854 855 uart_ao_a_pins: uart-a-ao { 856 mux { 857 groups = "uart_ao_a_tx", 858 "uart_ao_a_rx"; 859 function = "uart_ao_a"; 860 bias-disable; 861 }; 862 }; 863 864 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 865 mux { 866 groups = "uart_ao_a_cts", 867 "uart_ao_a_rts"; 868 function = "uart_ao_a"; 869 bias-disable; 870 }; 871 }; 872 873 pwm_ao_a_pins: pwm-ao-a { 874 mux { 875 groups = "pwm_ao_a"; 876 function = "pwm_ao_a"; 877 bias-disable; 878 }; 879 }; 880 881 pwm_ao_b_pins: pwm-ao-b { 882 mux { 883 groups = "pwm_ao_b"; 884 function = "pwm_ao_b"; 885 bias-disable; 886 }; 887 }; 888 889 pwm_ao_c_4_pins: pwm-ao-c-4 { 890 mux { 891 groups = "pwm_ao_c_4"; 892 function = "pwm_ao_c"; 893 bias-disable; 894 }; 895 }; 896 897 pwm_ao_c_6_pins: pwm-ao-c-6 { 898 mux { 899 groups = "pwm_ao_c_6"; 900 function = "pwm_ao_c"; 901 bias-disable; 902 }; 903 }; 904 905 pwm_ao_d_5_pins: pwm-ao-d-5 { 906 mux { 907 groups = "pwm_ao_d_5"; 908 function = "pwm_ao_d"; 909 bias-disable; 910 }; 911 }; 912 913 pwm_ao_d_10_pins: pwm-ao-d-10 { 914 mux { 915 groups = "pwm_ao_d_10"; 916 function = "pwm_ao_d"; 917 bias-disable; 918 }; 919 }; 920 921 pwm_ao_d_e_pins: pwm-ao-d-e { 922 mux { 923 groups = "pwm_ao_d_e"; 924 function = "pwm_ao_d"; 925 }; 926 }; 927 928 remote_input_ao_pins: remote-input-ao { 929 mux { 930 groups = "remote_ao_input"; 931 function = "remote_ao_input"; 932 bias-disable; 933 }; 934 }; 935 }; 936 }; 937 938 cec_AO: cec@100 { 939 compatible = "amlogic,meson-gx-ao-cec"; 940 reg = <0x0 0x00100 0x0 0x14>; 941 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 942 clocks = <&clkc_AO CLKID_AO_CEC>; 943 clock-names = "core"; 944 status = "disabled"; 945 }; 946 947 sec_AO: ao-secure@140 { 948 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 949 reg = <0x0 0x140 0x0 0x140>; 950 amlogic,has-chip-id; 951 }; 952 953 cecb_AO: cec@280 { 954 compatible = "amlogic,meson-g12a-ao-cec"; 955 reg = <0x0 0x00280 0x0 0x1c>; 956 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 957 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 958 clock-names = "oscin"; 959 status = "disabled"; 960 }; 961 962 pwm_AO_cd: pwm@2000 { 963 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 964 reg = <0x0 0x2000 0x0 0x20>; 965 #pwm-cells = <3>; 966 status = "disabled"; 967 }; 968 969 uart_AO: serial@3000 { 970 compatible = "amlogic,meson-gx-uart", 971 "amlogic,meson-ao-uart"; 972 reg = <0x0 0x3000 0x0 0x18>; 973 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 974 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 975 clock-names = "xtal", "pclk", "baud"; 976 status = "disabled"; 977 }; 978 979 uart_AO_B: serial@4000 { 980 compatible = "amlogic,meson-gx-uart", 981 "amlogic,meson-ao-uart"; 982 reg = <0x0 0x4000 0x0 0x18>; 983 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 984 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 985 clock-names = "xtal", "pclk", "baud"; 986 status = "disabled"; 987 }; 988 989 i2c_AO: i2c@5000 { 990 compatible = "amlogic,meson-axg-i2c"; 991 status = "disabled"; 992 reg = <0x0 0x05000 0x0 0x20>; 993 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 clocks = <&clkc CLKID_I2C>; 997 }; 998 999 pwm_AO_ab: pwm@7000 { 1000 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 1001 reg = <0x0 0x7000 0x0 0x20>; 1002 #pwm-cells = <3>; 1003 status = "disabled"; 1004 }; 1005 1006 ir: ir@8000 { 1007 compatible = "amlogic,meson-gxbb-ir"; 1008 reg = <0x0 0x8000 0x0 0x20>; 1009 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1010 status = "disabled"; 1011 }; 1012 1013 saradc: adc@9000 { 1014 compatible = "amlogic,meson-g12a-saradc", 1015 "amlogic,meson-saradc"; 1016 reg = <0x0 0x9000 0x0 0x48>; 1017 #io-channel-cells = <1>; 1018 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 1019 clocks = <&xtal>, 1020 <&clkc_AO CLKID_AO_SAR_ADC>, 1021 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1022 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1023 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1024 status = "disabled"; 1025 }; 1026 }; 1027 1028 vpu: vpu@ff900000 { 1029 compatible = "amlogic,meson-g12a-vpu"; 1030 reg = <0x0 0xff900000 0x0 0x100000>, 1031 <0x0 0xff63c000 0x0 0x1000>; 1032 reg-names = "vpu", "hhi"; 1033 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 amlogic,canvas = <&canvas>; 1037 power-domains = <&pwrc_vpu>; 1038 1039 /* CVBS VDAC output port */ 1040 cvbs_vdac_port: port@0 { 1041 reg = <0>; 1042 }; 1043 1044 /* HDMI-TX output port */ 1045 hdmi_tx_port: port@1 { 1046 reg = <1>; 1047 1048 hdmi_tx_out: endpoint { 1049 remote-endpoint = <&hdmi_tx_in>; 1050 }; 1051 }; 1052 }; 1053 1054 gic: interrupt-controller@ffc01000 { 1055 compatible = "arm,gic-400"; 1056 reg = <0x0 0xffc01000 0 0x1000>, 1057 <0x0 0xffc02000 0 0x2000>, 1058 <0x0 0xffc04000 0 0x2000>, 1059 <0x0 0xffc06000 0 0x2000>; 1060 interrupt-controller; 1061 interrupts = <GIC_PPI 9 1062 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1063 #interrupt-cells = <3>; 1064 #address-cells = <0>; 1065 }; 1066 1067 cbus: bus@ffd00000 { 1068 compatible = "simple-bus"; 1069 reg = <0x0 0xffd00000 0x0 0x100000>; 1070 #address-cells = <2>; 1071 #size-cells = <2>; 1072 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 1073 1074 reset: reset-controller@1004 { 1075 compatible = "amlogic,meson-g12a-reset", 1076 "amlogic,meson-axg-reset"; 1077 reg = <0x0 0x1004 0x0 0x9c>; 1078 #reset-cells = <1>; 1079 }; 1080 1081 pwm_ef: pwm@19000 { 1082 compatible = "amlogic,meson-g12a-ee-pwm"; 1083 reg = <0x0 0x19000 0x0 0x20>; 1084 #pwm-cells = <3>; 1085 status = "disabled"; 1086 }; 1087 1088 pwm_cd: pwm@1a000 { 1089 compatible = "amlogic,meson-g12a-ee-pwm"; 1090 reg = <0x0 0x1a000 0x0 0x20>; 1091 #pwm-cells = <3>; 1092 status = "disabled"; 1093 }; 1094 1095 pwm_ab: pwm@1b000 { 1096 compatible = "amlogic,meson-g12a-ee-pwm"; 1097 reg = <0x0 0x1b000 0x0 0x20>; 1098 #pwm-cells = <3>; 1099 status = "disabled"; 1100 }; 1101 1102 i2c3: i2c@1c000 { 1103 compatible = "amlogic,meson-axg-i2c"; 1104 status = "disabled"; 1105 reg = <0x0 0x1c000 0x0 0x20>; 1106 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 clocks = <&clkc CLKID_I2C>; 1110 }; 1111 1112 i2c2: i2c@1d000 { 1113 compatible = "amlogic,meson-axg-i2c"; 1114 status = "disabled"; 1115 reg = <0x0 0x1d000 0x0 0x20>; 1116 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 clocks = <&clkc CLKID_I2C>; 1120 }; 1121 1122 i2c1: i2c@1e000 { 1123 compatible = "amlogic,meson-axg-i2c"; 1124 status = "disabled"; 1125 reg = <0x0 0x1e000 0x0 0x20>; 1126 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 clocks = <&clkc CLKID_I2C>; 1130 }; 1131 1132 i2c0: i2c@1f000 { 1133 compatible = "amlogic,meson-axg-i2c"; 1134 status = "disabled"; 1135 reg = <0x0 0x1f000 0x0 0x20>; 1136 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 clocks = <&clkc CLKID_I2C>; 1140 }; 1141 1142 clk_msr: clock-measure@18000 { 1143 compatible = "amlogic,meson-g12a-clk-measure"; 1144 reg = <0x0 0x18000 0x0 0x10>; 1145 }; 1146 1147 uart_C: serial@22000 { 1148 compatible = "amlogic,meson-gx-uart"; 1149 reg = <0x0 0x22000 0x0 0x18>; 1150 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 1151 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 1152 clock-names = "xtal", "pclk", "baud"; 1153 status = "disabled"; 1154 }; 1155 1156 uart_B: serial@23000 { 1157 compatible = "amlogic,meson-gx-uart"; 1158 reg = <0x0 0x23000 0x0 0x18>; 1159 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1160 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1161 clock-names = "xtal", "pclk", "baud"; 1162 status = "disabled"; 1163 }; 1164 1165 uart_A: serial@24000 { 1166 compatible = "amlogic,meson-gx-uart"; 1167 reg = <0x0 0x24000 0x0 0x18>; 1168 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1169 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1170 clock-names = "xtal", "pclk", "baud"; 1171 status = "disabled"; 1172 }; 1173 }; 1174 1175 sd_emmc_b: sd@ffe05000 { 1176 compatible = "amlogic,meson-axg-mmc"; 1177 reg = <0x0 0xffe05000 0x0 0x800>; 1178 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 1179 status = "disabled"; 1180 clocks = <&clkc CLKID_SD_EMMC_B>, 1181 <&clkc CLKID_SD_EMMC_B_CLK0>, 1182 <&clkc CLKID_FCLK_DIV2>; 1183 clock-names = "core", "clkin0", "clkin1"; 1184 resets = <&reset RESET_SD_EMMC_B>; 1185 }; 1186 1187 sd_emmc_c: mmc@ffe07000 { 1188 compatible = "amlogic,meson-axg-mmc"; 1189 reg = <0x0 0xffe07000 0x0 0x800>; 1190 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 1191 status = "disabled"; 1192 clocks = <&clkc CLKID_SD_EMMC_C>, 1193 <&clkc CLKID_SD_EMMC_C_CLK0>, 1194 <&clkc CLKID_FCLK_DIV2>; 1195 clock-names = "core", "clkin0", "clkin1"; 1196 resets = <&reset RESET_SD_EMMC_C>; 1197 }; 1198 1199 usb: usb@ffe09000 { 1200 status = "disabled"; 1201 compatible = "amlogic,meson-g12a-usb-ctrl"; 1202 reg = <0x0 0xffe09000 0x0 0xa0>; 1203 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <2>; 1205 #size-cells = <2>; 1206 ranges; 1207 1208 clocks = <&clkc CLKID_USB>; 1209 resets = <&reset RESET_USB>; 1210 1211 dr_mode = "otg"; 1212 1213 phys = <&usb2_phy0>, <&usb2_phy1>, 1214 <&usb3_pcie_phy PHY_TYPE_USB3>; 1215 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 1216 1217 dwc2: usb@ff400000 { 1218 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 1219 reg = <0x0 0xff400000 0x0 0x40000>; 1220 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 1222 clock-names = "ddr"; 1223 phys = <&usb2_phy1>; 1224 dr_mode = "peripheral"; 1225 g-rx-fifo-size = <192>; 1226 g-np-tx-fifo-size = <128>; 1227 g-tx-fifo-size = <128 128 16 16 16>; 1228 }; 1229 1230 dwc3: usb@ff500000 { 1231 compatible = "snps,dwc3"; 1232 reg = <0x0 0xff500000 0x0 0x100000>; 1233 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1234 dr_mode = "host"; 1235 snps,dis_u2_susphy_quirk; 1236 snps,quirk-frame-length-adjustment; 1237 }; 1238 }; 1239 1240 mali: gpu@ffe40000 { 1241 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 1242 reg = <0x0 0xffe40000 0x0 0x40000>; 1243 interrupt-parent = <&gic>; 1244 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1247 interrupt-names = "gpu", "mmu", "job"; 1248 clocks = <&clkc CLKID_MALI>; 1249 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 1250 1251 /* 1252 * Mali clocking is provided by two identical clock paths 1253 * MALI_0 and MALI_1 muxed to a single clock by a glitch 1254 * free mux to safely change frequency while running. 1255 */ 1256 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 1257 <&clkc CLKID_MALI_0>, 1258 <&clkc CLKID_MALI>; /* Glitch free mux */ 1259 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 1260 <0>, /* Do Nothing */ 1261 <&clkc CLKID_MALI_0>; 1262 assigned-clock-rates = <0>, /* Do Nothing */ 1263 <800000000>, 1264 <0>; /* Do Nothing */ 1265 }; 1266 }; 1267 1268 timer { 1269 compatible = "arm,armv8-timer"; 1270 interrupts = <GIC_PPI 13 1271 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1272 <GIC_PPI 14 1273 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1274 <GIC_PPI 11 1275 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1276 <GIC_PPI 10 1277 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1278 }; 1279 1280 xtal: xtal-clk { 1281 compatible = "fixed-clock"; 1282 clock-frequency = <24000000>; 1283 clock-output-names = "xtal"; 1284 #clock-cells = <0>; 1285 }; 1286 1287}; 1288