1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include "meson-g12.dtsi"
7
8/ {
9	compatible = "amlogic,g12a";
10
11	cpus {
12		#address-cells = <0x2>;
13		#size-cells = <0x0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a53";
18			reg = <0x0 0x0>;
19			enable-method = "psci";
20			next-level-cache = <&l2>;
21			#cooling-cells = <2>;
22		};
23
24		cpu1: cpu@1 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a53";
27			reg = <0x0 0x1>;
28			enable-method = "psci";
29			next-level-cache = <&l2>;
30			#cooling-cells = <2>;
31		};
32
33		cpu2: cpu@2 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x0 0x2>;
37			enable-method = "psci";
38			next-level-cache = <&l2>;
39			#cooling-cells = <2>;
40		};
41
42		cpu3: cpu@3 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53";
45			reg = <0x0 0x3>;
46			enable-method = "psci";
47			next-level-cache = <&l2>;
48			#cooling-cells = <2>;
49		};
50
51		l2: l2-cache0 {
52			compatible = "cache";
53			cache-level = <2>;
54		};
55	};
56
57	cpu_opp_table: opp-table {
58		compatible = "operating-points-v2";
59		opp-shared;
60
61		opp-100000000 {
62			opp-hz = /bits/ 64 <100000000>;
63			opp-microvolt = <731000>;
64		};
65
66		opp-250000000 {
67			opp-hz = /bits/ 64 <250000000>;
68			opp-microvolt = <731000>;
69		};
70
71		opp-500000000 {
72			opp-hz = /bits/ 64 <500000000>;
73			opp-microvolt = <731000>;
74		};
75
76		opp-667000000 {
77			opp-hz = /bits/ 64 <666666666>;
78			opp-microvolt = <731000>;
79		};
80
81		opp-1000000000 {
82			opp-hz = /bits/ 64 <1000000000>;
83			opp-microvolt = <731000>;
84		};
85
86		opp-1200000000 {
87			opp-hz = /bits/ 64 <1200000000>;
88			opp-microvolt = <731000>;
89		};
90
91		opp-1398000000 {
92			opp-hz = /bits/ 64 <1398000000>;
93			opp-microvolt = <761000>;
94		};
95
96		opp-1512000000 {
97			opp-hz = /bits/ 64 <1512000000>;
98			opp-microvolt = <791000>;
99		};
100
101		opp-1608000000 {
102			opp-hz = /bits/ 64 <1608000000>;
103			opp-microvolt = <831000>;
104		};
105
106		opp-1704000000 {
107			opp-hz = /bits/ 64 <1704000000>;
108			opp-microvolt = <861000>;
109		};
110
111		opp-1800000000 {
112			opp-hz = /bits/ 64 <1800000000>;
113			opp-microvolt = <981000>;
114		};
115	};
116};
117
118&cpu_thermal {
119	cooling-maps {
120		map0 {
121			trip = <&cpu_passive>;
122			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
123					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
124					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
125					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
126		};
127
128		map1 {
129			trip = <&cpu_hot>;
130			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
131					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
132					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
133					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
134		};
135	};
136};
137