1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 14/ { 15 compatible = "amlogic,g12a"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <0x2>; 23 #size-cells = <0x0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0 0x1>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x2>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x3>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 l2: l2-cache0 { 58 compatible = "cache"; 59 }; 60 }; 61 62 efuse: efuse { 63 compatible = "amlogic,meson-gxbb-efuse"; 64 clocks = <&clkc CLKID_EFUSE>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 read-only; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 81 secmon_reserved: secmon@5000000 { 82 reg = <0x0 0x05000000 0x0 0x300000>; 83 no-map; 84 }; 85 86 linux,cma { 87 compatible = "shared-dma-pool"; 88 reusable; 89 size = <0x0 0x10000000>; 90 alignment = <0x0 0x400000>; 91 linux,cma-default; 92 }; 93 }; 94 95 sm: secure-monitor { 96 compatible = "amlogic,meson-gxbb-sm"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 apb: bus@ff600000 { 106 compatible = "simple-bus"; 107 reg = <0x0 0xff600000 0x0 0x200000>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111 112 hdmi_tx: hdmi-tx@0 { 113 compatible = "amlogic,meson-g12a-dw-hdmi"; 114 reg = <0x0 0x0 0x0 0x10000>; 115 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 116 resets = <&reset RESET_HDMITX_CAPB3>, 117 <&reset RESET_HDMITX_PHY>, 118 <&reset RESET_HDMITX>; 119 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 120 clocks = <&clkc CLKID_HDMI>, 121 <&clkc CLKID_HTX_PCLK>, 122 <&clkc CLKID_VPU_INTR>; 123 clock-names = "isfr", "iahb", "venci"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* VPU VENC Input */ 129 hdmi_tx_venc_port: port@0 { 130 reg = <0>; 131 132 hdmi_tx_in: endpoint { 133 remote-endpoint = <&hdmi_tx_out>; 134 }; 135 }; 136 137 /* TMDS Output */ 138 hdmi_tx_tmds_port: port@1 { 139 reg = <1>; 140 }; 141 }; 142 143 periphs: bus@34400 { 144 compatible = "simple-bus"; 145 reg = <0x0 0x34400 0x0 0x400>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 149 150 periphs_pinctrl: pinctrl@40 { 151 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 gpio: bank@40 { 157 reg = <0x0 0x40 0x0 0x4c>, 158 <0x0 0xe8 0x0 0x18>, 159 <0x0 0x120 0x0 0x18>, 160 <0x0 0x2c0 0x0 0x40>, 161 <0x0 0x340 0x0 0x1c>; 162 reg-names = "gpio", 163 "pull", 164 "pull-enable", 165 "mux", 166 "ds"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 0 86>; 170 }; 171 172 cec_ao_a_h_pins: cec_ao_a_h { 173 mux { 174 groups = "cec_ao_a_h"; 175 function = "cec_ao_a_h"; 176 bias-disable; 177 }; 178 }; 179 180 cec_ao_b_h_pins: cec_ao_b_h { 181 mux { 182 groups = "cec_ao_b_h"; 183 function = "cec_ao_b_h"; 184 bias-disable; 185 }; 186 }; 187 188 emmc_pins: emmc { 189 mux-0 { 190 groups = "emmc_nand_d0", 191 "emmc_nand_d1", 192 "emmc_nand_d2", 193 "emmc_nand_d3", 194 "emmc_nand_d4", 195 "emmc_nand_d5", 196 "emmc_nand_d6", 197 "emmc_nand_d7", 198 "emmc_cmd"; 199 function = "emmc"; 200 bias-pull-up; 201 drive-strength-microamp = <4000>; 202 }; 203 204 mux-1 { 205 groups = "emmc_clk"; 206 function = "emmc"; 207 bias-disable; 208 drive-strength-microamp = <4000>; 209 }; 210 }; 211 212 emmc_ds_pins: emmc-ds { 213 mux { 214 groups = "emmc_nand_ds"; 215 function = "emmc"; 216 bias-pull-down; 217 drive-strength-microamp = <4000>; 218 }; 219 }; 220 221 emmc_clk_gate_pins: emmc_clk_gate { 222 mux { 223 groups = "BOOT_8"; 224 function = "gpio_periphs"; 225 bias-pull-down; 226 drive-strength-microamp = <4000>; 227 }; 228 }; 229 230 hdmitx_ddc_pins: hdmitx_ddc { 231 mux { 232 groups = "hdmitx_sda", 233 "hdmitx_sck"; 234 function = "hdmitx"; 235 bias-disable; 236 }; 237 }; 238 239 hdmitx_hpd_pins: hdmitx_hpd { 240 mux { 241 groups = "hdmitx_hpd_in"; 242 function = "hdmitx"; 243 bias-disable; 244 }; 245 }; 246 247 pwm_a_pins: pwm-a { 248 mux { 249 groups = "pwm_a"; 250 function = "pwm_a"; 251 bias-disable; 252 }; 253 }; 254 255 pwm_b_x7_pins: pwm-b-x7 { 256 mux { 257 groups = "pwm_b_x7"; 258 function = "pwm_b"; 259 bias-disable; 260 }; 261 }; 262 263 pwm_b_x19_pins: pwm-b-x19 { 264 mux { 265 groups = "pwm_b_x19"; 266 function = "pwm_b"; 267 bias-disable; 268 }; 269 }; 270 271 pwm_c_c_pins: pwm-c-c { 272 mux { 273 groups = "pwm_c_c"; 274 function = "pwm_c"; 275 bias-disable; 276 }; 277 }; 278 279 pwm_c_x5_pins: pwm-c-x5 { 280 mux { 281 groups = "pwm_c_x5"; 282 function = "pwm_c"; 283 bias-disable; 284 }; 285 }; 286 287 pwm_c_x8_pins: pwm-c-x8 { 288 mux { 289 groups = "pwm_c_x8"; 290 function = "pwm_c"; 291 bias-disable; 292 }; 293 }; 294 295 pwm_d_x3_pins: pwm-d-x3 { 296 mux { 297 groups = "pwm_d_x3"; 298 function = "pwm_d"; 299 bias-disable; 300 }; 301 }; 302 303 pwm_d_x6_pins: pwm-d-x6 { 304 mux { 305 groups = "pwm_d_x6"; 306 function = "pwm_d"; 307 bias-disable; 308 }; 309 }; 310 311 pwm_e_pins: pwm-e { 312 mux { 313 groups = "pwm_e"; 314 function = "pwm_e"; 315 bias-disable; 316 }; 317 }; 318 319 pwm_f_x_pins: pwm-f-x { 320 mux { 321 groups = "pwm_f_x"; 322 function = "pwm_f"; 323 bias-disable; 324 }; 325 }; 326 327 pwm_f_h_pins: pwm-f-h { 328 mux { 329 groups = "pwm_f_h"; 330 function = "pwm_f"; 331 bias-disable; 332 }; 333 }; 334 335 sdcard_c_pins: sdcard_c { 336 mux-0 { 337 groups = "sdcard_d0_c", 338 "sdcard_d1_c", 339 "sdcard_d2_c", 340 "sdcard_d3_c", 341 "sdcard_cmd_c"; 342 function = "sdcard"; 343 bias-pull-up; 344 drive-strength-microamp = <4000>; 345 }; 346 347 mux-1 { 348 groups = "sdcard_clk_c"; 349 function = "sdcard"; 350 bias-disable; 351 drive-strength-microamp = <4000>; 352 }; 353 }; 354 355 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 356 mux { 357 groups = "GPIOC_4"; 358 function = "gpio_periphs"; 359 bias-pull-down; 360 drive-strength-microamp = <4000>; 361 }; 362 }; 363 364 sdcard_z_pins: sdcard_z { 365 mux-0 { 366 groups = "sdcard_d0_z", 367 "sdcard_d1_z", 368 "sdcard_d2_z", 369 "sdcard_d3_z", 370 "sdcard_cmd_z"; 371 function = "sdcard"; 372 bias-pull-up; 373 drive-strength-microamp = <4000>; 374 }; 375 376 mux-1 { 377 groups = "sdcard_clk_z"; 378 function = "sdcard"; 379 bias-disable; 380 drive-strength-microamp = <4000>; 381 }; 382 }; 383 384 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 385 mux { 386 groups = "GPIOZ_6"; 387 function = "gpio_periphs"; 388 bias-pull-down; 389 drive-strength-microamp = <4000>; 390 }; 391 }; 392 393 uart_a_pins: uart-a { 394 mux { 395 groups = "uart_a_tx", 396 "uart_a_rx"; 397 function = "uart_a"; 398 bias-disable; 399 }; 400 }; 401 402 uart_a_cts_rts_pins: uart-a-cts-rts { 403 mux { 404 groups = "uart_a_cts", 405 "uart_a_rts"; 406 function = "uart_a"; 407 bias-disable; 408 }; 409 }; 410 411 uart_b_pins: uart-b { 412 mux { 413 groups = "uart_b_tx", 414 "uart_b_rx"; 415 function = "uart_b"; 416 bias-disable; 417 }; 418 }; 419 420 uart_c_pins: uart-c { 421 mux { 422 groups = "uart_c_tx", 423 "uart_c_rx"; 424 function = "uart_c"; 425 bias-disable; 426 }; 427 }; 428 429 uart_c_cts_rts_pins: uart-c-cts-rts { 430 mux { 431 groups = "uart_c_cts", 432 "uart_c_rts"; 433 function = "uart_c"; 434 bias-disable; 435 }; 436 }; 437 }; 438 }; 439 440 usb2_phy0: phy@36000 { 441 compatible = "amlogic,g12a-usb2-phy"; 442 reg = <0x0 0x36000 0x0 0x2000>; 443 clocks = <&xtal>; 444 clock-names = "xtal"; 445 resets = <&reset RESET_USB_PHY20>; 446 reset-names = "phy"; 447 #phy-cells = <0>; 448 }; 449 450 dmc: bus@38000 { 451 compatible = "simple-bus"; 452 reg = <0x0 0x38000 0x0 0x400>; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 456 457 canvas: video-lut@48 { 458 compatible = "amlogic,canvas"; 459 reg = <0x0 0x48 0x0 0x14>; 460 }; 461 }; 462 463 usb2_phy1: phy@3a000 { 464 compatible = "amlogic,g12a-usb2-phy"; 465 reg = <0x0 0x3a000 0x0 0x2000>; 466 clocks = <&xtal>; 467 clock-names = "xtal"; 468 resets = <&reset RESET_USB_PHY21>; 469 reset-names = "phy"; 470 #phy-cells = <0>; 471 }; 472 473 hiu: bus@3c000 { 474 compatible = "simple-bus"; 475 reg = <0x0 0x3c000 0x0 0x1400>; 476 #address-cells = <2>; 477 #size-cells = <2>; 478 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 479 480 hhi: system-controller@0 { 481 compatible = "amlogic,meson-gx-hhi-sysctrl", 482 "simple-mfd", "syscon"; 483 reg = <0 0 0 0x400>; 484 485 clkc: clock-controller { 486 compatible = "amlogic,g12a-clkc"; 487 #clock-cells = <1>; 488 clocks = <&xtal>; 489 clock-names = "xtal"; 490 }; 491 }; 492 }; 493 494 usb3_pcie_phy: phy@46000 { 495 compatible = "amlogic,g12a-usb3-pcie-phy"; 496 reg = <0x0 0x46000 0x0 0x2000>; 497 clocks = <&clkc CLKID_PCIE_PLL>; 498 clock-names = "ref_clk"; 499 resets = <&reset RESET_PCIE_PHY>; 500 reset-names = "phy"; 501 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 502 assigned-clock-rates = <100000000>; 503 #phy-cells = <1>; 504 }; 505 }; 506 507 aobus: bus@ff800000 { 508 compatible = "simple-bus"; 509 reg = <0x0 0xff800000 0x0 0x100000>; 510 #address-cells = <2>; 511 #size-cells = <2>; 512 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 513 514 rti: sys-ctrl@0 { 515 compatible = "amlogic,meson-gx-ao-sysctrl", 516 "simple-mfd", "syscon"; 517 reg = <0x0 0x0 0x0 0x100>; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 521 522 clkc_AO: clock-controller { 523 compatible = "amlogic,meson-g12a-aoclkc"; 524 #clock-cells = <1>; 525 #reset-cells = <1>; 526 clocks = <&xtal>, <&clkc CLKID_CLK81>; 527 clock-names = "xtal", "mpeg-clk"; 528 }; 529 530 pwrc_vpu: power-controller-vpu { 531 compatible = "amlogic,meson-g12a-pwrc-vpu"; 532 #power-domain-cells = <0>; 533 amlogic,hhi-sysctrl = <&hhi>; 534 resets = <&reset RESET_VIU>, 535 <&reset RESET_VENC>, 536 <&reset RESET_VCBUS>, 537 <&reset RESET_BT656>, 538 <&reset RESET_RDMA>, 539 <&reset RESET_VENCI>, 540 <&reset RESET_VENCP>, 541 <&reset RESET_VDAC>, 542 <&reset RESET_VDI6>, 543 <&reset RESET_VENCL>, 544 <&reset RESET_VID_LOCK>; 545 clocks = <&clkc CLKID_VPU>, 546 <&clkc CLKID_VAPB>; 547 clock-names = "vpu", "vapb"; 548 /* 549 * VPU clocking is provided by two identical clock paths 550 * VPU_0 and VPU_1 muxed to a single clock by a glitch 551 * free mux to safely change frequency while running. 552 * Same for VAPB but with a final gate after the glitch free mux. 553 */ 554 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 555 <&clkc CLKID_VPU_0>, 556 <&clkc CLKID_VPU>, /* Glitch free mux */ 557 <&clkc CLKID_VAPB_0_SEL>, 558 <&clkc CLKID_VAPB_0>, 559 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 560 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 561 <0>, /* Do Nothing */ 562 <&clkc CLKID_VPU_0>, 563 <&clkc CLKID_FCLK_DIV4>, 564 <0>, /* Do Nothing */ 565 <&clkc CLKID_VAPB_0>; 566 assigned-clock-rates = <0>, /* Do Nothing */ 567 <666666666>, 568 <0>, /* Do Nothing */ 569 <0>, /* Do Nothing */ 570 <250000000>, 571 <0>; /* Do Nothing */ 572 }; 573 574 ao_pinctrl: pinctrl@14 { 575 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 576 #address-cells = <2>; 577 #size-cells = <2>; 578 ranges; 579 580 gpio_ao: bank@14 { 581 reg = <0x0 0x14 0x0 0x8>, 582 <0x0 0x1c 0x0 0x8>, 583 <0x0 0x24 0x0 0x14>; 584 reg-names = "mux", 585 "ds", 586 "gpio"; 587 gpio-controller; 588 #gpio-cells = <2>; 589 gpio-ranges = <&ao_pinctrl 0 0 15>; 590 }; 591 592 uart_ao_a_pins: uart-a-ao { 593 mux { 594 groups = "uart_ao_a_tx", 595 "uart_ao_a_rx"; 596 function = "uart_ao_a"; 597 bias-disable; 598 }; 599 }; 600 601 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 602 mux { 603 groups = "uart_ao_a_cts", 604 "uart_ao_a_rts"; 605 function = "uart_ao_a"; 606 bias-disable; 607 }; 608 }; 609 610 pwm_ao_a_pins: pwm-ao-a { 611 mux { 612 groups = "pwm_ao_a"; 613 function = "pwm_ao_a"; 614 bias-disable; 615 }; 616 }; 617 618 pwm_ao_b_pins: pwm-ao-b { 619 mux { 620 groups = "pwm_ao_b"; 621 function = "pwm_ao_b"; 622 bias-disable; 623 }; 624 }; 625 626 pwm_ao_c_4_pins: pwm-ao-c-4 { 627 mux { 628 groups = "pwm_ao_c_4"; 629 function = "pwm_ao_c"; 630 bias-disable; 631 }; 632 }; 633 634 pwm_ao_c_6_pins: pwm-ao-c-6 { 635 mux { 636 groups = "pwm_ao_c_6"; 637 function = "pwm_ao_c"; 638 bias-disable; 639 }; 640 }; 641 642 pwm_ao_d_5_pins: pwm-ao-d-5 { 643 mux { 644 groups = "pwm_ao_d_5"; 645 function = "pwm_ao_d"; 646 bias-disable; 647 }; 648 }; 649 650 pwm_ao_d_10_pins: pwm-ao-d-10 { 651 mux { 652 groups = "pwm_ao_d_10"; 653 function = "pwm_ao_d"; 654 bias-disable; 655 }; 656 }; 657 658 pwm_ao_d_e_pins: pwm-ao-d-e { 659 mux { 660 groups = "pwm_ao_d_e"; 661 function = "pwm_ao_d"; 662 }; 663 }; 664 665 remote_input_ao_pins: remote-input-ao { 666 mux { 667 groups = "remote_ao_input"; 668 function = "remote_ao_input"; 669 bias-disable; 670 }; 671 }; 672 }; 673 }; 674 675 cec_AO: cec@100 { 676 compatible = "amlogic,meson-gx-ao-cec"; 677 reg = <0x0 0x00100 0x0 0x14>; 678 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 679 clocks = <&clkc_AO CLKID_AO_CEC>; 680 clock-names = "core"; 681 status = "disabled"; 682 }; 683 684 sec_AO: ao-secure@140 { 685 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 686 reg = <0x0 0x140 0x0 0x140>; 687 amlogic,has-chip-id; 688 }; 689 690 cecb_AO: cec@280 { 691 compatible = "amlogic,meson-g12a-ao-cec"; 692 reg = <0x0 0x00280 0x0 0x1c>; 693 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 694 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 695 clock-names = "oscin"; 696 status = "disabled"; 697 }; 698 699 pwm_AO_cd: pwm@2000 { 700 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 701 reg = <0x0 0x2000 0x0 0x20>; 702 #pwm-cells = <3>; 703 status = "disabled"; 704 }; 705 706 uart_AO: serial@3000 { 707 compatible = "amlogic,meson-gx-uart", 708 "amlogic,meson-ao-uart"; 709 reg = <0x0 0x3000 0x0 0x18>; 710 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 711 clocks = <&xtal>, <&xtal>, <&xtal>; 712 clock-names = "xtal", "pclk", "baud"; 713 status = "disabled"; 714 }; 715 716 uart_AO_B: serial@4000 { 717 compatible = "amlogic,meson-gx-uart", 718 "amlogic,meson-ao-uart"; 719 reg = <0x0 0x4000 0x0 0x18>; 720 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 721 clocks = <&xtal>, <&xtal>, <&xtal>; 722 clock-names = "xtal", "pclk", "baud"; 723 status = "disabled"; 724 }; 725 726 pwm_AO_ab: pwm@7000 { 727 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 728 reg = <0x0 0x7000 0x0 0x20>; 729 #pwm-cells = <3>; 730 status = "disabled"; 731 }; 732 733 ir: ir@8000 { 734 compatible = "amlogic,meson-gxbb-ir"; 735 reg = <0x0 0x8000 0x0 0x20>; 736 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 737 status = "disabled"; 738 }; 739 740 saradc: adc@9000 { 741 compatible = "amlogic,meson-g12a-saradc", 742 "amlogic,meson-saradc"; 743 reg = <0x0 0x9000 0x0 0x48>; 744 #io-channel-cells = <1>; 745 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 746 clocks = <&xtal>, 747 <&clkc_AO CLKID_AO_SAR_ADC>, 748 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 749 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 750 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 751 status = "disabled"; 752 }; 753 }; 754 755 vpu: vpu@ff900000 { 756 compatible = "amlogic,meson-g12a-vpu"; 757 reg = <0x0 0xff900000 0x0 0x100000>, 758 <0x0 0xff63c000 0x0 0x1000>; 759 reg-names = "vpu", "hhi"; 760 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 amlogic,canvas = <&canvas>; 764 power-domains = <&pwrc_vpu>; 765 766 /* CVBS VDAC output port */ 767 cvbs_vdac_port: port@0 { 768 reg = <0>; 769 }; 770 771 /* HDMI-TX output port */ 772 hdmi_tx_port: port@1 { 773 reg = <1>; 774 775 hdmi_tx_out: endpoint { 776 remote-endpoint = <&hdmi_tx_in>; 777 }; 778 }; 779 }; 780 781 gic: interrupt-controller@ffc01000 { 782 compatible = "arm,gic-400"; 783 reg = <0x0 0xffc01000 0 0x1000>, 784 <0x0 0xffc02000 0 0x2000>, 785 <0x0 0xffc04000 0 0x2000>, 786 <0x0 0xffc06000 0 0x2000>; 787 interrupt-controller; 788 interrupts = <GIC_PPI 9 789 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 790 #interrupt-cells = <3>; 791 #address-cells = <0>; 792 }; 793 794 cbus: bus@ffd00000 { 795 compatible = "simple-bus"; 796 reg = <0x0 0xffd00000 0x0 0x100000>; 797 #address-cells = <2>; 798 #size-cells = <2>; 799 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 800 801 reset: reset-controller@1004 { 802 compatible = "amlogic,meson-g12a-reset", 803 "amlogic,meson-axg-reset"; 804 reg = <0x0 0x1004 0x0 0x9c>; 805 #reset-cells = <1>; 806 }; 807 808 pwm_ef: pwm@19000 { 809 compatible = "amlogic,meson-g12a-ee-pwm"; 810 reg = <0x0 0x19000 0x0 0x20>; 811 #pwm-cells = <3>; 812 status = "disabled"; 813 }; 814 815 pwm_cd: pwm@1a000 { 816 compatible = "amlogic,meson-g12a-ee-pwm"; 817 reg = <0x0 0x1a000 0x0 0x20>; 818 #pwm-cells = <3>; 819 status = "disabled"; 820 }; 821 822 pwm_ab: pwm@1b000 { 823 compatible = "amlogic,meson-g12a-ee-pwm"; 824 reg = <0x0 0x1b000 0x0 0x20>; 825 #pwm-cells = <3>; 826 status = "disabled"; 827 }; 828 829 clk_msr: clock-measure@18000 { 830 compatible = "amlogic,meson-g12a-clk-measure"; 831 reg = <0x0 0x18000 0x0 0x10>; 832 }; 833 834 uart_C: serial@22000 { 835 compatible = "amlogic,meson-gx-uart"; 836 reg = <0x0 0x22000 0x0 0x18>; 837 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 838 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 839 clock-names = "xtal", "pclk", "baud"; 840 status = "disabled"; 841 }; 842 843 uart_B: serial@23000 { 844 compatible = "amlogic,meson-gx-uart"; 845 reg = <0x0 0x23000 0x0 0x18>; 846 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 847 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 848 clock-names = "xtal", "pclk", "baud"; 849 status = "disabled"; 850 }; 851 852 uart_A: serial@24000 { 853 compatible = "amlogic,meson-gx-uart"; 854 reg = <0x0 0x24000 0x0 0x18>; 855 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 856 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 857 clock-names = "xtal", "pclk", "baud"; 858 status = "disabled"; 859 }; 860 }; 861 862 sd_emmc_b: sd@ffe05000 { 863 compatible = "amlogic,meson-axg-mmc"; 864 reg = <0x0 0xffe05000 0x0 0x800>; 865 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 866 status = "disabled"; 867 clocks = <&clkc CLKID_SD_EMMC_B>, 868 <&clkc CLKID_SD_EMMC_B_CLK0>, 869 <&clkc CLKID_FCLK_DIV2>; 870 clock-names = "core", "clkin0", "clkin1"; 871 resets = <&reset RESET_SD_EMMC_B>; 872 }; 873 874 sd_emmc_c: mmc@ffe07000 { 875 compatible = "amlogic,meson-axg-mmc"; 876 reg = <0x0 0xffe07000 0x0 0x800>; 877 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 878 status = "disabled"; 879 clocks = <&clkc CLKID_SD_EMMC_C>, 880 <&clkc CLKID_SD_EMMC_C_CLK0>, 881 <&clkc CLKID_FCLK_DIV2>; 882 clock-names = "core", "clkin0", "clkin1"; 883 resets = <&reset RESET_SD_EMMC_C>; 884 }; 885 886 usb: usb@ffe09000 { 887 status = "disabled"; 888 compatible = "amlogic,meson-g12a-usb-ctrl"; 889 reg = <0x0 0xffe09000 0x0 0xa0>; 890 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <2>; 892 #size-cells = <2>; 893 ranges; 894 895 clocks = <&clkc CLKID_USB>; 896 resets = <&reset RESET_USB>; 897 898 dr_mode = "otg"; 899 900 phys = <&usb2_phy0>, <&usb2_phy1>, 901 <&usb3_pcie_phy PHY_TYPE_USB3>; 902 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 903 904 dwc2: usb@ff400000 { 905 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 906 reg = <0x0 0xff400000 0x0 0x40000>; 907 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 909 clock-names = "ddr"; 910 phys = <&usb2_phy1>; 911 dr_mode = "peripheral"; 912 g-rx-fifo-size = <192>; 913 g-np-tx-fifo-size = <128>; 914 g-tx-fifo-size = <128 128 16 16 16>; 915 }; 916 917 dwc3: usb@ff500000 { 918 compatible = "snps,dwc3"; 919 reg = <0x0 0xff500000 0x0 0x100000>; 920 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 921 dr_mode = "host"; 922 snps,dis_u2_susphy_quirk; 923 snps,quirk-frame-length-adjustment; 924 }; 925 }; 926 927 mali: gpu@ffe40000 { 928 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 929 reg = <0x0 0xffe40000 0x0 0x40000>; 930 interrupt-parent = <&gic>; 931 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "gpu", "mmu", "job"; 935 clocks = <&clkc CLKID_MALI>; 936 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 937 938 /* 939 * Mali clocking is provided by two identical clock paths 940 * MALI_0 and MALI_1 muxed to a single clock by a glitch 941 * free mux to safely change frequency while running. 942 */ 943 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 944 <&clkc CLKID_MALI_0>, 945 <&clkc CLKID_MALI>; /* Glitch free mux */ 946 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 947 <0>, /* Do Nothing */ 948 <&clkc CLKID_MALI_0>; 949 assigned-clock-rates = <0>, /* Do Nothing */ 950 <800000000>, 951 <0>; /* Do Nothing */ 952 }; 953 }; 954 955 timer { 956 compatible = "arm,armv8-timer"; 957 interrupts = <GIC_PPI 13 958 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 959 <GIC_PPI 14 960 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 961 <GIC_PPI 11 962 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 963 <GIC_PPI 10 964 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 965 }; 966 967 xtal: xtal-clk { 968 compatible = "fixed-clock"; 969 clock-frequency = <24000000>; 970 clock-output-names = "xtal"; 971 #clock-cells = <0>; 972 }; 973 974}; 975