1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 14/ { 15 compatible = "amlogic,g12a"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <0x2>; 23 #size-cells = <0x0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0 0x1>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x2>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x3>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 l2: l2-cache0 { 58 compatible = "cache"; 59 }; 60 }; 61 62 efuse: efuse { 63 compatible = "amlogic,meson-gxbb-efuse"; 64 clocks = <&clkc CLKID_EFUSE>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 read-only; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 81 secmon_reserved: secmon@5000000 { 82 reg = <0x0 0x05000000 0x0 0x300000>; 83 no-map; 84 }; 85 86 linux,cma { 87 compatible = "shared-dma-pool"; 88 reusable; 89 size = <0x0 0x10000000>; 90 alignment = <0x0 0x400000>; 91 linux,cma-default; 92 }; 93 }; 94 95 sm: secure-monitor { 96 compatible = "amlogic,meson-gxbb-sm"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 apb: bus@ff600000 { 106 compatible = "simple-bus"; 107 reg = <0x0 0xff600000 0x0 0x200000>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111 112 hdmi_tx: hdmi-tx@0 { 113 compatible = "amlogic,meson-g12a-dw-hdmi"; 114 reg = <0x0 0x0 0x0 0x10000>; 115 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 116 resets = <&reset RESET_HDMITX_CAPB3>, 117 <&reset RESET_HDMITX_PHY>, 118 <&reset RESET_HDMITX>; 119 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 120 clocks = <&clkc CLKID_HDMI>, 121 <&clkc CLKID_HTX_PCLK>, 122 <&clkc CLKID_VPU_INTR>; 123 clock-names = "isfr", "iahb", "venci"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* VPU VENC Input */ 129 hdmi_tx_venc_port: port@0 { 130 reg = <0>; 131 132 hdmi_tx_in: endpoint { 133 remote-endpoint = <&hdmi_tx_out>; 134 }; 135 }; 136 137 /* TMDS Output */ 138 hdmi_tx_tmds_port: port@1 { 139 reg = <1>; 140 }; 141 }; 142 143 periphs: bus@34400 { 144 compatible = "simple-bus"; 145 reg = <0x0 0x34400 0x0 0x400>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 149 150 periphs_pinctrl: pinctrl@40 { 151 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 gpio: bank@40 { 157 reg = <0x0 0x40 0x0 0x4c>, 158 <0x0 0xe8 0x0 0x18>, 159 <0x0 0x120 0x0 0x18>, 160 <0x0 0x2c0 0x0 0x40>, 161 <0x0 0x340 0x0 0x1c>; 162 reg-names = "gpio", 163 "pull", 164 "pull-enable", 165 "mux", 166 "ds"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 0 86>; 170 }; 171 172 cec_ao_a_h_pins: cec_ao_a_h { 173 mux { 174 groups = "cec_ao_a_h"; 175 function = "cec_ao_a_h"; 176 bias-disable; 177 }; 178 }; 179 180 cec_ao_b_h_pins: cec_ao_b_h { 181 mux { 182 groups = "cec_ao_b_h"; 183 function = "cec_ao_b_h"; 184 bias-disable; 185 }; 186 }; 187 188 emmc_pins: emmc { 189 mux-0 { 190 groups = "emmc_nand_d0", 191 "emmc_nand_d1", 192 "emmc_nand_d2", 193 "emmc_nand_d3", 194 "emmc_nand_d4", 195 "emmc_nand_d5", 196 "emmc_nand_d6", 197 "emmc_nand_d7", 198 "emmc_cmd"; 199 function = "emmc"; 200 bias-pull-up; 201 drive-strength-microamp = <4000>; 202 }; 203 204 mux-1 { 205 groups = "emmc_clk"; 206 function = "emmc"; 207 bias-disable; 208 drive-strength-microamp = <4000>; 209 }; 210 }; 211 212 emmc_ds_pins: emmc-ds { 213 mux { 214 groups = "emmc_nand_ds"; 215 function = "emmc"; 216 bias-pull-down; 217 drive-strength-microamp = <4000>; 218 }; 219 }; 220 221 emmc_clk_gate_pins: emmc_clk_gate { 222 mux { 223 groups = "BOOT_8"; 224 function = "gpio_periphs"; 225 bias-pull-down; 226 drive-strength-microamp = <4000>; 227 }; 228 }; 229 230 hdmitx_ddc_pins: hdmitx_ddc { 231 mux { 232 groups = "hdmitx_sda", 233 "hdmitx_sck"; 234 function = "hdmitx"; 235 bias-disable; 236 }; 237 }; 238 239 hdmitx_hpd_pins: hdmitx_hpd { 240 mux { 241 groups = "hdmitx_hpd_in"; 242 function = "hdmitx"; 243 bias-disable; 244 }; 245 }; 246 247 248 i2c0_sda_c_pins: i2c0-sda-c { 249 mux { 250 groups = "i2c0_sda_c"; 251 function = "i2c0"; 252 bias-disable; 253 drive-strength-microamp = <3000>; 254 255 }; 256 }; 257 258 i2c0_sck_c_pins: i2c0-sck-c { 259 mux { 260 groups = "i2c0_sck_c"; 261 function = "i2c0"; 262 bias-disable; 263 drive-strength-microamp = <3000>; 264 }; 265 }; 266 267 i2c0_sda_z0_pins: i2c0-sda-z0 { 268 mux { 269 groups = "i2c0_sda_z0"; 270 function = "i2c0"; 271 bias-disable; 272 drive-strength-microamp = <3000>; 273 }; 274 }; 275 276 i2c0_sck_z1_pins: i2c0-sck-z1 { 277 mux { 278 groups = "i2c0_sck_z1"; 279 function = "i2c0"; 280 bias-disable; 281 drive-strength-microamp = <3000>; 282 }; 283 }; 284 285 i2c0_sda_z7_pins: i2c0-sda-z7 { 286 mux { 287 groups = "i2c0_sda_z7"; 288 function = "i2c0"; 289 bias-disable; 290 drive-strength-microamp = <3000>; 291 }; 292 }; 293 294 i2c0_sda_z8_pins: i2c0-sda-z8 { 295 mux { 296 groups = "i2c0_sda_z8"; 297 function = "i2c0"; 298 bias-disable; 299 drive-strength-microamp = <3000>; 300 }; 301 }; 302 303 i2c1_sda_x_pins: i2c1-sda-x { 304 mux { 305 groups = "i2c1_sda_x"; 306 function = "i2c1"; 307 bias-disable; 308 drive-strength-microamp = <3000>; 309 }; 310 }; 311 312 i2c1_sck_x_pins: i2c1-sck-x { 313 mux { 314 groups = "i2c1_sck_x"; 315 function = "i2c1"; 316 bias-disable; 317 drive-strength-microamp = <3000>; 318 }; 319 }; 320 321 i2c1_sda_h2_pins: i2c1-sda-h2 { 322 mux { 323 groups = "i2c1_sda_h2"; 324 function = "i2c1"; 325 bias-disable; 326 drive-strength-microamp = <3000>; 327 }; 328 }; 329 330 i2c1_sck_h3_pins: i2c1-sck-h3 { 331 mux { 332 groups = "i2c1_sck_h3"; 333 function = "i2c1"; 334 bias-disable; 335 drive-strength-microamp = <3000>; 336 }; 337 }; 338 339 i2c1_sda_h6_pins: i2c1-sda-h6 { 340 mux { 341 groups = "i2c1_sda_h6"; 342 function = "i2c1"; 343 bias-disable; 344 drive-strength-microamp = <3000>; 345 }; 346 }; 347 348 i2c1_sck_h7_pins: i2c1-sck-h7 { 349 mux { 350 groups = "i2c1_sck_h7"; 351 function = "i2c1"; 352 bias-disable; 353 drive-strength-microamp = <3000>; 354 }; 355 }; 356 357 i2c2_sda_x_pins: i2c2-sda-x { 358 mux { 359 groups = "i2c2_sda_x"; 360 function = "i2c2"; 361 bias-disable; 362 drive-strength-microamp = <3000>; 363 }; 364 }; 365 366 i2c2_sck_x_pins: i2c2-sck-x { 367 mux { 368 groups = "i2c2_sck_x"; 369 function = "i2c2"; 370 bias-disable; 371 drive-strength-microamp = <3000>; 372 }; 373 }; 374 375 i2c2_sda_z_pins: i2c2-sda-z { 376 mux { 377 groups = "i2c2_sda_z"; 378 function = "i2c2"; 379 bias-disable; 380 drive-strength-microamp = <3000>; 381 }; 382 }; 383 384 i2c2_sck_z_pins: i2c2-sck-z { 385 mux { 386 groups = "i2c2_sck_z"; 387 function = "i2c2"; 388 bias-disable; 389 drive-strength-microamp = <3000>; 390 }; 391 }; 392 393 i2c3_sda_h_pins: i2c3-sda-h { 394 mux { 395 groups = "i2c3_sda_h"; 396 function = "i2c3"; 397 bias-disable; 398 drive-strength-microamp = <3000>; 399 }; 400 }; 401 402 i2c3_sck_h_pins: i2c3-sck-h { 403 mux { 404 groups = "i2c3_sck_h"; 405 function = "i2c3"; 406 bias-disable; 407 drive-strength-microamp = <3000>; 408 }; 409 }; 410 411 i2c3_sda_a_pins: i2c3-sda-a { 412 mux { 413 groups = "i2c3_sda_a"; 414 function = "i2c3"; 415 bias-disable; 416 drive-strength-microamp = <3000>; 417 }; 418 }; 419 420 i2c3_sck_a_pins: i2c3-sck-a { 421 mux { 422 groups = "i2c3_sck_a"; 423 function = "i2c3"; 424 bias-disable; 425 drive-strength-microamp = <3000>; 426 }; 427 }; 428 429 pwm_a_pins: pwm-a { 430 mux { 431 groups = "pwm_a"; 432 function = "pwm_a"; 433 bias-disable; 434 }; 435 }; 436 437 pwm_b_x7_pins: pwm-b-x7 { 438 mux { 439 groups = "pwm_b_x7"; 440 function = "pwm_b"; 441 bias-disable; 442 }; 443 }; 444 445 pwm_b_x19_pins: pwm-b-x19 { 446 mux { 447 groups = "pwm_b_x19"; 448 function = "pwm_b"; 449 bias-disable; 450 }; 451 }; 452 453 pwm_c_c_pins: pwm-c-c { 454 mux { 455 groups = "pwm_c_c"; 456 function = "pwm_c"; 457 bias-disable; 458 }; 459 }; 460 461 pwm_c_x5_pins: pwm-c-x5 { 462 mux { 463 groups = "pwm_c_x5"; 464 function = "pwm_c"; 465 bias-disable; 466 }; 467 }; 468 469 pwm_c_x8_pins: pwm-c-x8 { 470 mux { 471 groups = "pwm_c_x8"; 472 function = "pwm_c"; 473 bias-disable; 474 }; 475 }; 476 477 pwm_d_x3_pins: pwm-d-x3 { 478 mux { 479 groups = "pwm_d_x3"; 480 function = "pwm_d"; 481 bias-disable; 482 }; 483 }; 484 485 pwm_d_x6_pins: pwm-d-x6 { 486 mux { 487 groups = "pwm_d_x6"; 488 function = "pwm_d"; 489 bias-disable; 490 }; 491 }; 492 493 pwm_e_pins: pwm-e { 494 mux { 495 groups = "pwm_e"; 496 function = "pwm_e"; 497 bias-disable; 498 }; 499 }; 500 501 pwm_f_x_pins: pwm-f-x { 502 mux { 503 groups = "pwm_f_x"; 504 function = "pwm_f"; 505 bias-disable; 506 }; 507 }; 508 509 pwm_f_h_pins: pwm-f-h { 510 mux { 511 groups = "pwm_f_h"; 512 function = "pwm_f"; 513 bias-disable; 514 }; 515 }; 516 517 sdcard_c_pins: sdcard_c { 518 mux-0 { 519 groups = "sdcard_d0_c", 520 "sdcard_d1_c", 521 "sdcard_d2_c", 522 "sdcard_d3_c", 523 "sdcard_cmd_c"; 524 function = "sdcard"; 525 bias-pull-up; 526 drive-strength-microamp = <4000>; 527 }; 528 529 mux-1 { 530 groups = "sdcard_clk_c"; 531 function = "sdcard"; 532 bias-disable; 533 drive-strength-microamp = <4000>; 534 }; 535 }; 536 537 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 538 mux { 539 groups = "GPIOC_4"; 540 function = "gpio_periphs"; 541 bias-pull-down; 542 drive-strength-microamp = <4000>; 543 }; 544 }; 545 546 sdcard_z_pins: sdcard_z { 547 mux-0 { 548 groups = "sdcard_d0_z", 549 "sdcard_d1_z", 550 "sdcard_d2_z", 551 "sdcard_d3_z", 552 "sdcard_cmd_z"; 553 function = "sdcard"; 554 bias-pull-up; 555 drive-strength-microamp = <4000>; 556 }; 557 558 mux-1 { 559 groups = "sdcard_clk_z"; 560 function = "sdcard"; 561 bias-disable; 562 drive-strength-microamp = <4000>; 563 }; 564 }; 565 566 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 567 mux { 568 groups = "GPIOZ_6"; 569 function = "gpio_periphs"; 570 bias-pull-down; 571 drive-strength-microamp = <4000>; 572 }; 573 }; 574 575 uart_a_pins: uart-a { 576 mux { 577 groups = "uart_a_tx", 578 "uart_a_rx"; 579 function = "uart_a"; 580 bias-disable; 581 }; 582 }; 583 584 uart_a_cts_rts_pins: uart-a-cts-rts { 585 mux { 586 groups = "uart_a_cts", 587 "uart_a_rts"; 588 function = "uart_a"; 589 bias-disable; 590 }; 591 }; 592 593 uart_b_pins: uart-b { 594 mux { 595 groups = "uart_b_tx", 596 "uart_b_rx"; 597 function = "uart_b"; 598 bias-disable; 599 }; 600 }; 601 602 uart_c_pins: uart-c { 603 mux { 604 groups = "uart_c_tx", 605 "uart_c_rx"; 606 function = "uart_c"; 607 bias-disable; 608 }; 609 }; 610 611 uart_c_cts_rts_pins: uart-c-cts-rts { 612 mux { 613 groups = "uart_c_cts", 614 "uart_c_rts"; 615 function = "uart_c"; 616 bias-disable; 617 }; 618 }; 619 }; 620 }; 621 622 usb2_phy0: phy@36000 { 623 compatible = "amlogic,g12a-usb2-phy"; 624 reg = <0x0 0x36000 0x0 0x2000>; 625 clocks = <&xtal>; 626 clock-names = "xtal"; 627 resets = <&reset RESET_USB_PHY20>; 628 reset-names = "phy"; 629 #phy-cells = <0>; 630 }; 631 632 dmc: bus@38000 { 633 compatible = "simple-bus"; 634 reg = <0x0 0x38000 0x0 0x400>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 638 639 canvas: video-lut@48 { 640 compatible = "amlogic,canvas"; 641 reg = <0x0 0x48 0x0 0x14>; 642 }; 643 }; 644 645 usb2_phy1: phy@3a000 { 646 compatible = "amlogic,g12a-usb2-phy"; 647 reg = <0x0 0x3a000 0x0 0x2000>; 648 clocks = <&xtal>; 649 clock-names = "xtal"; 650 resets = <&reset RESET_USB_PHY21>; 651 reset-names = "phy"; 652 #phy-cells = <0>; 653 }; 654 655 hiu: bus@3c000 { 656 compatible = "simple-bus"; 657 reg = <0x0 0x3c000 0x0 0x1400>; 658 #address-cells = <2>; 659 #size-cells = <2>; 660 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 661 662 hhi: system-controller@0 { 663 compatible = "amlogic,meson-gx-hhi-sysctrl", 664 "simple-mfd", "syscon"; 665 reg = <0 0 0 0x400>; 666 667 clkc: clock-controller { 668 compatible = "amlogic,g12a-clkc"; 669 #clock-cells = <1>; 670 clocks = <&xtal>; 671 clock-names = "xtal"; 672 }; 673 }; 674 }; 675 676 audio: bus@42000 { 677 compatible = "simple-bus"; 678 reg = <0x0 0x42000 0x0 0x2000>; 679 #address-cells = <2>; 680 #size-cells = <2>; 681 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 682 683 clkc_audio: clock-controller@0 { 684 status = "disabled"; 685 compatible = "amlogic,g12a-audio-clkc"; 686 reg = <0x0 0x0 0x0 0xb4>; 687 #clock-cells = <1>; 688 689 clocks = <&clkc CLKID_AUDIO>, 690 <&clkc CLKID_MPLL0>, 691 <&clkc CLKID_MPLL1>, 692 <&clkc CLKID_MPLL2>, 693 <&clkc CLKID_MPLL3>, 694 <&clkc CLKID_HIFI_PLL>, 695 <&clkc CLKID_FCLK_DIV3>, 696 <&clkc CLKID_FCLK_DIV4>, 697 <&clkc CLKID_GP0_PLL>; 698 clock-names = "pclk", 699 "mst_in0", 700 "mst_in1", 701 "mst_in2", 702 "mst_in3", 703 "mst_in4", 704 "mst_in5", 705 "mst_in6", 706 "mst_in7"; 707 708 resets = <&reset RESET_AUDIO>; 709 }; 710 }; 711 712 usb3_pcie_phy: phy@46000 { 713 compatible = "amlogic,g12a-usb3-pcie-phy"; 714 reg = <0x0 0x46000 0x0 0x2000>; 715 clocks = <&clkc CLKID_PCIE_PLL>; 716 clock-names = "ref_clk"; 717 resets = <&reset RESET_PCIE_PHY>; 718 reset-names = "phy"; 719 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 720 assigned-clock-rates = <100000000>; 721 #phy-cells = <1>; 722 }; 723 }; 724 725 aobus: bus@ff800000 { 726 compatible = "simple-bus"; 727 reg = <0x0 0xff800000 0x0 0x100000>; 728 #address-cells = <2>; 729 #size-cells = <2>; 730 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 731 732 rti: sys-ctrl@0 { 733 compatible = "amlogic,meson-gx-ao-sysctrl", 734 "simple-mfd", "syscon"; 735 reg = <0x0 0x0 0x0 0x100>; 736 #address-cells = <2>; 737 #size-cells = <2>; 738 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 739 740 clkc_AO: clock-controller { 741 compatible = "amlogic,meson-g12a-aoclkc"; 742 #clock-cells = <1>; 743 #reset-cells = <1>; 744 clocks = <&xtal>, <&clkc CLKID_CLK81>; 745 clock-names = "xtal", "mpeg-clk"; 746 }; 747 748 pwrc_vpu: power-controller-vpu { 749 compatible = "amlogic,meson-g12a-pwrc-vpu"; 750 #power-domain-cells = <0>; 751 amlogic,hhi-sysctrl = <&hhi>; 752 resets = <&reset RESET_VIU>, 753 <&reset RESET_VENC>, 754 <&reset RESET_VCBUS>, 755 <&reset RESET_BT656>, 756 <&reset RESET_RDMA>, 757 <&reset RESET_VENCI>, 758 <&reset RESET_VENCP>, 759 <&reset RESET_VDAC>, 760 <&reset RESET_VDI6>, 761 <&reset RESET_VENCL>, 762 <&reset RESET_VID_LOCK>; 763 clocks = <&clkc CLKID_VPU>, 764 <&clkc CLKID_VAPB>; 765 clock-names = "vpu", "vapb"; 766 /* 767 * VPU clocking is provided by two identical clock paths 768 * VPU_0 and VPU_1 muxed to a single clock by a glitch 769 * free mux to safely change frequency while running. 770 * Same for VAPB but with a final gate after the glitch free mux. 771 */ 772 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 773 <&clkc CLKID_VPU_0>, 774 <&clkc CLKID_VPU>, /* Glitch free mux */ 775 <&clkc CLKID_VAPB_0_SEL>, 776 <&clkc CLKID_VAPB_0>, 777 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 778 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 779 <0>, /* Do Nothing */ 780 <&clkc CLKID_VPU_0>, 781 <&clkc CLKID_FCLK_DIV4>, 782 <0>, /* Do Nothing */ 783 <&clkc CLKID_VAPB_0>; 784 assigned-clock-rates = <0>, /* Do Nothing */ 785 <666666666>, 786 <0>, /* Do Nothing */ 787 <0>, /* Do Nothing */ 788 <250000000>, 789 <0>; /* Do Nothing */ 790 }; 791 792 ao_pinctrl: pinctrl@14 { 793 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 794 #address-cells = <2>; 795 #size-cells = <2>; 796 ranges; 797 798 gpio_ao: bank@14 { 799 reg = <0x0 0x14 0x0 0x8>, 800 <0x0 0x1c 0x0 0x8>, 801 <0x0 0x24 0x0 0x14>; 802 reg-names = "mux", 803 "ds", 804 "gpio"; 805 gpio-controller; 806 #gpio-cells = <2>; 807 gpio-ranges = <&ao_pinctrl 0 0 15>; 808 }; 809 810 i2c_ao_sck_pins: i2c_ao_sck_pins { 811 mux { 812 groups = "i2c_ao_sck"; 813 function = "i2c_ao"; 814 bias-disable; 815 drive-strength-microamp = <3000>; 816 }; 817 }; 818 819 i2c_ao_sda_pins: i2c_ao_sda { 820 mux { 821 groups = "i2c_ao_sda"; 822 function = "i2c_ao"; 823 bias-disable; 824 drive-strength-microamp = <3000>; 825 }; 826 }; 827 828 i2c_ao_sck_e_pins: i2c_ao_sck_e { 829 mux { 830 groups = "i2c_ao_sck_e"; 831 function = "i2c_ao"; 832 bias-disable; 833 drive-strength-microamp = <3000>; 834 }; 835 }; 836 837 i2c_ao_sda_e_pins: i2c_ao_sda_e { 838 mux { 839 groups = "i2c_ao_sda_e"; 840 function = "i2c_ao"; 841 bias-disable; 842 drive-strength-microamp = <3000>; 843 }; 844 }; 845 846 uart_ao_a_pins: uart-a-ao { 847 mux { 848 groups = "uart_ao_a_tx", 849 "uart_ao_a_rx"; 850 function = "uart_ao_a"; 851 bias-disable; 852 }; 853 }; 854 855 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 856 mux { 857 groups = "uart_ao_a_cts", 858 "uart_ao_a_rts"; 859 function = "uart_ao_a"; 860 bias-disable; 861 }; 862 }; 863 864 pwm_ao_a_pins: pwm-ao-a { 865 mux { 866 groups = "pwm_ao_a"; 867 function = "pwm_ao_a"; 868 bias-disable; 869 }; 870 }; 871 872 pwm_ao_b_pins: pwm-ao-b { 873 mux { 874 groups = "pwm_ao_b"; 875 function = "pwm_ao_b"; 876 bias-disable; 877 }; 878 }; 879 880 pwm_ao_c_4_pins: pwm-ao-c-4 { 881 mux { 882 groups = "pwm_ao_c_4"; 883 function = "pwm_ao_c"; 884 bias-disable; 885 }; 886 }; 887 888 pwm_ao_c_6_pins: pwm-ao-c-6 { 889 mux { 890 groups = "pwm_ao_c_6"; 891 function = "pwm_ao_c"; 892 bias-disable; 893 }; 894 }; 895 896 pwm_ao_d_5_pins: pwm-ao-d-5 { 897 mux { 898 groups = "pwm_ao_d_5"; 899 function = "pwm_ao_d"; 900 bias-disable; 901 }; 902 }; 903 904 pwm_ao_d_10_pins: pwm-ao-d-10 { 905 mux { 906 groups = "pwm_ao_d_10"; 907 function = "pwm_ao_d"; 908 bias-disable; 909 }; 910 }; 911 912 pwm_ao_d_e_pins: pwm-ao-d-e { 913 mux { 914 groups = "pwm_ao_d_e"; 915 function = "pwm_ao_d"; 916 }; 917 }; 918 919 remote_input_ao_pins: remote-input-ao { 920 mux { 921 groups = "remote_ao_input"; 922 function = "remote_ao_input"; 923 bias-disable; 924 }; 925 }; 926 }; 927 }; 928 929 cec_AO: cec@100 { 930 compatible = "amlogic,meson-gx-ao-cec"; 931 reg = <0x0 0x00100 0x0 0x14>; 932 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 933 clocks = <&clkc_AO CLKID_AO_CEC>; 934 clock-names = "core"; 935 status = "disabled"; 936 }; 937 938 sec_AO: ao-secure@140 { 939 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 940 reg = <0x0 0x140 0x0 0x140>; 941 amlogic,has-chip-id; 942 }; 943 944 cecb_AO: cec@280 { 945 compatible = "amlogic,meson-g12a-ao-cec"; 946 reg = <0x0 0x00280 0x0 0x1c>; 947 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 948 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 949 clock-names = "oscin"; 950 status = "disabled"; 951 }; 952 953 pwm_AO_cd: pwm@2000 { 954 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 955 reg = <0x0 0x2000 0x0 0x20>; 956 #pwm-cells = <3>; 957 status = "disabled"; 958 }; 959 960 uart_AO: serial@3000 { 961 compatible = "amlogic,meson-gx-uart", 962 "amlogic,meson-ao-uart"; 963 reg = <0x0 0x3000 0x0 0x18>; 964 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 965 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 966 clock-names = "xtal", "pclk", "baud"; 967 status = "disabled"; 968 }; 969 970 uart_AO_B: serial@4000 { 971 compatible = "amlogic,meson-gx-uart", 972 "amlogic,meson-ao-uart"; 973 reg = <0x0 0x4000 0x0 0x18>; 974 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 975 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 976 clock-names = "xtal", "pclk", "baud"; 977 status = "disabled"; 978 }; 979 980 i2c_AO: i2c@5000 { 981 compatible = "amlogic,meson-axg-i2c"; 982 status = "disabled"; 983 reg = <0x0 0x05000 0x0 0x20>; 984 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 clocks = <&clkc CLKID_I2C>; 988 }; 989 990 pwm_AO_ab: pwm@7000 { 991 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 992 reg = <0x0 0x7000 0x0 0x20>; 993 #pwm-cells = <3>; 994 status = "disabled"; 995 }; 996 997 ir: ir@8000 { 998 compatible = "amlogic,meson-gxbb-ir"; 999 reg = <0x0 0x8000 0x0 0x20>; 1000 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1001 status = "disabled"; 1002 }; 1003 1004 saradc: adc@9000 { 1005 compatible = "amlogic,meson-g12a-saradc", 1006 "amlogic,meson-saradc"; 1007 reg = <0x0 0x9000 0x0 0x48>; 1008 #io-channel-cells = <1>; 1009 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 1010 clocks = <&xtal>, 1011 <&clkc_AO CLKID_AO_SAR_ADC>, 1012 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1013 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1014 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1015 status = "disabled"; 1016 }; 1017 }; 1018 1019 vpu: vpu@ff900000 { 1020 compatible = "amlogic,meson-g12a-vpu"; 1021 reg = <0x0 0xff900000 0x0 0x100000>, 1022 <0x0 0xff63c000 0x0 0x1000>; 1023 reg-names = "vpu", "hhi"; 1024 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 amlogic,canvas = <&canvas>; 1028 power-domains = <&pwrc_vpu>; 1029 1030 /* CVBS VDAC output port */ 1031 cvbs_vdac_port: port@0 { 1032 reg = <0>; 1033 }; 1034 1035 /* HDMI-TX output port */ 1036 hdmi_tx_port: port@1 { 1037 reg = <1>; 1038 1039 hdmi_tx_out: endpoint { 1040 remote-endpoint = <&hdmi_tx_in>; 1041 }; 1042 }; 1043 }; 1044 1045 gic: interrupt-controller@ffc01000 { 1046 compatible = "arm,gic-400"; 1047 reg = <0x0 0xffc01000 0 0x1000>, 1048 <0x0 0xffc02000 0 0x2000>, 1049 <0x0 0xffc04000 0 0x2000>, 1050 <0x0 0xffc06000 0 0x2000>; 1051 interrupt-controller; 1052 interrupts = <GIC_PPI 9 1053 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1054 #interrupt-cells = <3>; 1055 #address-cells = <0>; 1056 }; 1057 1058 cbus: bus@ffd00000 { 1059 compatible = "simple-bus"; 1060 reg = <0x0 0xffd00000 0x0 0x100000>; 1061 #address-cells = <2>; 1062 #size-cells = <2>; 1063 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 1064 1065 reset: reset-controller@1004 { 1066 compatible = "amlogic,meson-g12a-reset", 1067 "amlogic,meson-axg-reset"; 1068 reg = <0x0 0x1004 0x0 0x9c>; 1069 #reset-cells = <1>; 1070 }; 1071 1072 pwm_ef: pwm@19000 { 1073 compatible = "amlogic,meson-g12a-ee-pwm"; 1074 reg = <0x0 0x19000 0x0 0x20>; 1075 #pwm-cells = <3>; 1076 status = "disabled"; 1077 }; 1078 1079 pwm_cd: pwm@1a000 { 1080 compatible = "amlogic,meson-g12a-ee-pwm"; 1081 reg = <0x0 0x1a000 0x0 0x20>; 1082 #pwm-cells = <3>; 1083 status = "disabled"; 1084 }; 1085 1086 pwm_ab: pwm@1b000 { 1087 compatible = "amlogic,meson-g12a-ee-pwm"; 1088 reg = <0x0 0x1b000 0x0 0x20>; 1089 #pwm-cells = <3>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c3: i2c@1c000 { 1094 compatible = "amlogic,meson-axg-i2c"; 1095 status = "disabled"; 1096 reg = <0x0 0x1c000 0x0 0x20>; 1097 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 clocks = <&clkc CLKID_I2C>; 1101 }; 1102 1103 i2c2: i2c@1d000 { 1104 compatible = "amlogic,meson-axg-i2c"; 1105 status = "disabled"; 1106 reg = <0x0 0x1d000 0x0 0x20>; 1107 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 clocks = <&clkc CLKID_I2C>; 1111 }; 1112 1113 i2c1: i2c@1e000 { 1114 compatible = "amlogic,meson-axg-i2c"; 1115 status = "disabled"; 1116 reg = <0x0 0x1e000 0x0 0x20>; 1117 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 clocks = <&clkc CLKID_I2C>; 1121 }; 1122 1123 i2c0: i2c@1f000 { 1124 compatible = "amlogic,meson-axg-i2c"; 1125 status = "disabled"; 1126 reg = <0x0 0x1f000 0x0 0x20>; 1127 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 clocks = <&clkc CLKID_I2C>; 1131 }; 1132 1133 clk_msr: clock-measure@18000 { 1134 compatible = "amlogic,meson-g12a-clk-measure"; 1135 reg = <0x0 0x18000 0x0 0x10>; 1136 }; 1137 1138 uart_C: serial@22000 { 1139 compatible = "amlogic,meson-gx-uart"; 1140 reg = <0x0 0x22000 0x0 0x18>; 1141 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 1142 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 1143 clock-names = "xtal", "pclk", "baud"; 1144 status = "disabled"; 1145 }; 1146 1147 uart_B: serial@23000 { 1148 compatible = "amlogic,meson-gx-uart"; 1149 reg = <0x0 0x23000 0x0 0x18>; 1150 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1151 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1152 clock-names = "xtal", "pclk", "baud"; 1153 status = "disabled"; 1154 }; 1155 1156 uart_A: serial@24000 { 1157 compatible = "amlogic,meson-gx-uart"; 1158 reg = <0x0 0x24000 0x0 0x18>; 1159 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1160 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1161 clock-names = "xtal", "pclk", "baud"; 1162 status = "disabled"; 1163 }; 1164 }; 1165 1166 sd_emmc_b: sd@ffe05000 { 1167 compatible = "amlogic,meson-axg-mmc"; 1168 reg = <0x0 0xffe05000 0x0 0x800>; 1169 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 1170 status = "disabled"; 1171 clocks = <&clkc CLKID_SD_EMMC_B>, 1172 <&clkc CLKID_SD_EMMC_B_CLK0>, 1173 <&clkc CLKID_FCLK_DIV2>; 1174 clock-names = "core", "clkin0", "clkin1"; 1175 resets = <&reset RESET_SD_EMMC_B>; 1176 }; 1177 1178 sd_emmc_c: mmc@ffe07000 { 1179 compatible = "amlogic,meson-axg-mmc"; 1180 reg = <0x0 0xffe07000 0x0 0x800>; 1181 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 1182 status = "disabled"; 1183 clocks = <&clkc CLKID_SD_EMMC_C>, 1184 <&clkc CLKID_SD_EMMC_C_CLK0>, 1185 <&clkc CLKID_FCLK_DIV2>; 1186 clock-names = "core", "clkin0", "clkin1"; 1187 resets = <&reset RESET_SD_EMMC_C>; 1188 }; 1189 1190 usb: usb@ffe09000 { 1191 status = "disabled"; 1192 compatible = "amlogic,meson-g12a-usb-ctrl"; 1193 reg = <0x0 0xffe09000 0x0 0xa0>; 1194 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <2>; 1196 #size-cells = <2>; 1197 ranges; 1198 1199 clocks = <&clkc CLKID_USB>; 1200 resets = <&reset RESET_USB>; 1201 1202 dr_mode = "otg"; 1203 1204 phys = <&usb2_phy0>, <&usb2_phy1>, 1205 <&usb3_pcie_phy PHY_TYPE_USB3>; 1206 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 1207 1208 dwc2: usb@ff400000 { 1209 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 1210 reg = <0x0 0xff400000 0x0 0x40000>; 1211 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 1213 clock-names = "ddr"; 1214 phys = <&usb2_phy1>; 1215 dr_mode = "peripheral"; 1216 g-rx-fifo-size = <192>; 1217 g-np-tx-fifo-size = <128>; 1218 g-tx-fifo-size = <128 128 16 16 16>; 1219 }; 1220 1221 dwc3: usb@ff500000 { 1222 compatible = "snps,dwc3"; 1223 reg = <0x0 0xff500000 0x0 0x100000>; 1224 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1225 dr_mode = "host"; 1226 snps,dis_u2_susphy_quirk; 1227 snps,quirk-frame-length-adjustment; 1228 }; 1229 }; 1230 1231 mali: gpu@ffe40000 { 1232 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 1233 reg = <0x0 0xffe40000 0x0 0x40000>; 1234 interrupt-parent = <&gic>; 1235 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1238 interrupt-names = "gpu", "mmu", "job"; 1239 clocks = <&clkc CLKID_MALI>; 1240 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 1241 1242 /* 1243 * Mali clocking is provided by two identical clock paths 1244 * MALI_0 and MALI_1 muxed to a single clock by a glitch 1245 * free mux to safely change frequency while running. 1246 */ 1247 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 1248 <&clkc CLKID_MALI_0>, 1249 <&clkc CLKID_MALI>; /* Glitch free mux */ 1250 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 1251 <0>, /* Do Nothing */ 1252 <&clkc CLKID_MALI_0>; 1253 assigned-clock-rates = <0>, /* Do Nothing */ 1254 <800000000>, 1255 <0>; /* Do Nothing */ 1256 }; 1257 }; 1258 1259 timer { 1260 compatible = "arm,armv8-timer"; 1261 interrupts = <GIC_PPI 13 1262 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1263 <GIC_PPI 14 1264 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1265 <GIC_PPI 11 1266 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1267 <GIC_PPI 10 1268 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1269 }; 1270 1271 xtal: xtal-clk { 1272 compatible = "fixed-clock"; 1273 clock-frequency = <24000000>; 1274 clock-output-names = "xtal"; 1275 #clock-cells = <0>; 1276 }; 1277 1278}; 1279