19c8c52f7SJianxin Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29c8c52f7SJianxin Pan/* 39c8c52f7SJianxin Pan * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 49c8c52f7SJianxin Pan */ 59c8c52f7SJianxin Pan 69c8c52f7SJianxin Pan#include <dt-bindings/gpio/gpio.h> 7965c827aSJerome Brunet#include <dt-bindings/clock/g12a-clkc.h> 89c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/irq.h> 99c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/arm-gic.h> 109c8c52f7SJianxin Pan 119c8c52f7SJianxin Pan/ { 129c8c52f7SJianxin Pan compatible = "amlogic,g12a"; 139c8c52f7SJianxin Pan 149c8c52f7SJianxin Pan interrupt-parent = <&gic>; 159c8c52f7SJianxin Pan #address-cells = <2>; 169c8c52f7SJianxin Pan #size-cells = <2>; 179c8c52f7SJianxin Pan 189c8c52f7SJianxin Pan cpus { 199c8c52f7SJianxin Pan #address-cells = <0x2>; 209c8c52f7SJianxin Pan #size-cells = <0x0>; 219c8c52f7SJianxin Pan 229c8c52f7SJianxin Pan cpu0: cpu@0 { 239c8c52f7SJianxin Pan device_type = "cpu"; 2431af04cdSRob Herring compatible = "arm,cortex-a53"; 259c8c52f7SJianxin Pan reg = <0x0 0x0>; 269c8c52f7SJianxin Pan enable-method = "psci"; 279c8c52f7SJianxin Pan next-level-cache = <&l2>; 289c8c52f7SJianxin Pan }; 299c8c52f7SJianxin Pan 309c8c52f7SJianxin Pan cpu1: cpu@1 { 319c8c52f7SJianxin Pan device_type = "cpu"; 3231af04cdSRob Herring compatible = "arm,cortex-a53"; 339c8c52f7SJianxin Pan reg = <0x0 0x1>; 349c8c52f7SJianxin Pan enable-method = "psci"; 359c8c52f7SJianxin Pan next-level-cache = <&l2>; 369c8c52f7SJianxin Pan }; 379c8c52f7SJianxin Pan 389c8c52f7SJianxin Pan cpu2: cpu@2 { 399c8c52f7SJianxin Pan device_type = "cpu"; 4031af04cdSRob Herring compatible = "arm,cortex-a53"; 419c8c52f7SJianxin Pan reg = <0x0 0x2>; 429c8c52f7SJianxin Pan enable-method = "psci"; 439c8c52f7SJianxin Pan next-level-cache = <&l2>; 449c8c52f7SJianxin Pan }; 459c8c52f7SJianxin Pan 469c8c52f7SJianxin Pan cpu3: cpu@3 { 479c8c52f7SJianxin Pan device_type = "cpu"; 4831af04cdSRob Herring compatible = "arm,cortex-a53"; 499c8c52f7SJianxin Pan reg = <0x0 0x3>; 509c8c52f7SJianxin Pan enable-method = "psci"; 519c8c52f7SJianxin Pan next-level-cache = <&l2>; 529c8c52f7SJianxin Pan }; 539c8c52f7SJianxin Pan 549c8c52f7SJianxin Pan l2: l2-cache0 { 559c8c52f7SJianxin Pan compatible = "cache"; 569c8c52f7SJianxin Pan }; 579c8c52f7SJianxin Pan }; 589c8c52f7SJianxin Pan 59965c827aSJerome Brunet efuse: efuse { 60965c827aSJerome Brunet compatible = "amlogic,meson-gxbb-efuse"; 61965c827aSJerome Brunet clocks = <&clkc CLKID_EFUSE>; 62965c827aSJerome Brunet #address-cells = <1>; 63965c827aSJerome Brunet #size-cells = <1>; 64965c827aSJerome Brunet read-only; 65965c827aSJerome Brunet }; 66965c827aSJerome Brunet 679c8c52f7SJianxin Pan psci { 689c8c52f7SJianxin Pan compatible = "arm,psci-1.0"; 699c8c52f7SJianxin Pan method = "smc"; 709c8c52f7SJianxin Pan }; 719c8c52f7SJianxin Pan 729c8c52f7SJianxin Pan reserved-memory { 739c8c52f7SJianxin Pan #address-cells = <2>; 749c8c52f7SJianxin Pan #size-cells = <2>; 759c8c52f7SJianxin Pan ranges; 769c8c52f7SJianxin Pan 779c8c52f7SJianxin Pan /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 789c8c52f7SJianxin Pan secmon_reserved: secmon@5000000 { 799c8c52f7SJianxin Pan reg = <0x0 0x05000000 0x0 0x300000>; 809c8c52f7SJianxin Pan no-map; 819c8c52f7SJianxin Pan }; 82e2cffeb3SNeil Armstrong 83e2cffeb3SNeil Armstrong linux,cma { 84e2cffeb3SNeil Armstrong compatible = "shared-dma-pool"; 85e2cffeb3SNeil Armstrong reusable; 86e2cffeb3SNeil Armstrong size = <0x0 0x10000000>; 87e2cffeb3SNeil Armstrong alignment = <0x0 0x400000>; 88e2cffeb3SNeil Armstrong linux,cma-default; 89e2cffeb3SNeil Armstrong }; 909c8c52f7SJianxin Pan }; 919c8c52f7SJianxin Pan 92bd395152SJerome Brunet sm: secure-monitor { 93bd395152SJerome Brunet compatible = "amlogic,meson-gxbb-sm"; 94bd395152SJerome Brunet }; 95bd395152SJerome Brunet 969c8c52f7SJianxin Pan soc { 979c8c52f7SJianxin Pan compatible = "simple-bus"; 989c8c52f7SJianxin Pan #address-cells = <2>; 999c8c52f7SJianxin Pan #size-cells = <2>; 1009c8c52f7SJianxin Pan ranges; 1019c8c52f7SJianxin Pan 102503f5fedSJerome Brunet apb: bus@ff600000 { 1039c8c52f7SJianxin Pan compatible = "simple-bus"; 104503f5fedSJerome Brunet reg = <0x0 0xff600000 0x0 0x200000>; 1059c8c52f7SJianxin Pan #address-cells = <2>; 1069c8c52f7SJianxin Pan #size-cells = <2>; 107503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 108503f5fedSJerome Brunet 109503f5fedSJerome Brunet periphs: bus@34400 { 110503f5fedSJerome Brunet compatible = "simple-bus"; 111503f5fedSJerome Brunet reg = <0x0 0x34400 0x0 0x400>; 112503f5fedSJerome Brunet #address-cells = <2>; 113503f5fedSJerome Brunet #size-cells = <2>; 114503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 11511a7bea1SJerome Brunet 11611a7bea1SJerome Brunet periphs_pinctrl: pinctrl@40 { 11711a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-periphs-pinctrl"; 11811a7bea1SJerome Brunet #address-cells = <2>; 11911a7bea1SJerome Brunet #size-cells = <2>; 12011a7bea1SJerome Brunet ranges; 12111a7bea1SJerome Brunet 12211a7bea1SJerome Brunet gpio: bank@40 { 12311a7bea1SJerome Brunet reg = <0x0 0x40 0x0 0x4c>, 12411a7bea1SJerome Brunet <0x0 0xe8 0x0 0x18>, 12511a7bea1SJerome Brunet <0x0 0x120 0x0 0x18>, 12611a7bea1SJerome Brunet <0x0 0x2c0 0x0 0x40>, 12711a7bea1SJerome Brunet <0x0 0x340 0x0 0x1c>; 12811a7bea1SJerome Brunet reg-names = "gpio", 12911a7bea1SJerome Brunet "pull", 13011a7bea1SJerome Brunet "pull-enable", 13111a7bea1SJerome Brunet "mux", 13211a7bea1SJerome Brunet "ds"; 13311a7bea1SJerome Brunet gpio-controller; 13411a7bea1SJerome Brunet #gpio-cells = <2>; 13511a7bea1SJerome Brunet gpio-ranges = <&periphs_pinctrl 0 0 86>; 13611a7bea1SJerome Brunet }; 137ff4f8b6cSNeil Armstrong 138ff4f8b6cSNeil Armstrong uart_a_pins: uart-a { 139ff4f8b6cSNeil Armstrong mux { 140ff4f8b6cSNeil Armstrong groups = "uart_a_tx", 141ff4f8b6cSNeil Armstrong "uart_a_rx"; 142ff4f8b6cSNeil Armstrong function = "uart_a"; 143ff4f8b6cSNeil Armstrong bias-disable; 144ff4f8b6cSNeil Armstrong }; 145ff4f8b6cSNeil Armstrong }; 146ff4f8b6cSNeil Armstrong 147ff4f8b6cSNeil Armstrong uart_a_cts_rts_pins: uart-a-cts-rts { 148ff4f8b6cSNeil Armstrong mux { 149ff4f8b6cSNeil Armstrong groups = "uart_a_cts", 150ff4f8b6cSNeil Armstrong "uart_a_rts"; 151ff4f8b6cSNeil Armstrong function = "uart_a"; 152ff4f8b6cSNeil Armstrong bias-disable; 153ff4f8b6cSNeil Armstrong }; 154ff4f8b6cSNeil Armstrong }; 155ff4f8b6cSNeil Armstrong 156ff4f8b6cSNeil Armstrong uart_b_pins: uart-b { 157ff4f8b6cSNeil Armstrong mux { 158ff4f8b6cSNeil Armstrong groups = "uart_b_tx", 159ff4f8b6cSNeil Armstrong "uart_b_rx"; 160ff4f8b6cSNeil Armstrong function = "uart_b"; 161ff4f8b6cSNeil Armstrong bias-disable; 162ff4f8b6cSNeil Armstrong }; 163ff4f8b6cSNeil Armstrong }; 164ff4f8b6cSNeil Armstrong 165ff4f8b6cSNeil Armstrong uart_c_pins: uart-c { 166ff4f8b6cSNeil Armstrong mux { 167ff4f8b6cSNeil Armstrong groups = "uart_c_tx", 168ff4f8b6cSNeil Armstrong "uart_c_rx"; 169ff4f8b6cSNeil Armstrong function = "uart_c"; 170ff4f8b6cSNeil Armstrong bias-disable; 171ff4f8b6cSNeil Armstrong }; 172ff4f8b6cSNeil Armstrong }; 173ff4f8b6cSNeil Armstrong 174ff4f8b6cSNeil Armstrong uart_c_cts_rts_pins: uart-c-cts-rts { 175ff4f8b6cSNeil Armstrong mux { 176ff4f8b6cSNeil Armstrong groups = "uart_c_cts", 177ff4f8b6cSNeil Armstrong "uart_c_rts"; 178ff4f8b6cSNeil Armstrong function = "uart_c"; 179ff4f8b6cSNeil Armstrong bias-disable; 180ff4f8b6cSNeil Armstrong }; 181ff4f8b6cSNeil Armstrong }; 18211a7bea1SJerome Brunet }; 1839c8c52f7SJianxin Pan }; 1849c8c52f7SJianxin Pan 185503f5fedSJerome Brunet hiu: bus@3c000 { 1869c8c52f7SJianxin Pan compatible = "simple-bus"; 187503f5fedSJerome Brunet reg = <0x0 0x3c000 0x0 0x1400>; 1889c8c52f7SJianxin Pan #address-cells = <2>; 1899c8c52f7SJianxin Pan #size-cells = <2>; 190503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 191785fb434SJerome Brunet 192785fb434SJerome Brunet hhi: system-controller@0 { 193785fb434SJerome Brunet compatible = "amlogic,meson-gx-hhi-sysctrl", 194785fb434SJerome Brunet "simple-mfd", "syscon"; 195785fb434SJerome Brunet reg = <0 0 0 0x400>; 196785fb434SJerome Brunet 197785fb434SJerome Brunet clkc: clock-controller { 198785fb434SJerome Brunet compatible = "amlogic,g12a-clkc"; 199785fb434SJerome Brunet #clock-cells = <1>; 200785fb434SJerome Brunet clocks = <&xtal>; 201785fb434SJerome Brunet clock-names = "xtal"; 202785fb434SJerome Brunet }; 203785fb434SJerome Brunet }; 204503f5fedSJerome Brunet }; 2059c8c52f7SJianxin Pan }; 2069c8c52f7SJianxin Pan 2079c8c52f7SJianxin Pan aobus: bus@ff800000 { 2089c8c52f7SJianxin Pan compatible = "simple-bus"; 2099c8c52f7SJianxin Pan reg = <0x0 0xff800000 0x0 0x100000>; 2109c8c52f7SJianxin Pan #address-cells = <2>; 2119c8c52f7SJianxin Pan #size-cells = <2>; 2129c8c52f7SJianxin Pan ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 2139c8c52f7SJianxin Pan 214b019f4a4SNeil Armstrong rti: sys-ctrl@0 { 215b019f4a4SNeil Armstrong compatible = "amlogic,meson-gx-ao-sysctrl", 216b019f4a4SNeil Armstrong "simple-mfd", "syscon"; 217b019f4a4SNeil Armstrong reg = <0x0 0x0 0x0 0x100>; 218b019f4a4SNeil Armstrong #address-cells = <2>; 219b019f4a4SNeil Armstrong #size-cells = <2>; 220b019f4a4SNeil Armstrong ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 221b019f4a4SNeil Armstrong 222b019f4a4SNeil Armstrong clkc_AO: clock-controller { 223b019f4a4SNeil Armstrong compatible = "amlogic,meson-g12a-aoclkc"; 224b019f4a4SNeil Armstrong #clock-cells = <1>; 225b019f4a4SNeil Armstrong #reset-cells = <1>; 226b019f4a4SNeil Armstrong clocks = <&xtal>, <&clkc CLKID_CLK81>; 227b019f4a4SNeil Armstrong clock-names = "xtal", "mpeg-clk"; 228b019f4a4SNeil Armstrong }; 22911a7bea1SJerome Brunet 23011a7bea1SJerome Brunet ao_pinctrl: pinctrl@14 { 23111a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-aobus-pinctrl"; 23211a7bea1SJerome Brunet #address-cells = <2>; 23311a7bea1SJerome Brunet #size-cells = <2>; 23411a7bea1SJerome Brunet ranges; 23511a7bea1SJerome Brunet 23611a7bea1SJerome Brunet gpio_ao: bank@14 { 23711a7bea1SJerome Brunet reg = <0x0 0x14 0x0 0x8>, 23811a7bea1SJerome Brunet <0x0 0x1c 0x0 0x8>, 23911a7bea1SJerome Brunet <0x0 0x24 0x0 0x14>; 24011a7bea1SJerome Brunet reg-names = "mux", 24111a7bea1SJerome Brunet "ds", 24211a7bea1SJerome Brunet "gpio"; 24311a7bea1SJerome Brunet gpio-controller; 24411a7bea1SJerome Brunet #gpio-cells = <2>; 24511a7bea1SJerome Brunet gpio-ranges = <&ao_pinctrl 0 0 15>; 24611a7bea1SJerome Brunet }; 247e92546c2SJerome Brunet 248e92546c2SJerome Brunet uart_ao_a_pins: uart-a-ao { 249e92546c2SJerome Brunet mux { 250e92546c2SJerome Brunet groups = "uart_ao_a_tx", 251e92546c2SJerome Brunet "uart_ao_a_rx"; 252e92546c2SJerome Brunet function = "uart_ao_a"; 253e92546c2SJerome Brunet bias-disable; 254e92546c2SJerome Brunet }; 255e92546c2SJerome Brunet }; 256e92546c2SJerome Brunet 257e92546c2SJerome Brunet uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 258e92546c2SJerome Brunet mux { 259e92546c2SJerome Brunet groups = "uart_ao_a_cts", 260e92546c2SJerome Brunet "uart_ao_a_rts"; 261e92546c2SJerome Brunet function = "uart_ao_a"; 262e92546c2SJerome Brunet bias-disable; 263e92546c2SJerome Brunet }; 264e92546c2SJerome Brunet }; 26511a7bea1SJerome Brunet }; 266b019f4a4SNeil Armstrong }; 267b019f4a4SNeil Armstrong 2680fa724c5SNeil Armstrong sec_AO: ao-secure@140 { 2690fa724c5SNeil Armstrong compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2700fa724c5SNeil Armstrong reg = <0x0 0x140 0x0 0x140>; 2710fa724c5SNeil Armstrong amlogic,has-chip-id; 2720fa724c5SNeil Armstrong }; 2730fa724c5SNeil Armstrong 2749c8c52f7SJianxin Pan uart_AO: serial@3000 { 275503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 276503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 2779c8c52f7SJianxin Pan reg = <0x0 0x3000 0x0 0x18>; 2789c8c52f7SJianxin Pan interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2799c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 2809c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 2819c8c52f7SJianxin Pan status = "disabled"; 2829c8c52f7SJianxin Pan }; 2839c8c52f7SJianxin Pan 2849c8c52f7SJianxin Pan uart_AO_B: serial@4000 { 285503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 286503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 2879c8c52f7SJianxin Pan reg = <0x0 0x4000 0x0 0x18>; 2889c8c52f7SJianxin Pan interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2899c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 2909c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 2919c8c52f7SJianxin Pan status = "disabled"; 2929c8c52f7SJianxin Pan }; 2939c8c52f7SJianxin Pan }; 2949c8c52f7SJianxin Pan 2959c8c52f7SJianxin Pan gic: interrupt-controller@ffc01000 { 2969c8c52f7SJianxin Pan compatible = "arm,gic-400"; 2979c8c52f7SJianxin Pan reg = <0x0 0xffc01000 0 0x1000>, 2989c8c52f7SJianxin Pan <0x0 0xffc02000 0 0x2000>, 2999c8c52f7SJianxin Pan <0x0 0xffc04000 0 0x2000>, 3009c8c52f7SJianxin Pan <0x0 0xffc06000 0 0x2000>; 3019c8c52f7SJianxin Pan interrupt-controller; 3029c8c52f7SJianxin Pan interrupts = <GIC_PPI 9 3039c8c52f7SJianxin Pan (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 3049c8c52f7SJianxin Pan #interrupt-cells = <3>; 3059c8c52f7SJianxin Pan #address-cells = <0>; 3069c8c52f7SJianxin Pan }; 3079c8c52f7SJianxin Pan 3089c8c52f7SJianxin Pan cbus: bus@ffd00000 { 3099c8c52f7SJianxin Pan compatible = "simple-bus"; 310503f5fedSJerome Brunet reg = <0x0 0xffd00000 0x0 0x100000>; 3119c8c52f7SJianxin Pan #address-cells = <2>; 3129c8c52f7SJianxin Pan #size-cells = <2>; 313503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 3149c8c52f7SJianxin Pan 3157ab41c47SJerome Brunet reset: reset-controller@1004 { 3167ab41c47SJerome Brunet compatible = "amlogic,meson-g12a-reset", 3177ab41c47SJerome Brunet "amlogic,meson-axg-reset"; 3187ab41c47SJerome Brunet reg = <0x0 0x1004 0x0 0x9c>; 3197ab41c47SJerome Brunet #reset-cells = <1>; 3207ab41c47SJerome Brunet }; 3217ab41c47SJerome Brunet 32260d4fdb8SJerome Brunet clk_msr: clock-measure@18000 { 32360d4fdb8SJerome Brunet compatible = "amlogic,meson-g12a-clk-measure"; 32460d4fdb8SJerome Brunet reg = <0x0 0x18000 0x0 0x10>; 32560d4fdb8SJerome Brunet }; 326ff4f8b6cSNeil Armstrong 327ff4f8b6cSNeil Armstrong uart_C: serial@22000 { 328ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 329ff4f8b6cSNeil Armstrong reg = <0x0 0x22000 0x0 0x18>; 330ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 331ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 332ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 333ff4f8b6cSNeil Armstrong status = "disabled"; 334ff4f8b6cSNeil Armstrong }; 335ff4f8b6cSNeil Armstrong 336ff4f8b6cSNeil Armstrong uart_B: serial@23000 { 337ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 338ff4f8b6cSNeil Armstrong reg = <0x0 0x23000 0x0 0x18>; 339ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 340ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 341ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 342ff4f8b6cSNeil Armstrong status = "disabled"; 343ff4f8b6cSNeil Armstrong }; 344ff4f8b6cSNeil Armstrong 345ff4f8b6cSNeil Armstrong uart_A: serial@24000 { 346ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 347ff4f8b6cSNeil Armstrong reg = <0x0 0x24000 0x0 0x18>; 348ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 349ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 350ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 351ff4f8b6cSNeil Armstrong status = "disabled"; 352ff4f8b6cSNeil Armstrong }; 3539c8c52f7SJianxin Pan }; 3549c8c52f7SJianxin Pan }; 3559c8c52f7SJianxin Pan 3569c8c52f7SJianxin Pan timer { 3579c8c52f7SJianxin Pan compatible = "arm,armv8-timer"; 3589c8c52f7SJianxin Pan interrupts = <GIC_PPI 13 3599c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3609c8c52f7SJianxin Pan <GIC_PPI 14 3619c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3629c8c52f7SJianxin Pan <GIC_PPI 11 3639c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3649c8c52f7SJianxin Pan <GIC_PPI 10 3659c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 3669c8c52f7SJianxin Pan }; 3679c8c52f7SJianxin Pan 3689c8c52f7SJianxin Pan xtal: xtal-clk { 3699c8c52f7SJianxin Pan compatible = "fixed-clock"; 3709c8c52f7SJianxin Pan clock-frequency = <24000000>; 3719c8c52f7SJianxin Pan clock-output-names = "xtal"; 3729c8c52f7SJianxin Pan #clock-cells = <0>; 3739c8c52f7SJianxin Pan }; 3749c8c52f7SJianxin Pan 3759c8c52f7SJianxin Pan}; 376