19c8c52f7SJianxin Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29c8c52f7SJianxin Pan/* 39c8c52f7SJianxin Pan * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 49c8c52f7SJianxin Pan */ 59c8c52f7SJianxin Pan 69c8c52f7SJianxin Pan#include <dt-bindings/gpio/gpio.h> 7965c827aSJerome Brunet#include <dt-bindings/clock/g12a-clkc.h> 8820873cfSNeil Armstrong#include <dt-bindings/clock/g12a-aoclkc.h> 99c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/irq.h> 109c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/arm-gic.h> 119c8c52f7SJianxin Pan 129c8c52f7SJianxin Pan/ { 139c8c52f7SJianxin Pan compatible = "amlogic,g12a"; 149c8c52f7SJianxin Pan 159c8c52f7SJianxin Pan interrupt-parent = <&gic>; 169c8c52f7SJianxin Pan #address-cells = <2>; 179c8c52f7SJianxin Pan #size-cells = <2>; 189c8c52f7SJianxin Pan 199c8c52f7SJianxin Pan cpus { 209c8c52f7SJianxin Pan #address-cells = <0x2>; 219c8c52f7SJianxin Pan #size-cells = <0x0>; 229c8c52f7SJianxin Pan 239c8c52f7SJianxin Pan cpu0: cpu@0 { 249c8c52f7SJianxin Pan device_type = "cpu"; 2531af04cdSRob Herring compatible = "arm,cortex-a53"; 269c8c52f7SJianxin Pan reg = <0x0 0x0>; 279c8c52f7SJianxin Pan enable-method = "psci"; 289c8c52f7SJianxin Pan next-level-cache = <&l2>; 299c8c52f7SJianxin Pan }; 309c8c52f7SJianxin Pan 319c8c52f7SJianxin Pan cpu1: cpu@1 { 329c8c52f7SJianxin Pan device_type = "cpu"; 3331af04cdSRob Herring compatible = "arm,cortex-a53"; 349c8c52f7SJianxin Pan reg = <0x0 0x1>; 359c8c52f7SJianxin Pan enable-method = "psci"; 369c8c52f7SJianxin Pan next-level-cache = <&l2>; 379c8c52f7SJianxin Pan }; 389c8c52f7SJianxin Pan 399c8c52f7SJianxin Pan cpu2: cpu@2 { 409c8c52f7SJianxin Pan device_type = "cpu"; 4131af04cdSRob Herring compatible = "arm,cortex-a53"; 429c8c52f7SJianxin Pan reg = <0x0 0x2>; 439c8c52f7SJianxin Pan enable-method = "psci"; 449c8c52f7SJianxin Pan next-level-cache = <&l2>; 459c8c52f7SJianxin Pan }; 469c8c52f7SJianxin Pan 479c8c52f7SJianxin Pan cpu3: cpu@3 { 489c8c52f7SJianxin Pan device_type = "cpu"; 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 509c8c52f7SJianxin Pan reg = <0x0 0x3>; 519c8c52f7SJianxin Pan enable-method = "psci"; 529c8c52f7SJianxin Pan next-level-cache = <&l2>; 539c8c52f7SJianxin Pan }; 549c8c52f7SJianxin Pan 559c8c52f7SJianxin Pan l2: l2-cache0 { 569c8c52f7SJianxin Pan compatible = "cache"; 579c8c52f7SJianxin Pan }; 589c8c52f7SJianxin Pan }; 599c8c52f7SJianxin Pan 60965c827aSJerome Brunet efuse: efuse { 61965c827aSJerome Brunet compatible = "amlogic,meson-gxbb-efuse"; 62965c827aSJerome Brunet clocks = <&clkc CLKID_EFUSE>; 63965c827aSJerome Brunet #address-cells = <1>; 64965c827aSJerome Brunet #size-cells = <1>; 65965c827aSJerome Brunet read-only; 66965c827aSJerome Brunet }; 67965c827aSJerome Brunet 689c8c52f7SJianxin Pan psci { 699c8c52f7SJianxin Pan compatible = "arm,psci-1.0"; 709c8c52f7SJianxin Pan method = "smc"; 719c8c52f7SJianxin Pan }; 729c8c52f7SJianxin Pan 739c8c52f7SJianxin Pan reserved-memory { 749c8c52f7SJianxin Pan #address-cells = <2>; 759c8c52f7SJianxin Pan #size-cells = <2>; 769c8c52f7SJianxin Pan ranges; 779c8c52f7SJianxin Pan 789c8c52f7SJianxin Pan /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 799c8c52f7SJianxin Pan secmon_reserved: secmon@5000000 { 809c8c52f7SJianxin Pan reg = <0x0 0x05000000 0x0 0x300000>; 819c8c52f7SJianxin Pan no-map; 829c8c52f7SJianxin Pan }; 83e2cffeb3SNeil Armstrong 84e2cffeb3SNeil Armstrong linux,cma { 85e2cffeb3SNeil Armstrong compatible = "shared-dma-pool"; 86e2cffeb3SNeil Armstrong reusable; 87e2cffeb3SNeil Armstrong size = <0x0 0x10000000>; 88e2cffeb3SNeil Armstrong alignment = <0x0 0x400000>; 89e2cffeb3SNeil Armstrong linux,cma-default; 90e2cffeb3SNeil Armstrong }; 919c8c52f7SJianxin Pan }; 929c8c52f7SJianxin Pan 93bd395152SJerome Brunet sm: secure-monitor { 94bd395152SJerome Brunet compatible = "amlogic,meson-gxbb-sm"; 95bd395152SJerome Brunet }; 96bd395152SJerome Brunet 979c8c52f7SJianxin Pan soc { 989c8c52f7SJianxin Pan compatible = "simple-bus"; 999c8c52f7SJianxin Pan #address-cells = <2>; 1009c8c52f7SJianxin Pan #size-cells = <2>; 1019c8c52f7SJianxin Pan ranges; 1029c8c52f7SJianxin Pan 103503f5fedSJerome Brunet apb: bus@ff600000 { 1049c8c52f7SJianxin Pan compatible = "simple-bus"; 105503f5fedSJerome Brunet reg = <0x0 0xff600000 0x0 0x200000>; 1069c8c52f7SJianxin Pan #address-cells = <2>; 1079c8c52f7SJianxin Pan #size-cells = <2>; 108503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 109503f5fedSJerome Brunet 110503f5fedSJerome Brunet periphs: bus@34400 { 111503f5fedSJerome Brunet compatible = "simple-bus"; 112503f5fedSJerome Brunet reg = <0x0 0x34400 0x0 0x400>; 113503f5fedSJerome Brunet #address-cells = <2>; 114503f5fedSJerome Brunet #size-cells = <2>; 115503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 11611a7bea1SJerome Brunet 11711a7bea1SJerome Brunet periphs_pinctrl: pinctrl@40 { 11811a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-periphs-pinctrl"; 11911a7bea1SJerome Brunet #address-cells = <2>; 12011a7bea1SJerome Brunet #size-cells = <2>; 12111a7bea1SJerome Brunet ranges; 12211a7bea1SJerome Brunet 12311a7bea1SJerome Brunet gpio: bank@40 { 12411a7bea1SJerome Brunet reg = <0x0 0x40 0x0 0x4c>, 12511a7bea1SJerome Brunet <0x0 0xe8 0x0 0x18>, 12611a7bea1SJerome Brunet <0x0 0x120 0x0 0x18>, 12711a7bea1SJerome Brunet <0x0 0x2c0 0x0 0x40>, 12811a7bea1SJerome Brunet <0x0 0x340 0x0 0x1c>; 12911a7bea1SJerome Brunet reg-names = "gpio", 13011a7bea1SJerome Brunet "pull", 13111a7bea1SJerome Brunet "pull-enable", 13211a7bea1SJerome Brunet "mux", 13311a7bea1SJerome Brunet "ds"; 13411a7bea1SJerome Brunet gpio-controller; 13511a7bea1SJerome Brunet #gpio-cells = <2>; 13611a7bea1SJerome Brunet gpio-ranges = <&periphs_pinctrl 0 0 86>; 13711a7bea1SJerome Brunet }; 138ff4f8b6cSNeil Armstrong 139ff4f8b6cSNeil Armstrong uart_a_pins: uart-a { 140ff4f8b6cSNeil Armstrong mux { 141ff4f8b6cSNeil Armstrong groups = "uart_a_tx", 142ff4f8b6cSNeil Armstrong "uart_a_rx"; 143ff4f8b6cSNeil Armstrong function = "uart_a"; 144ff4f8b6cSNeil Armstrong bias-disable; 145ff4f8b6cSNeil Armstrong }; 146ff4f8b6cSNeil Armstrong }; 147ff4f8b6cSNeil Armstrong 148ff4f8b6cSNeil Armstrong uart_a_cts_rts_pins: uart-a-cts-rts { 149ff4f8b6cSNeil Armstrong mux { 150ff4f8b6cSNeil Armstrong groups = "uart_a_cts", 151ff4f8b6cSNeil Armstrong "uart_a_rts"; 152ff4f8b6cSNeil Armstrong function = "uart_a"; 153ff4f8b6cSNeil Armstrong bias-disable; 154ff4f8b6cSNeil Armstrong }; 155ff4f8b6cSNeil Armstrong }; 156ff4f8b6cSNeil Armstrong 157ff4f8b6cSNeil Armstrong uart_b_pins: uart-b { 158ff4f8b6cSNeil Armstrong mux { 159ff4f8b6cSNeil Armstrong groups = "uart_b_tx", 160ff4f8b6cSNeil Armstrong "uart_b_rx"; 161ff4f8b6cSNeil Armstrong function = "uart_b"; 162ff4f8b6cSNeil Armstrong bias-disable; 163ff4f8b6cSNeil Armstrong }; 164ff4f8b6cSNeil Armstrong }; 165ff4f8b6cSNeil Armstrong 166ff4f8b6cSNeil Armstrong uart_c_pins: uart-c { 167ff4f8b6cSNeil Armstrong mux { 168ff4f8b6cSNeil Armstrong groups = "uart_c_tx", 169ff4f8b6cSNeil Armstrong "uart_c_rx"; 170ff4f8b6cSNeil Armstrong function = "uart_c"; 171ff4f8b6cSNeil Armstrong bias-disable; 172ff4f8b6cSNeil Armstrong }; 173ff4f8b6cSNeil Armstrong }; 174ff4f8b6cSNeil Armstrong 175ff4f8b6cSNeil Armstrong uart_c_cts_rts_pins: uart-c-cts-rts { 176ff4f8b6cSNeil Armstrong mux { 177ff4f8b6cSNeil Armstrong groups = "uart_c_cts", 178ff4f8b6cSNeil Armstrong "uart_c_rts"; 179ff4f8b6cSNeil Armstrong function = "uart_c"; 180ff4f8b6cSNeil Armstrong bias-disable; 181ff4f8b6cSNeil Armstrong }; 182ff4f8b6cSNeil Armstrong }; 18311a7bea1SJerome Brunet }; 1849c8c52f7SJianxin Pan }; 1859c8c52f7SJianxin Pan 186503f5fedSJerome Brunet hiu: bus@3c000 { 1879c8c52f7SJianxin Pan compatible = "simple-bus"; 188503f5fedSJerome Brunet reg = <0x0 0x3c000 0x0 0x1400>; 1899c8c52f7SJianxin Pan #address-cells = <2>; 1909c8c52f7SJianxin Pan #size-cells = <2>; 191503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 192785fb434SJerome Brunet 193785fb434SJerome Brunet hhi: system-controller@0 { 194785fb434SJerome Brunet compatible = "amlogic,meson-gx-hhi-sysctrl", 195785fb434SJerome Brunet "simple-mfd", "syscon"; 196785fb434SJerome Brunet reg = <0 0 0 0x400>; 197785fb434SJerome Brunet 198785fb434SJerome Brunet clkc: clock-controller { 199785fb434SJerome Brunet compatible = "amlogic,g12a-clkc"; 200785fb434SJerome Brunet #clock-cells = <1>; 201785fb434SJerome Brunet clocks = <&xtal>; 202785fb434SJerome Brunet clock-names = "xtal"; 203785fb434SJerome Brunet }; 204785fb434SJerome Brunet }; 205503f5fedSJerome Brunet }; 2069c8c52f7SJianxin Pan }; 2079c8c52f7SJianxin Pan 2089c8c52f7SJianxin Pan aobus: bus@ff800000 { 2099c8c52f7SJianxin Pan compatible = "simple-bus"; 2109c8c52f7SJianxin Pan reg = <0x0 0xff800000 0x0 0x100000>; 2119c8c52f7SJianxin Pan #address-cells = <2>; 2129c8c52f7SJianxin Pan #size-cells = <2>; 2139c8c52f7SJianxin Pan ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 2149c8c52f7SJianxin Pan 215b019f4a4SNeil Armstrong rti: sys-ctrl@0 { 216b019f4a4SNeil Armstrong compatible = "amlogic,meson-gx-ao-sysctrl", 217b019f4a4SNeil Armstrong "simple-mfd", "syscon"; 218b019f4a4SNeil Armstrong reg = <0x0 0x0 0x0 0x100>; 219b019f4a4SNeil Armstrong #address-cells = <2>; 220b019f4a4SNeil Armstrong #size-cells = <2>; 221b019f4a4SNeil Armstrong ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 222b019f4a4SNeil Armstrong 223b019f4a4SNeil Armstrong clkc_AO: clock-controller { 224b019f4a4SNeil Armstrong compatible = "amlogic,meson-g12a-aoclkc"; 225b019f4a4SNeil Armstrong #clock-cells = <1>; 226b019f4a4SNeil Armstrong #reset-cells = <1>; 227b019f4a4SNeil Armstrong clocks = <&xtal>, <&clkc CLKID_CLK81>; 228b019f4a4SNeil Armstrong clock-names = "xtal", "mpeg-clk"; 229b019f4a4SNeil Armstrong }; 23011a7bea1SJerome Brunet 23111a7bea1SJerome Brunet ao_pinctrl: pinctrl@14 { 23211a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-aobus-pinctrl"; 23311a7bea1SJerome Brunet #address-cells = <2>; 23411a7bea1SJerome Brunet #size-cells = <2>; 23511a7bea1SJerome Brunet ranges; 23611a7bea1SJerome Brunet 23711a7bea1SJerome Brunet gpio_ao: bank@14 { 23811a7bea1SJerome Brunet reg = <0x0 0x14 0x0 0x8>, 23911a7bea1SJerome Brunet <0x0 0x1c 0x0 0x8>, 24011a7bea1SJerome Brunet <0x0 0x24 0x0 0x14>; 24111a7bea1SJerome Brunet reg-names = "mux", 24211a7bea1SJerome Brunet "ds", 24311a7bea1SJerome Brunet "gpio"; 24411a7bea1SJerome Brunet gpio-controller; 24511a7bea1SJerome Brunet #gpio-cells = <2>; 24611a7bea1SJerome Brunet gpio-ranges = <&ao_pinctrl 0 0 15>; 24711a7bea1SJerome Brunet }; 248e92546c2SJerome Brunet 249e92546c2SJerome Brunet uart_ao_a_pins: uart-a-ao { 250e92546c2SJerome Brunet mux { 251e92546c2SJerome Brunet groups = "uart_ao_a_tx", 252e92546c2SJerome Brunet "uart_ao_a_rx"; 253e92546c2SJerome Brunet function = "uart_ao_a"; 254e92546c2SJerome Brunet bias-disable; 255e92546c2SJerome Brunet }; 256e92546c2SJerome Brunet }; 257e92546c2SJerome Brunet 258e92546c2SJerome Brunet uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 259e92546c2SJerome Brunet mux { 260e92546c2SJerome Brunet groups = "uart_ao_a_cts", 261e92546c2SJerome Brunet "uart_ao_a_rts"; 262e92546c2SJerome Brunet function = "uart_ao_a"; 263e92546c2SJerome Brunet bias-disable; 264e92546c2SJerome Brunet }; 265e92546c2SJerome Brunet }; 26611a7bea1SJerome Brunet }; 267b019f4a4SNeil Armstrong }; 268b019f4a4SNeil Armstrong 2690fa724c5SNeil Armstrong sec_AO: ao-secure@140 { 2700fa724c5SNeil Armstrong compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2710fa724c5SNeil Armstrong reg = <0x0 0x140 0x0 0x140>; 2720fa724c5SNeil Armstrong amlogic,has-chip-id; 2730fa724c5SNeil Armstrong }; 2740fa724c5SNeil Armstrong 2759c8c52f7SJianxin Pan uart_AO: serial@3000 { 276503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 277503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 2789c8c52f7SJianxin Pan reg = <0x0 0x3000 0x0 0x18>; 2799c8c52f7SJianxin Pan interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2809c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 2819c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 2829c8c52f7SJianxin Pan status = "disabled"; 2839c8c52f7SJianxin Pan }; 2849c8c52f7SJianxin Pan 2859c8c52f7SJianxin Pan uart_AO_B: serial@4000 { 286503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 287503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 2889c8c52f7SJianxin Pan reg = <0x0 0x4000 0x0 0x18>; 2899c8c52f7SJianxin Pan interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2909c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 2919c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 2929c8c52f7SJianxin Pan status = "disabled"; 2939c8c52f7SJianxin Pan }; 294820873cfSNeil Armstrong 295820873cfSNeil Armstrong saradc: adc@9000 { 296820873cfSNeil Armstrong compatible = "amlogic,meson-g12a-saradc", 297820873cfSNeil Armstrong "amlogic,meson-saradc"; 298820873cfSNeil Armstrong reg = <0x0 0x9000 0x0 0x48>; 299820873cfSNeil Armstrong #io-channel-cells = <1>; 300820873cfSNeil Armstrong interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 301820873cfSNeil Armstrong clocks = <&xtal>, 302820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC>, 303820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 304820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 305820873cfSNeil Armstrong clock-names = "clkin", "core", "adc_clk", "adc_sel"; 306820873cfSNeil Armstrong status = "disabled"; 307820873cfSNeil Armstrong }; 3089c8c52f7SJianxin Pan }; 3099c8c52f7SJianxin Pan 3109c8c52f7SJianxin Pan gic: interrupt-controller@ffc01000 { 3119c8c52f7SJianxin Pan compatible = "arm,gic-400"; 3129c8c52f7SJianxin Pan reg = <0x0 0xffc01000 0 0x1000>, 3139c8c52f7SJianxin Pan <0x0 0xffc02000 0 0x2000>, 3149c8c52f7SJianxin Pan <0x0 0xffc04000 0 0x2000>, 3159c8c52f7SJianxin Pan <0x0 0xffc06000 0 0x2000>; 3169c8c52f7SJianxin Pan interrupt-controller; 3179c8c52f7SJianxin Pan interrupts = <GIC_PPI 9 3189c8c52f7SJianxin Pan (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 3199c8c52f7SJianxin Pan #interrupt-cells = <3>; 3209c8c52f7SJianxin Pan #address-cells = <0>; 3219c8c52f7SJianxin Pan }; 3229c8c52f7SJianxin Pan 3239c8c52f7SJianxin Pan cbus: bus@ffd00000 { 3249c8c52f7SJianxin Pan compatible = "simple-bus"; 325503f5fedSJerome Brunet reg = <0x0 0xffd00000 0x0 0x100000>; 3269c8c52f7SJianxin Pan #address-cells = <2>; 3279c8c52f7SJianxin Pan #size-cells = <2>; 328503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 3299c8c52f7SJianxin Pan 3307ab41c47SJerome Brunet reset: reset-controller@1004 { 3317ab41c47SJerome Brunet compatible = "amlogic,meson-g12a-reset", 3327ab41c47SJerome Brunet "amlogic,meson-axg-reset"; 3337ab41c47SJerome Brunet reg = <0x0 0x1004 0x0 0x9c>; 3347ab41c47SJerome Brunet #reset-cells = <1>; 3357ab41c47SJerome Brunet }; 3367ab41c47SJerome Brunet 33760d4fdb8SJerome Brunet clk_msr: clock-measure@18000 { 33860d4fdb8SJerome Brunet compatible = "amlogic,meson-g12a-clk-measure"; 33960d4fdb8SJerome Brunet reg = <0x0 0x18000 0x0 0x10>; 34060d4fdb8SJerome Brunet }; 341ff4f8b6cSNeil Armstrong 342ff4f8b6cSNeil Armstrong uart_C: serial@22000 { 343ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 344ff4f8b6cSNeil Armstrong reg = <0x0 0x22000 0x0 0x18>; 345ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 346ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 347ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 348ff4f8b6cSNeil Armstrong status = "disabled"; 349ff4f8b6cSNeil Armstrong }; 350ff4f8b6cSNeil Armstrong 351ff4f8b6cSNeil Armstrong uart_B: serial@23000 { 352ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 353ff4f8b6cSNeil Armstrong reg = <0x0 0x23000 0x0 0x18>; 354ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 355ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 356ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 357ff4f8b6cSNeil Armstrong status = "disabled"; 358ff4f8b6cSNeil Armstrong }; 359ff4f8b6cSNeil Armstrong 360ff4f8b6cSNeil Armstrong uart_A: serial@24000 { 361ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 362ff4f8b6cSNeil Armstrong reg = <0x0 0x24000 0x0 0x18>; 363ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 364ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 365ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 366ff4f8b6cSNeil Armstrong status = "disabled"; 367ff4f8b6cSNeil Armstrong }; 3689c8c52f7SJianxin Pan }; 3699c8c52f7SJianxin Pan }; 3709c8c52f7SJianxin Pan 3719c8c52f7SJianxin Pan timer { 3729c8c52f7SJianxin Pan compatible = "arm,armv8-timer"; 3739c8c52f7SJianxin Pan interrupts = <GIC_PPI 13 3749c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3759c8c52f7SJianxin Pan <GIC_PPI 14 3769c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3779c8c52f7SJianxin Pan <GIC_PPI 11 3789c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 3799c8c52f7SJianxin Pan <GIC_PPI 10 3809c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 3819c8c52f7SJianxin Pan }; 3829c8c52f7SJianxin Pan 3839c8c52f7SJianxin Pan xtal: xtal-clk { 3849c8c52f7SJianxin Pan compatible = "fixed-clock"; 3859c8c52f7SJianxin Pan clock-frequency = <24000000>; 3869c8c52f7SJianxin Pan clock-output-names = "xtal"; 3879c8c52f7SJianxin Pan #clock-cells = <0>; 3889c8c52f7SJianxin Pan }; 3899c8c52f7SJianxin Pan 3909c8c52f7SJianxin Pan}; 391