19c8c52f7SJianxin Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29c8c52f7SJianxin Pan/* 39c8c52f7SJianxin Pan * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 49c8c52f7SJianxin Pan */ 59c8c52f7SJianxin Pan 69ed437d6SJerome Brunet#include "meson-g12.dtsi" 79c8c52f7SJianxin Pan 89c8c52f7SJianxin Pan/ { 99c8c52f7SJianxin Pan compatible = "amlogic,g12a"; 109c8c52f7SJianxin Pan 119c8c52f7SJianxin Pan cpus { 129c8c52f7SJianxin Pan #address-cells = <0x2>; 139c8c52f7SJianxin Pan #size-cells = <0x0>; 149c8c52f7SJianxin Pan 159c8c52f7SJianxin Pan cpu0: cpu@0 { 169c8c52f7SJianxin Pan device_type = "cpu"; 1731af04cdSRob Herring compatible = "arm,cortex-a53"; 189c8c52f7SJianxin Pan reg = <0x0 0x0>; 199c8c52f7SJianxin Pan enable-method = "psci"; 209c8c52f7SJianxin Pan next-level-cache = <&l2>; 218eef8bcaSGuillaume La Roque #cooling-cells = <2>; 229c8c52f7SJianxin Pan }; 239c8c52f7SJianxin Pan 249c8c52f7SJianxin Pan cpu1: cpu@1 { 259c8c52f7SJianxin Pan device_type = "cpu"; 2631af04cdSRob Herring compatible = "arm,cortex-a53"; 279c8c52f7SJianxin Pan reg = <0x0 0x1>; 289c8c52f7SJianxin Pan enable-method = "psci"; 299c8c52f7SJianxin Pan next-level-cache = <&l2>; 308eef8bcaSGuillaume La Roque #cooling-cells = <2>; 319c8c52f7SJianxin Pan }; 329c8c52f7SJianxin Pan 339c8c52f7SJianxin Pan cpu2: cpu@2 { 349c8c52f7SJianxin Pan device_type = "cpu"; 3531af04cdSRob Herring compatible = "arm,cortex-a53"; 369c8c52f7SJianxin Pan reg = <0x0 0x2>; 379c8c52f7SJianxin Pan enable-method = "psci"; 389c8c52f7SJianxin Pan next-level-cache = <&l2>; 398eef8bcaSGuillaume La Roque #cooling-cells = <2>; 409c8c52f7SJianxin Pan }; 419c8c52f7SJianxin Pan 429c8c52f7SJianxin Pan cpu3: cpu@3 { 439c8c52f7SJianxin Pan device_type = "cpu"; 4431af04cdSRob Herring compatible = "arm,cortex-a53"; 459c8c52f7SJianxin Pan reg = <0x0 0x3>; 469c8c52f7SJianxin Pan enable-method = "psci"; 479c8c52f7SJianxin Pan next-level-cache = <&l2>; 488eef8bcaSGuillaume La Roque #cooling-cells = <2>; 499c8c52f7SJianxin Pan }; 509c8c52f7SJianxin Pan 519c8c52f7SJianxin Pan l2: l2-cache0 { 529c8c52f7SJianxin Pan compatible = "cache"; 53*49f65e2eSPierre Gondois cache-level = <2>; 549c8c52f7SJianxin Pan }; 559c8c52f7SJianxin Pan }; 56b190056fSNeil Armstrong 57b190056fSNeil Armstrong cpu_opp_table: opp-table { 58b190056fSNeil Armstrong compatible = "operating-points-v2"; 59b190056fSNeil Armstrong opp-shared; 60b190056fSNeil Armstrong 61b190056fSNeil Armstrong opp-100000000 { 62b190056fSNeil Armstrong opp-hz = /bits/ 64 <100000000>; 63b190056fSNeil Armstrong opp-microvolt = <731000>; 64b190056fSNeil Armstrong }; 65b190056fSNeil Armstrong 66b190056fSNeil Armstrong opp-250000000 { 67b190056fSNeil Armstrong opp-hz = /bits/ 64 <250000000>; 68b190056fSNeil Armstrong opp-microvolt = <731000>; 69b190056fSNeil Armstrong }; 70b190056fSNeil Armstrong 71b190056fSNeil Armstrong opp-500000000 { 72b190056fSNeil Armstrong opp-hz = /bits/ 64 <500000000>; 73b190056fSNeil Armstrong opp-microvolt = <731000>; 74b190056fSNeil Armstrong }; 75b190056fSNeil Armstrong 76b190056fSNeil Armstrong opp-667000000 { 77b190056fSNeil Armstrong opp-hz = /bits/ 64 <666666666>; 78b190056fSNeil Armstrong opp-microvolt = <731000>; 79b190056fSNeil Armstrong }; 80b190056fSNeil Armstrong 81b190056fSNeil Armstrong opp-1000000000 { 82b190056fSNeil Armstrong opp-hz = /bits/ 64 <1000000000>; 83b190056fSNeil Armstrong opp-microvolt = <731000>; 84b190056fSNeil Armstrong }; 85b190056fSNeil Armstrong 86b190056fSNeil Armstrong opp-1200000000 { 87b190056fSNeil Armstrong opp-hz = /bits/ 64 <1200000000>; 88b190056fSNeil Armstrong opp-microvolt = <731000>; 89b190056fSNeil Armstrong }; 90b190056fSNeil Armstrong 91b190056fSNeil Armstrong opp-1398000000 { 92b190056fSNeil Armstrong opp-hz = /bits/ 64 <1398000000>; 93b190056fSNeil Armstrong opp-microvolt = <761000>; 94b190056fSNeil Armstrong }; 95b190056fSNeil Armstrong 96b190056fSNeil Armstrong opp-1512000000 { 97b190056fSNeil Armstrong opp-hz = /bits/ 64 <1512000000>; 98b190056fSNeil Armstrong opp-microvolt = <791000>; 99b190056fSNeil Armstrong }; 100b190056fSNeil Armstrong 101b190056fSNeil Armstrong opp-1608000000 { 102b190056fSNeil Armstrong opp-hz = /bits/ 64 <1608000000>; 103b190056fSNeil Armstrong opp-microvolt = <831000>; 104b190056fSNeil Armstrong }; 105b190056fSNeil Armstrong 106b190056fSNeil Armstrong opp-1704000000 { 107b190056fSNeil Armstrong opp-hz = /bits/ 64 <1704000000>; 108b190056fSNeil Armstrong opp-microvolt = <861000>; 109b190056fSNeil Armstrong }; 110b190056fSNeil Armstrong 111b190056fSNeil Armstrong opp-1800000000 { 112b190056fSNeil Armstrong opp-hz = /bits/ 64 <1800000000>; 113b190056fSNeil Armstrong opp-microvolt = <981000>; 114b190056fSNeil Armstrong }; 115b190056fSNeil Armstrong }; 116965c827aSJerome Brunet}; 1178eef8bcaSGuillaume La Roque 1188eef8bcaSGuillaume La Roque&cpu_thermal { 1198eef8bcaSGuillaume La Roque cooling-maps { 1208eef8bcaSGuillaume La Roque map0 { 1218eef8bcaSGuillaume La Roque trip = <&cpu_passive>; 1228eef8bcaSGuillaume La Roque cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1238eef8bcaSGuillaume La Roque <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1248eef8bcaSGuillaume La Roque <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1258eef8bcaSGuillaume La Roque <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1268eef8bcaSGuillaume La Roque }; 1278eef8bcaSGuillaume La Roque 1288eef8bcaSGuillaume La Roque map1 { 1298eef8bcaSGuillaume La Roque trip = <&cpu_hot>; 1308eef8bcaSGuillaume La Roque cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1318eef8bcaSGuillaume La Roque <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1328eef8bcaSGuillaume La Roque <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1338eef8bcaSGuillaume La Roque <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1348eef8bcaSGuillaume La Roque }; 1358eef8bcaSGuillaume La Roque }; 1368eef8bcaSGuillaume La Roque}; 137