19c8c52f7SJianxin Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29c8c52f7SJianxin Pan/* 39c8c52f7SJianxin Pan * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 49c8c52f7SJianxin Pan */ 59c8c52f7SJianxin Pan 69baf7d6bSNeil Armstrong#include <dt-bindings/phy/phy.h> 79c8c52f7SJianxin Pan#include <dt-bindings/gpio/gpio.h> 8965c827aSJerome Brunet#include <dt-bindings/clock/g12a-clkc.h> 9820873cfSNeil Armstrong#include <dt-bindings/clock/g12a-aoclkc.h> 109c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/irq.h> 119c8c52f7SJianxin Pan#include <dt-bindings/interrupt-controller/arm-gic.h> 129baf7d6bSNeil Armstrong#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 139c8c52f7SJianxin Pan 149c8c52f7SJianxin Pan/ { 159c8c52f7SJianxin Pan compatible = "amlogic,g12a"; 169c8c52f7SJianxin Pan 179c8c52f7SJianxin Pan interrupt-parent = <&gic>; 189c8c52f7SJianxin Pan #address-cells = <2>; 199c8c52f7SJianxin Pan #size-cells = <2>; 209c8c52f7SJianxin Pan 219c8c52f7SJianxin Pan cpus { 229c8c52f7SJianxin Pan #address-cells = <0x2>; 239c8c52f7SJianxin Pan #size-cells = <0x0>; 249c8c52f7SJianxin Pan 259c8c52f7SJianxin Pan cpu0: cpu@0 { 269c8c52f7SJianxin Pan device_type = "cpu"; 2731af04cdSRob Herring compatible = "arm,cortex-a53"; 289c8c52f7SJianxin Pan reg = <0x0 0x0>; 299c8c52f7SJianxin Pan enable-method = "psci"; 309c8c52f7SJianxin Pan next-level-cache = <&l2>; 319c8c52f7SJianxin Pan }; 329c8c52f7SJianxin Pan 339c8c52f7SJianxin Pan cpu1: cpu@1 { 349c8c52f7SJianxin Pan device_type = "cpu"; 3531af04cdSRob Herring compatible = "arm,cortex-a53"; 369c8c52f7SJianxin Pan reg = <0x0 0x1>; 379c8c52f7SJianxin Pan enable-method = "psci"; 389c8c52f7SJianxin Pan next-level-cache = <&l2>; 399c8c52f7SJianxin Pan }; 409c8c52f7SJianxin Pan 419c8c52f7SJianxin Pan cpu2: cpu@2 { 429c8c52f7SJianxin Pan device_type = "cpu"; 4331af04cdSRob Herring compatible = "arm,cortex-a53"; 449c8c52f7SJianxin Pan reg = <0x0 0x2>; 459c8c52f7SJianxin Pan enable-method = "psci"; 469c8c52f7SJianxin Pan next-level-cache = <&l2>; 479c8c52f7SJianxin Pan }; 489c8c52f7SJianxin Pan 499c8c52f7SJianxin Pan cpu3: cpu@3 { 509c8c52f7SJianxin Pan device_type = "cpu"; 5131af04cdSRob Herring compatible = "arm,cortex-a53"; 529c8c52f7SJianxin Pan reg = <0x0 0x3>; 539c8c52f7SJianxin Pan enable-method = "psci"; 549c8c52f7SJianxin Pan next-level-cache = <&l2>; 559c8c52f7SJianxin Pan }; 569c8c52f7SJianxin Pan 579c8c52f7SJianxin Pan l2: l2-cache0 { 589c8c52f7SJianxin Pan compatible = "cache"; 599c8c52f7SJianxin Pan }; 609c8c52f7SJianxin Pan }; 619c8c52f7SJianxin Pan 62965c827aSJerome Brunet efuse: efuse { 63965c827aSJerome Brunet compatible = "amlogic,meson-gxbb-efuse"; 64965c827aSJerome Brunet clocks = <&clkc CLKID_EFUSE>; 65965c827aSJerome Brunet #address-cells = <1>; 66965c827aSJerome Brunet #size-cells = <1>; 67965c827aSJerome Brunet read-only; 68965c827aSJerome Brunet }; 69965c827aSJerome Brunet 709c8c52f7SJianxin Pan psci { 719c8c52f7SJianxin Pan compatible = "arm,psci-1.0"; 729c8c52f7SJianxin Pan method = "smc"; 739c8c52f7SJianxin Pan }; 749c8c52f7SJianxin Pan 759c8c52f7SJianxin Pan reserved-memory { 769c8c52f7SJianxin Pan #address-cells = <2>; 779c8c52f7SJianxin Pan #size-cells = <2>; 789c8c52f7SJianxin Pan ranges; 799c8c52f7SJianxin Pan 809c8c52f7SJianxin Pan /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 819c8c52f7SJianxin Pan secmon_reserved: secmon@5000000 { 829c8c52f7SJianxin Pan reg = <0x0 0x05000000 0x0 0x300000>; 839c8c52f7SJianxin Pan no-map; 849c8c52f7SJianxin Pan }; 85e2cffeb3SNeil Armstrong 86e2cffeb3SNeil Armstrong linux,cma { 87e2cffeb3SNeil Armstrong compatible = "shared-dma-pool"; 88e2cffeb3SNeil Armstrong reusable; 89e2cffeb3SNeil Armstrong size = <0x0 0x10000000>; 90e2cffeb3SNeil Armstrong alignment = <0x0 0x400000>; 91e2cffeb3SNeil Armstrong linux,cma-default; 92e2cffeb3SNeil Armstrong }; 939c8c52f7SJianxin Pan }; 949c8c52f7SJianxin Pan 95bd395152SJerome Brunet sm: secure-monitor { 96bd395152SJerome Brunet compatible = "amlogic,meson-gxbb-sm"; 97bd395152SJerome Brunet }; 98bd395152SJerome Brunet 999c8c52f7SJianxin Pan soc { 1009c8c52f7SJianxin Pan compatible = "simple-bus"; 1019c8c52f7SJianxin Pan #address-cells = <2>; 1029c8c52f7SJianxin Pan #size-cells = <2>; 1039c8c52f7SJianxin Pan ranges; 1049c8c52f7SJianxin Pan 105503f5fedSJerome Brunet apb: bus@ff600000 { 1069c8c52f7SJianxin Pan compatible = "simple-bus"; 107503f5fedSJerome Brunet reg = <0x0 0xff600000 0x0 0x200000>; 1089c8c52f7SJianxin Pan #address-cells = <2>; 1099c8c52f7SJianxin Pan #size-cells = <2>; 110503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111503f5fedSJerome Brunet 112503f5fedSJerome Brunet periphs: bus@34400 { 113503f5fedSJerome Brunet compatible = "simple-bus"; 114503f5fedSJerome Brunet reg = <0x0 0x34400 0x0 0x400>; 115503f5fedSJerome Brunet #address-cells = <2>; 116503f5fedSJerome Brunet #size-cells = <2>; 117503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 11811a7bea1SJerome Brunet 11911a7bea1SJerome Brunet periphs_pinctrl: pinctrl@40 { 12011a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-periphs-pinctrl"; 12111a7bea1SJerome Brunet #address-cells = <2>; 12211a7bea1SJerome Brunet #size-cells = <2>; 12311a7bea1SJerome Brunet ranges; 12411a7bea1SJerome Brunet 12511a7bea1SJerome Brunet gpio: bank@40 { 12611a7bea1SJerome Brunet reg = <0x0 0x40 0x0 0x4c>, 12711a7bea1SJerome Brunet <0x0 0xe8 0x0 0x18>, 12811a7bea1SJerome Brunet <0x0 0x120 0x0 0x18>, 12911a7bea1SJerome Brunet <0x0 0x2c0 0x0 0x40>, 13011a7bea1SJerome Brunet <0x0 0x340 0x0 0x1c>; 13111a7bea1SJerome Brunet reg-names = "gpio", 13211a7bea1SJerome Brunet "pull", 13311a7bea1SJerome Brunet "pull-enable", 13411a7bea1SJerome Brunet "mux", 13511a7bea1SJerome Brunet "ds"; 13611a7bea1SJerome Brunet gpio-controller; 13711a7bea1SJerome Brunet #gpio-cells = <2>; 13811a7bea1SJerome Brunet gpio-ranges = <&periphs_pinctrl 0 0 86>; 13911a7bea1SJerome Brunet }; 140ff4f8b6cSNeil Armstrong 141ff4f8b6cSNeil Armstrong uart_a_pins: uart-a { 142ff4f8b6cSNeil Armstrong mux { 143ff4f8b6cSNeil Armstrong groups = "uart_a_tx", 144ff4f8b6cSNeil Armstrong "uart_a_rx"; 145ff4f8b6cSNeil Armstrong function = "uart_a"; 146ff4f8b6cSNeil Armstrong bias-disable; 147ff4f8b6cSNeil Armstrong }; 148ff4f8b6cSNeil Armstrong }; 149ff4f8b6cSNeil Armstrong 150ff4f8b6cSNeil Armstrong uart_a_cts_rts_pins: uart-a-cts-rts { 151ff4f8b6cSNeil Armstrong mux { 152ff4f8b6cSNeil Armstrong groups = "uart_a_cts", 153ff4f8b6cSNeil Armstrong "uart_a_rts"; 154ff4f8b6cSNeil Armstrong function = "uart_a"; 155ff4f8b6cSNeil Armstrong bias-disable; 156ff4f8b6cSNeil Armstrong }; 157ff4f8b6cSNeil Armstrong }; 158ff4f8b6cSNeil Armstrong 159ff4f8b6cSNeil Armstrong uart_b_pins: uart-b { 160ff4f8b6cSNeil Armstrong mux { 161ff4f8b6cSNeil Armstrong groups = "uart_b_tx", 162ff4f8b6cSNeil Armstrong "uart_b_rx"; 163ff4f8b6cSNeil Armstrong function = "uart_b"; 164ff4f8b6cSNeil Armstrong bias-disable; 165ff4f8b6cSNeil Armstrong }; 166ff4f8b6cSNeil Armstrong }; 167ff4f8b6cSNeil Armstrong 168ff4f8b6cSNeil Armstrong uart_c_pins: uart-c { 169ff4f8b6cSNeil Armstrong mux { 170ff4f8b6cSNeil Armstrong groups = "uart_c_tx", 171ff4f8b6cSNeil Armstrong "uart_c_rx"; 172ff4f8b6cSNeil Armstrong function = "uart_c"; 173ff4f8b6cSNeil Armstrong bias-disable; 174ff4f8b6cSNeil Armstrong }; 175ff4f8b6cSNeil Armstrong }; 176ff4f8b6cSNeil Armstrong 177ff4f8b6cSNeil Armstrong uart_c_cts_rts_pins: uart-c-cts-rts { 178ff4f8b6cSNeil Armstrong mux { 179ff4f8b6cSNeil Armstrong groups = "uart_c_cts", 180ff4f8b6cSNeil Armstrong "uart_c_rts"; 181ff4f8b6cSNeil Armstrong function = "uart_c"; 182ff4f8b6cSNeil Armstrong bias-disable; 183ff4f8b6cSNeil Armstrong }; 184ff4f8b6cSNeil Armstrong }; 18511a7bea1SJerome Brunet }; 1869c8c52f7SJianxin Pan }; 1879c8c52f7SJianxin Pan 1889baf7d6bSNeil Armstrong usb2_phy0: phy@36000 { 1899baf7d6bSNeil Armstrong compatible = "amlogic,g12a-usb2-phy"; 1909baf7d6bSNeil Armstrong reg = <0x0 0x36000 0x0 0x2000>; 1919baf7d6bSNeil Armstrong clocks = <&xtal>; 1929baf7d6bSNeil Armstrong clock-names = "xtal"; 1939baf7d6bSNeil Armstrong resets = <&reset RESET_USB_PHY20>; 1949baf7d6bSNeil Armstrong reset-names = "phy"; 1959baf7d6bSNeil Armstrong #phy-cells = <0>; 1969baf7d6bSNeil Armstrong }; 1979baf7d6bSNeil Armstrong 1989baf7d6bSNeil Armstrong usb2_phy1: phy@3a000 { 1999baf7d6bSNeil Armstrong compatible = "amlogic,g12a-usb2-phy"; 2009baf7d6bSNeil Armstrong reg = <0x0 0x3a000 0x0 0x2000>; 2019baf7d6bSNeil Armstrong clocks = <&xtal>; 2029baf7d6bSNeil Armstrong clock-names = "xtal"; 2039baf7d6bSNeil Armstrong resets = <&reset RESET_USB_PHY21>; 2049baf7d6bSNeil Armstrong reset-names = "phy"; 2059baf7d6bSNeil Armstrong #phy-cells = <0>; 2069baf7d6bSNeil Armstrong }; 2079baf7d6bSNeil Armstrong 208503f5fedSJerome Brunet hiu: bus@3c000 { 2099c8c52f7SJianxin Pan compatible = "simple-bus"; 210503f5fedSJerome Brunet reg = <0x0 0x3c000 0x0 0x1400>; 2119c8c52f7SJianxin Pan #address-cells = <2>; 2129c8c52f7SJianxin Pan #size-cells = <2>; 213503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 214785fb434SJerome Brunet 215785fb434SJerome Brunet hhi: system-controller@0 { 216785fb434SJerome Brunet compatible = "amlogic,meson-gx-hhi-sysctrl", 217785fb434SJerome Brunet "simple-mfd", "syscon"; 218785fb434SJerome Brunet reg = <0 0 0 0x400>; 219785fb434SJerome Brunet 220785fb434SJerome Brunet clkc: clock-controller { 221785fb434SJerome Brunet compatible = "amlogic,g12a-clkc"; 222785fb434SJerome Brunet #clock-cells = <1>; 223785fb434SJerome Brunet clocks = <&xtal>; 224785fb434SJerome Brunet clock-names = "xtal"; 225785fb434SJerome Brunet }; 226785fb434SJerome Brunet }; 227503f5fedSJerome Brunet }; 2289baf7d6bSNeil Armstrong 2299baf7d6bSNeil Armstrong usb3_pcie_phy: phy@46000 { 2309baf7d6bSNeil Armstrong compatible = "amlogic,g12a-usb3-pcie-phy"; 2319baf7d6bSNeil Armstrong reg = <0x0 0x46000 0x0 0x2000>; 2329baf7d6bSNeil Armstrong clocks = <&clkc CLKID_PCIE_PLL>; 2339baf7d6bSNeil Armstrong clock-names = "ref_clk"; 2349baf7d6bSNeil Armstrong resets = <&reset RESET_PCIE_PHY>; 2359baf7d6bSNeil Armstrong reset-names = "phy"; 2369baf7d6bSNeil Armstrong assigned-clocks = <&clkc CLKID_PCIE_PLL>; 2379baf7d6bSNeil Armstrong assigned-clock-rates = <100000000>; 2389baf7d6bSNeil Armstrong #phy-cells = <1>; 2399baf7d6bSNeil Armstrong }; 2409c8c52f7SJianxin Pan }; 2419c8c52f7SJianxin Pan 2429c8c52f7SJianxin Pan aobus: bus@ff800000 { 2439c8c52f7SJianxin Pan compatible = "simple-bus"; 2449c8c52f7SJianxin Pan reg = <0x0 0xff800000 0x0 0x100000>; 2459c8c52f7SJianxin Pan #address-cells = <2>; 2469c8c52f7SJianxin Pan #size-cells = <2>; 2479c8c52f7SJianxin Pan ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 2489c8c52f7SJianxin Pan 249b019f4a4SNeil Armstrong rti: sys-ctrl@0 { 250b019f4a4SNeil Armstrong compatible = "amlogic,meson-gx-ao-sysctrl", 251b019f4a4SNeil Armstrong "simple-mfd", "syscon"; 252b019f4a4SNeil Armstrong reg = <0x0 0x0 0x0 0x100>; 253b019f4a4SNeil Armstrong #address-cells = <2>; 254b019f4a4SNeil Armstrong #size-cells = <2>; 255b019f4a4SNeil Armstrong ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 256b019f4a4SNeil Armstrong 257b019f4a4SNeil Armstrong clkc_AO: clock-controller { 258b019f4a4SNeil Armstrong compatible = "amlogic,meson-g12a-aoclkc"; 259b019f4a4SNeil Armstrong #clock-cells = <1>; 260b019f4a4SNeil Armstrong #reset-cells = <1>; 261b019f4a4SNeil Armstrong clocks = <&xtal>, <&clkc CLKID_CLK81>; 262b019f4a4SNeil Armstrong clock-names = "xtal", "mpeg-clk"; 263b019f4a4SNeil Armstrong }; 26411a7bea1SJerome Brunet 26511a7bea1SJerome Brunet ao_pinctrl: pinctrl@14 { 26611a7bea1SJerome Brunet compatible = "amlogic,meson-g12a-aobus-pinctrl"; 26711a7bea1SJerome Brunet #address-cells = <2>; 26811a7bea1SJerome Brunet #size-cells = <2>; 26911a7bea1SJerome Brunet ranges; 27011a7bea1SJerome Brunet 27111a7bea1SJerome Brunet gpio_ao: bank@14 { 27211a7bea1SJerome Brunet reg = <0x0 0x14 0x0 0x8>, 27311a7bea1SJerome Brunet <0x0 0x1c 0x0 0x8>, 27411a7bea1SJerome Brunet <0x0 0x24 0x0 0x14>; 27511a7bea1SJerome Brunet reg-names = "mux", 27611a7bea1SJerome Brunet "ds", 27711a7bea1SJerome Brunet "gpio"; 27811a7bea1SJerome Brunet gpio-controller; 27911a7bea1SJerome Brunet #gpio-cells = <2>; 28011a7bea1SJerome Brunet gpio-ranges = <&ao_pinctrl 0 0 15>; 28111a7bea1SJerome Brunet }; 282e92546c2SJerome Brunet 283e92546c2SJerome Brunet uart_ao_a_pins: uart-a-ao { 284e92546c2SJerome Brunet mux { 285e92546c2SJerome Brunet groups = "uart_ao_a_tx", 286e92546c2SJerome Brunet "uart_ao_a_rx"; 287e92546c2SJerome Brunet function = "uart_ao_a"; 288e92546c2SJerome Brunet bias-disable; 289e92546c2SJerome Brunet }; 290e92546c2SJerome Brunet }; 291e92546c2SJerome Brunet 292e92546c2SJerome Brunet uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 293e92546c2SJerome Brunet mux { 294e92546c2SJerome Brunet groups = "uart_ao_a_cts", 295e92546c2SJerome Brunet "uart_ao_a_rts"; 296e92546c2SJerome Brunet function = "uart_ao_a"; 297e92546c2SJerome Brunet bias-disable; 298e92546c2SJerome Brunet }; 299e92546c2SJerome Brunet }; 30011a7bea1SJerome Brunet }; 301b019f4a4SNeil Armstrong }; 302b019f4a4SNeil Armstrong 3030fa724c5SNeil Armstrong sec_AO: ao-secure@140 { 3040fa724c5SNeil Armstrong compatible = "amlogic,meson-gx-ao-secure", "syscon"; 3050fa724c5SNeil Armstrong reg = <0x0 0x140 0x0 0x140>; 3060fa724c5SNeil Armstrong amlogic,has-chip-id; 3070fa724c5SNeil Armstrong }; 3080fa724c5SNeil Armstrong 3099c8c52f7SJianxin Pan uart_AO: serial@3000 { 310503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 311503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 3129c8c52f7SJianxin Pan reg = <0x0 0x3000 0x0 0x18>; 3139c8c52f7SJianxin Pan interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 3149c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 3159c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 3169c8c52f7SJianxin Pan status = "disabled"; 3179c8c52f7SJianxin Pan }; 3189c8c52f7SJianxin Pan 3199c8c52f7SJianxin Pan uart_AO_B: serial@4000 { 320503f5fedSJerome Brunet compatible = "amlogic,meson-gx-uart", 321503f5fedSJerome Brunet "amlogic,meson-ao-uart"; 3229c8c52f7SJianxin Pan reg = <0x0 0x4000 0x0 0x18>; 3239c8c52f7SJianxin Pan interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 3249c8c52f7SJianxin Pan clocks = <&xtal>, <&xtal>, <&xtal>; 3259c8c52f7SJianxin Pan clock-names = "xtal", "pclk", "baud"; 3269c8c52f7SJianxin Pan status = "disabled"; 3279c8c52f7SJianxin Pan }; 328820873cfSNeil Armstrong 329820873cfSNeil Armstrong saradc: adc@9000 { 330820873cfSNeil Armstrong compatible = "amlogic,meson-g12a-saradc", 331820873cfSNeil Armstrong "amlogic,meson-saradc"; 332820873cfSNeil Armstrong reg = <0x0 0x9000 0x0 0x48>; 333820873cfSNeil Armstrong #io-channel-cells = <1>; 334820873cfSNeil Armstrong interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 335820873cfSNeil Armstrong clocks = <&xtal>, 336820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC>, 337820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 338820873cfSNeil Armstrong <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 339820873cfSNeil Armstrong clock-names = "clkin", "core", "adc_clk", "adc_sel"; 340820873cfSNeil Armstrong status = "disabled"; 341820873cfSNeil Armstrong }; 3429c8c52f7SJianxin Pan }; 3439c8c52f7SJianxin Pan 3449c8c52f7SJianxin Pan gic: interrupt-controller@ffc01000 { 3459c8c52f7SJianxin Pan compatible = "arm,gic-400"; 3469c8c52f7SJianxin Pan reg = <0x0 0xffc01000 0 0x1000>, 3479c8c52f7SJianxin Pan <0x0 0xffc02000 0 0x2000>, 3489c8c52f7SJianxin Pan <0x0 0xffc04000 0 0x2000>, 3499c8c52f7SJianxin Pan <0x0 0xffc06000 0 0x2000>; 3509c8c52f7SJianxin Pan interrupt-controller; 3519c8c52f7SJianxin Pan interrupts = <GIC_PPI 9 3529c8c52f7SJianxin Pan (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 3539c8c52f7SJianxin Pan #interrupt-cells = <3>; 3549c8c52f7SJianxin Pan #address-cells = <0>; 3559c8c52f7SJianxin Pan }; 3569c8c52f7SJianxin Pan 3579c8c52f7SJianxin Pan cbus: bus@ffd00000 { 3589c8c52f7SJianxin Pan compatible = "simple-bus"; 359503f5fedSJerome Brunet reg = <0x0 0xffd00000 0x0 0x100000>; 3609c8c52f7SJianxin Pan #address-cells = <2>; 3619c8c52f7SJianxin Pan #size-cells = <2>; 362503f5fedSJerome Brunet ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 3639c8c52f7SJianxin Pan 3647ab41c47SJerome Brunet reset: reset-controller@1004 { 3657ab41c47SJerome Brunet compatible = "amlogic,meson-g12a-reset", 3667ab41c47SJerome Brunet "amlogic,meson-axg-reset"; 3677ab41c47SJerome Brunet reg = <0x0 0x1004 0x0 0x9c>; 3687ab41c47SJerome Brunet #reset-cells = <1>; 3697ab41c47SJerome Brunet }; 3707ab41c47SJerome Brunet 37160d4fdb8SJerome Brunet clk_msr: clock-measure@18000 { 37260d4fdb8SJerome Brunet compatible = "amlogic,meson-g12a-clk-measure"; 37360d4fdb8SJerome Brunet reg = <0x0 0x18000 0x0 0x10>; 37460d4fdb8SJerome Brunet }; 375ff4f8b6cSNeil Armstrong 376ff4f8b6cSNeil Armstrong uart_C: serial@22000 { 377ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 378ff4f8b6cSNeil Armstrong reg = <0x0 0x22000 0x0 0x18>; 379ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 380ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 381ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 382ff4f8b6cSNeil Armstrong status = "disabled"; 383ff4f8b6cSNeil Armstrong }; 384ff4f8b6cSNeil Armstrong 385ff4f8b6cSNeil Armstrong uart_B: serial@23000 { 386ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 387ff4f8b6cSNeil Armstrong reg = <0x0 0x23000 0x0 0x18>; 388ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 389ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 390ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 391ff4f8b6cSNeil Armstrong status = "disabled"; 392ff4f8b6cSNeil Armstrong }; 393ff4f8b6cSNeil Armstrong 394ff4f8b6cSNeil Armstrong uart_A: serial@24000 { 395ff4f8b6cSNeil Armstrong compatible = "amlogic,meson-gx-uart"; 396ff4f8b6cSNeil Armstrong reg = <0x0 0x24000 0x0 0x18>; 397ff4f8b6cSNeil Armstrong interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 398ff4f8b6cSNeil Armstrong clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 399ff4f8b6cSNeil Armstrong clock-names = "xtal", "pclk", "baud"; 400ff4f8b6cSNeil Armstrong status = "disabled"; 401ff4f8b6cSNeil Armstrong }; 4029c8c52f7SJianxin Pan }; 4039baf7d6bSNeil Armstrong 4049baf7d6bSNeil Armstrong usb: usb@ffe09000 { 4059baf7d6bSNeil Armstrong status = "disabled"; 4069baf7d6bSNeil Armstrong compatible = "amlogic,meson-g12a-usb-ctrl"; 4079baf7d6bSNeil Armstrong reg = <0x0 0xffe09000 0x0 0xa0>; 4089baf7d6bSNeil Armstrong interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 4099baf7d6bSNeil Armstrong #address-cells = <2>; 4109baf7d6bSNeil Armstrong #size-cells = <2>; 4119baf7d6bSNeil Armstrong ranges; 4129baf7d6bSNeil Armstrong 4139baf7d6bSNeil Armstrong clocks = <&clkc CLKID_USB>; 4149baf7d6bSNeil Armstrong resets = <&reset RESET_USB>; 4159baf7d6bSNeil Armstrong 4169baf7d6bSNeil Armstrong dr_mode = "otg"; 4179baf7d6bSNeil Armstrong 4189baf7d6bSNeil Armstrong phys = <&usb2_phy0>, <&usb2_phy1>, 4199baf7d6bSNeil Armstrong <&usb3_pcie_phy PHY_TYPE_USB3>; 4209baf7d6bSNeil Armstrong phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 4219baf7d6bSNeil Armstrong 4229baf7d6bSNeil Armstrong dwc2: usb@ff400000 { 4239baf7d6bSNeil Armstrong compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 4249baf7d6bSNeil Armstrong reg = <0x0 0xff400000 0x0 0x40000>; 4259baf7d6bSNeil Armstrong interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 4269baf7d6bSNeil Armstrong clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 4279baf7d6bSNeil Armstrong clock-names = "ddr"; 4289baf7d6bSNeil Armstrong phys = <&usb2_phy1>; 4299baf7d6bSNeil Armstrong dr_mode = "peripheral"; 4309baf7d6bSNeil Armstrong g-rx-fifo-size = <192>; 4319baf7d6bSNeil Armstrong g-np-tx-fifo-size = <128>; 4329baf7d6bSNeil Armstrong g-tx-fifo-size = <128 128 16 16 16>; 4339baf7d6bSNeil Armstrong }; 4349baf7d6bSNeil Armstrong 4359baf7d6bSNeil Armstrong dwc3: usb@ff500000 { 4369baf7d6bSNeil Armstrong compatible = "snps,dwc3"; 4379baf7d6bSNeil Armstrong reg = <0x0 0xff500000 0x0 0x100000>; 4389baf7d6bSNeil Armstrong interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 4399baf7d6bSNeil Armstrong dr_mode = "host"; 4409baf7d6bSNeil Armstrong snps,dis_u2_susphy_quirk; 4419baf7d6bSNeil Armstrong snps,quirk-frame-length-adjustment; 4429baf7d6bSNeil Armstrong }; 4439baf7d6bSNeil Armstrong }; 4442607fd08SNeil Armstrong 4452607fd08SNeil Armstrong mali: gpu@ffe40000 { 4462607fd08SNeil Armstrong compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 4472607fd08SNeil Armstrong reg = <0x0 0xffe40000 0x0 0x40000>; 4482607fd08SNeil Armstrong interrupt-parent = <&gic>; 4492607fd08SNeil Armstrong interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 4502607fd08SNeil Armstrong <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 4512607fd08SNeil Armstrong <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 4522607fd08SNeil Armstrong interrupt-names = "gpu", "mmu", "job"; 4532607fd08SNeil Armstrong clocks = <&clkc CLKID_MALI>; 4542607fd08SNeil Armstrong resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 4552607fd08SNeil Armstrong 4562607fd08SNeil Armstrong /* 4572607fd08SNeil Armstrong * Mali clocking is provided by two identical clock paths 4582607fd08SNeil Armstrong * MALI_0 and MALI_1 muxed to a single clock by a glitch 4592607fd08SNeil Armstrong * free mux to safely change frequency while running. 4602607fd08SNeil Armstrong */ 4612607fd08SNeil Armstrong assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 4622607fd08SNeil Armstrong <&clkc CLKID_MALI_0>, 4632607fd08SNeil Armstrong <&clkc CLKID_MALI>; /* Glitch free mux */ 4642607fd08SNeil Armstrong assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 4652607fd08SNeil Armstrong <0>, /* Do Nothing */ 4662607fd08SNeil Armstrong <&clkc CLKID_MALI_0>; 4672607fd08SNeil Armstrong assigned-clock-rates = <0>, /* Do Nothing */ 4682607fd08SNeil Armstrong <800000000>, 4692607fd08SNeil Armstrong <0>; /* Do Nothing */ 4702607fd08SNeil Armstrong }; 4719c8c52f7SJianxin Pan }; 4729c8c52f7SJianxin Pan 4739c8c52f7SJianxin Pan timer { 4749c8c52f7SJianxin Pan compatible = "arm,armv8-timer"; 4759c8c52f7SJianxin Pan interrupts = <GIC_PPI 13 4769c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 4779c8c52f7SJianxin Pan <GIC_PPI 14 4789c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 4799c8c52f7SJianxin Pan <GIC_PPI 11 4809c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 4819c8c52f7SJianxin Pan <GIC_PPI 10 4829c8c52f7SJianxin Pan (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 4839c8c52f7SJianxin Pan }; 4849c8c52f7SJianxin Pan 4859c8c52f7SJianxin Pan xtal: xtal-clk { 4869c8c52f7SJianxin Pan compatible = "fixed-clock"; 4879c8c52f7SJianxin Pan clock-frequency = <24000000>; 4889c8c52f7SJianxin Pan clock-output-names = "xtal"; 4899c8c52f7SJianxin Pan #clock-cells = <0>; 4909c8c52f7SJianxin Pan }; 4919c8c52f7SJianxin Pan 4929c8c52f7SJianxin Pan}; 493