1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-audio-clkc.h> 10#include <dt-bindings/clock/axg-clkc.h> 11#include <dt-bindings/clock/axg-aoclkc.h> 12#include <dt-bindings/gpio/meson-axg-gpio.h> 13#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 14 15/ { 16 compatible = "amlogic,meson-axg"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 reserved-memory { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 /* 16 MiB reserved for Hardware ROM Firmware */ 28 hwrom_reserved: hwrom@0 { 29 reg = <0x0 0x0 0x0 0x1000000>; 30 no-map; 31 }; 32 33 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 34 secmon_reserved: secmon@5000000 { 35 reg = <0x0 0x05000000 0x0 0x300000>; 36 no-map; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <0x2>; 42 #size-cells = <0x0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 }; 51 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <0x0 0x1>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0x0 0x2>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 reg = <0x0 0x3>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 l2: l2-cache0 { 77 compatible = "cache"; 78 }; 79 }; 80 81 arm-pmu { 82 compatible = "arm,cortex-a53-pmu"; 83 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 102 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 105 }; 106 107 xtal: xtal-clk { 108 compatible = "fixed-clock"; 109 clock-frequency = <24000000>; 110 clock-output-names = "xtal"; 111 #clock-cells = <0>; 112 }; 113 114 ao_alt_xtal: ao_alt_xtal-clk { 115 compatible = "fixed-clock"; 116 clock-frequency = <32000000>; 117 clock-output-names = "ao_alt_xtal"; 118 #clock-cells = <0>; 119 }; 120 121 soc { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 apb: apb@ffe00000 { 128 compatible = "simple-bus"; 129 reg = <0x0 0xffe00000 0x0 0x200000>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 133 134 sd_emmc_b: sd@5000 { 135 compatible = "amlogic,meson-axg-mmc"; 136 reg = <0x0 0x5000 0x0 0x2000>; 137 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 138 status = "disabled"; 139 clocks = <&clkc CLKID_SD_EMMC_B>, 140 <&clkc CLKID_SD_EMMC_B_CLK0>, 141 <&clkc CLKID_FCLK_DIV2>; 142 clock-names = "core", "clkin0", "clkin1"; 143 resets = <&reset RESET_SD_EMMC_B>; 144 }; 145 146 sd_emmc_c: mmc@7000 { 147 compatible = "amlogic,meson-axg-mmc"; 148 reg = <0x0 0x7000 0x0 0x2000>; 149 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 150 status = "disabled"; 151 clocks = <&clkc CLKID_SD_EMMC_C>, 152 <&clkc CLKID_SD_EMMC_C_CLK0>, 153 <&clkc CLKID_FCLK_DIV2>; 154 clock-names = "core", "clkin0", "clkin1"; 155 resets = <&reset RESET_SD_EMMC_C>; 156 }; 157 }; 158 159 audio: bus@ff642000 { 160 compatible = "simple-bus"; 161 reg = <0x0 0xff642000 0x0 0x2000>; 162 #address-cells = <2>; 163 #size-cells = <2>; 164 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 165 166 clkc_audio: clock-controller@0 { 167 compatible = "amlogic,axg-audio-clkc"; 168 reg = <0x0 0x0 0x0 0xb4>; 169 #clock-cells = <1>; 170 171 clocks = <&clkc CLKID_AUDIO>, 172 <&clkc CLKID_MPLL0>, 173 <&clkc CLKID_MPLL1>, 174 <&clkc CLKID_MPLL2>, 175 <&clkc CLKID_MPLL3>, 176 <&clkc CLKID_HIFI_PLL>, 177 <&clkc CLKID_FCLK_DIV3>, 178 <&clkc CLKID_FCLK_DIV4>, 179 <&clkc CLKID_GP0_PLL>; 180 clock-names = "pclk", 181 "mst_in0", 182 "mst_in1", 183 "mst_in2", 184 "mst_in3", 185 "mst_in4", 186 "mst_in5", 187 "mst_in6", 188 "mst_in7"; 189 190 resets = <&reset RESET_AUDIO>; 191 }; 192 193 arb: reset-controller@280 { 194 compatible = "amlogic,meson-axg-audio-arb"; 195 reg = <0x0 0x280 0x0 0x4>; 196 #reset-cells = <1>; 197 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 198 }; 199 200 tdmin_a: audio-controller@300 { 201 compatible = "amlogic,axg-tdmin"; 202 reg = <0x0 0x300 0x0 0x40>; 203 sound-name-prefix = "TDMIN_A"; 204 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 205 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 206 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 207 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 208 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 209 clock-names = "pclk", "sclk", "sclk_sel", 210 "lrclk", "lrclk_sel"; 211 status = "disabled"; 212 }; 213 214 tdmin_b: audio-controller@340 { 215 compatible = "amlogic,axg-tdmin"; 216 reg = <0x0 0x340 0x0 0x40>; 217 sound-name-prefix = "TDMIN_B"; 218 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 219 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 220 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 221 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 222 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 223 clock-names = "pclk", "sclk", "sclk_sel", 224 "lrclk", "lrclk_sel"; 225 status = "disabled"; 226 }; 227 228 tdmin_c: audio-controller@380 { 229 compatible = "amlogic,axg-tdmin"; 230 reg = <0x0 0x380 0x0 0x40>; 231 sound-name-prefix = "TDMIN_C"; 232 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 233 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 234 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 235 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 236 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 237 clock-names = "pclk", "sclk", "sclk_sel", 238 "lrclk", "lrclk_sel"; 239 status = "disabled"; 240 }; 241 242 tdmin_lb: audio-controller@3c0 { 243 compatible = "amlogic,axg-tdmin"; 244 reg = <0x0 0x3c0 0x0 0x40>; 245 sound-name-prefix = "TDMIN_LB"; 246 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 247 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 248 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 249 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 250 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 251 clock-names = "pclk", "sclk", "sclk_sel", 252 "lrclk", "lrclk_sel"; 253 status = "disabled"; 254 }; 255 256 spdifout: audio-controller@480 { 257 compatible = "amlogic,axg-spdifout"; 258 reg = <0x0 0x480 0x0 0x50>; 259 #sound-dai-cells = <0>; 260 sound-name-prefix = "SPDIFOUT"; 261 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 262 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 263 clock-names = "pclk", "mclk"; 264 status = "disabled"; 265 }; 266 267 tdmout_a: audio-controller@500 { 268 compatible = "amlogic,axg-tdmout"; 269 reg = <0x0 0x500 0x0 0x40>; 270 sound-name-prefix = "TDMOUT_A"; 271 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 272 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 273 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 274 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 275 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 276 clock-names = "pclk", "sclk", "sclk_sel", 277 "lrclk", "lrclk_sel"; 278 status = "disabled"; 279 }; 280 281 tdmout_b: audio-controller@540 { 282 compatible = "amlogic,axg-tdmout"; 283 reg = <0x0 0x540 0x0 0x40>; 284 sound-name-prefix = "TDMOUT_B"; 285 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 286 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 287 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 288 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 289 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 290 clock-names = "pclk", "sclk", "sclk_sel", 291 "lrclk", "lrclk_sel"; 292 status = "disabled"; 293 }; 294 295 tdmout_c: audio-controller@580 { 296 compatible = "amlogic,axg-tdmout"; 297 reg = <0x0 0x580 0x0 0x40>; 298 sound-name-prefix = "TDMOUT_C"; 299 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 300 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 301 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 302 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 303 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 304 clock-names = "pclk", "sclk", "sclk_sel", 305 "lrclk", "lrclk_sel"; 306 status = "disabled"; 307 }; 308 }; 309 310 cbus: bus@ffd00000 { 311 compatible = "simple-bus"; 312 reg = <0x0 0xffd00000 0x0 0x25000>; 313 #address-cells = <2>; 314 #size-cells = <2>; 315 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 316 317 gpio_intc: interrupt-controller@f080 { 318 compatible = "amlogic,meson-gpio-intc"; 319 reg = <0x0 0xf080 0x0 0x10>; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 323 status = "disabled"; 324 }; 325 326 pwm_ab: pwm@1b000 { 327 compatible = "amlogic,meson-axg-ee-pwm"; 328 reg = <0x0 0x1b000 0x0 0x20>; 329 #pwm-cells = <3>; 330 status = "disabled"; 331 }; 332 333 pwm_cd: pwm@1a000 { 334 compatible = "amlogic,meson-axg-ee-pwm"; 335 reg = <0x0 0x1a000 0x0 0x20>; 336 #pwm-cells = <3>; 337 status = "disabled"; 338 }; 339 340 reset: reset-controller@1004 { 341 compatible = "amlogic,meson-axg-reset"; 342 reg = <0x0 0x01004 0x0 0x9c>; 343 #reset-cells = <1>; 344 }; 345 346 spicc0: spi@13000 { 347 compatible = "amlogic,meson-axg-spicc"; 348 reg = <0x0 0x13000 0x0 0x3c>; 349 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&clkc CLKID_SPICC0>; 351 clock-names = "core"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 spicc1: spi@15000 { 358 compatible = "amlogic,meson-axg-spicc"; 359 reg = <0x0 0x15000 0x0 0x3c>; 360 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clkc CLKID_SPICC1>; 362 clock-names = "core"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 status = "disabled"; 366 }; 367 368 i2c0: i2c@1f000 { 369 compatible = "amlogic,meson-axg-i2c"; 370 reg = <0x0 0x1f000 0x0 0x20>; 371 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 372 clocks = <&clkc CLKID_I2C>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 i2c1: i2c@1e000 { 379 compatible = "amlogic,meson-axg-i2c"; 380 reg = <0x0 0x1e000 0x0 0x20>; 381 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 382 clocks = <&clkc CLKID_I2C>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 388 i2c2: i2c@1d000 { 389 compatible = "amlogic,meson-axg-i2c"; 390 reg = <0x0 0x1d000 0x0 0x20>; 391 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 392 clocks = <&clkc CLKID_I2C>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 status = "disabled"; 396 }; 397 398 i2c3: i2c@1c000 { 399 compatible = "amlogic,meson-axg-i2c"; 400 reg = <0x0 0x1c000 0x0 0x20>; 401 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 402 clocks = <&clkc CLKID_I2C>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 uart_A: serial@24000 { 409 compatible = "amlogic,meson-gx-uart"; 410 reg = <0x0 0x24000 0x0 0x18>; 411 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 412 status = "disabled"; 413 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 414 clock-names = "xtal", "pclk", "baud"; 415 }; 416 417 uart_B: serial@23000 { 418 compatible = "amlogic,meson-gx-uart"; 419 reg = <0x0 0x23000 0x0 0x18>; 420 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 421 status = "disabled"; 422 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 423 clock-names = "xtal", "pclk", "baud"; 424 }; 425 }; 426 427 ethmac: ethernet@ff3f0000 { 428 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 429 reg = <0x0 0xff3f0000 0x0 0x10000 430 0x0 0xff634540 0x0 0x8>; 431 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 432 interrupt-names = "macirq"; 433 clocks = <&clkc CLKID_ETH>, 434 <&clkc CLKID_FCLK_DIV2>, 435 <&clkc CLKID_MPLL2>; 436 clock-names = "stmmaceth", "clkin0", "clkin1"; 437 status = "disabled"; 438 }; 439 440 gic: interrupt-controller@ffc01000 { 441 compatible = "arm,gic-400"; 442 reg = <0x0 0xffc01000 0 0x1000>, 443 <0x0 0xffc02000 0 0x2000>, 444 <0x0 0xffc04000 0 0x2000>, 445 <0x0 0xffc06000 0 0x2000>; 446 interrupt-controller; 447 interrupts = <GIC_PPI 9 448 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 449 #interrupt-cells = <3>; 450 #address-cells = <0>; 451 }; 452 453 hiubus: bus@ff63c000 { 454 compatible = "simple-bus"; 455 reg = <0x0 0xff63c000 0x0 0x1c00>; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 459 460 sysctrl: system-controller@0 { 461 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 462 reg = <0 0 0 0x400>; 463 464 clkc: clock-controller { 465 compatible = "amlogic,axg-clkc"; 466 #clock-cells = <1>; 467 }; 468 }; 469 }; 470 471 mailbox: mailbox@ff63dc00 { 472 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 473 reg = <0 0xff63dc00 0 0x400>; 474 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 477 #mbox-cells = <1>; 478 }; 479 480 periphs: periphs@ff634000 { 481 compatible = "simple-bus"; 482 reg = <0x0 0xff634000 0x0 0x2000>; 483 #address-cells = <2>; 484 #size-cells = <2>; 485 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 486 487 hwrng: rng { 488 compatible = "amlogic,meson-rng"; 489 reg = <0x0 0x18 0x0 0x4>; 490 clocks = <&clkc CLKID_RNG0>; 491 clock-names = "core"; 492 }; 493 494 pinctrl_periphs: pinctrl@480 { 495 compatible = "amlogic,meson-axg-periphs-pinctrl"; 496 #address-cells = <2>; 497 #size-cells = <2>; 498 ranges; 499 500 gpio: bank@480 { 501 reg = <0x0 0x00480 0x0 0x40>, 502 <0x0 0x004e8 0x0 0x14>, 503 <0x0 0x00520 0x0 0x14>, 504 <0x0 0x00430 0x0 0x3c>; 505 reg-names = "mux", "pull", "pull-enable", "gpio"; 506 gpio-controller; 507 #gpio-cells = <2>; 508 gpio-ranges = <&pinctrl_periphs 0 0 86>; 509 }; 510 511 emmc_pins: emmc { 512 mux { 513 groups = "emmc_nand_d0", 514 "emmc_nand_d1", 515 "emmc_nand_d2", 516 "emmc_nand_d3", 517 "emmc_nand_d4", 518 "emmc_nand_d5", 519 "emmc_nand_d6", 520 "emmc_nand_d7", 521 "emmc_clk", 522 "emmc_cmd", 523 "emmc_ds"; 524 function = "emmc"; 525 }; 526 }; 527 528 emmc_clk_gate_pins: emmc_clk_gate { 529 mux { 530 groups = "BOOT_8"; 531 function = "gpio_periphs"; 532 }; 533 cfg-pull-down { 534 pins = "BOOT_8"; 535 bias-pull-down; 536 }; 537 }; 538 539 sdio_pins: sdio { 540 mux { 541 groups = "sdio_d0", 542 "sdio_d1", 543 "sdio_d2", 544 "sdio_d3", 545 "sdio_cmd", 546 "sdio_clk"; 547 function = "sdio"; 548 }; 549 }; 550 551 sdio_clk_gate_pins: sdio_clk_gate { 552 mux { 553 groups = "GPIOX_4"; 554 function = "gpio_periphs"; 555 }; 556 cfg-pull-down { 557 pins = "GPIOX_4"; 558 bias-pull-down; 559 }; 560 }; 561 562 eth_rmii_x_pins: eth-x-rmii { 563 mux { 564 groups = "eth_mdio_x", 565 "eth_mdc_x", 566 "eth_rgmii_rx_clk_x", 567 "eth_rx_dv_x", 568 "eth_rxd0_x", 569 "eth_rxd1_x", 570 "eth_txen_x", 571 "eth_txd0_x", 572 "eth_txd1_x"; 573 function = "eth"; 574 }; 575 }; 576 577 eth_rmii_y_pins: eth-y-rmii { 578 mux { 579 groups = "eth_mdio_y", 580 "eth_mdc_y", 581 "eth_rgmii_rx_clk_y", 582 "eth_rx_dv_y", 583 "eth_rxd0_y", 584 "eth_rxd1_y", 585 "eth_txen_y", 586 "eth_txd0_y", 587 "eth_txd1_y"; 588 function = "eth"; 589 }; 590 }; 591 592 eth_rgmii_x_pins: eth-x-rgmii { 593 mux { 594 groups = "eth_mdio_x", 595 "eth_mdc_x", 596 "eth_rgmii_rx_clk_x", 597 "eth_rx_dv_x", 598 "eth_rxd0_x", 599 "eth_rxd1_x", 600 "eth_rxd2_rgmii", 601 "eth_rxd3_rgmii", 602 "eth_rgmii_tx_clk", 603 "eth_txen_x", 604 "eth_txd0_x", 605 "eth_txd1_x", 606 "eth_txd2_rgmii", 607 "eth_txd3_rgmii"; 608 function = "eth"; 609 }; 610 }; 611 612 eth_rgmii_y_pins: eth-y-rgmii { 613 mux { 614 groups = "eth_mdio_y", 615 "eth_mdc_y", 616 "eth_rgmii_rx_clk_y", 617 "eth_rx_dv_y", 618 "eth_rxd0_y", 619 "eth_rxd1_y", 620 "eth_rxd2_rgmii", 621 "eth_rxd3_rgmii", 622 "eth_rgmii_tx_clk", 623 "eth_txen_y", 624 "eth_txd0_y", 625 "eth_txd1_y", 626 "eth_txd2_rgmii", 627 "eth_txd3_rgmii"; 628 function = "eth"; 629 }; 630 }; 631 632 pdm_dclk_a14_pins: pdm_dclk_a14 { 633 mux { 634 groups = "pdm_dclk_a14"; 635 function = "pdm"; 636 }; 637 }; 638 639 pdm_dclk_a19_pins: pdm_dclk_a19 { 640 mux { 641 groups = "pdm_dclk_a19"; 642 function = "pdm"; 643 }; 644 }; 645 646 pdm_din0_pins: pdm_din0 { 647 mux { 648 groups = "pdm_din0"; 649 function = "pdm"; 650 }; 651 }; 652 653 pdm_din1_pins: pdm_din1 { 654 mux { 655 groups = "pdm_din1"; 656 function = "pdm"; 657 }; 658 }; 659 660 pdm_din2_pins: pdm_din2 { 661 mux { 662 groups = "pdm_din2"; 663 function = "pdm"; 664 }; 665 }; 666 667 pdm_din3_pins: pdm_din3 { 668 mux { 669 groups = "pdm_din3"; 670 function = "pdm"; 671 }; 672 }; 673 674 pwm_a_a_pins: pwm_a_a { 675 mux { 676 groups = "pwm_a_a"; 677 function = "pwm_a"; 678 }; 679 }; 680 681 pwm_a_x18_pins: pwm_a_x18 { 682 mux { 683 groups = "pwm_a_x18"; 684 function = "pwm_a"; 685 }; 686 }; 687 688 pwm_a_x20_pins: pwm_a_x20 { 689 mux { 690 groups = "pwm_a_x20"; 691 function = "pwm_a"; 692 }; 693 }; 694 695 pwm_a_z_pins: pwm_a_z { 696 mux { 697 groups = "pwm_a_z"; 698 function = "pwm_a"; 699 }; 700 }; 701 702 pwm_b_a_pins: pwm_b_a { 703 mux { 704 groups = "pwm_b_a"; 705 function = "pwm_b"; 706 }; 707 }; 708 709 pwm_b_x_pins: pwm_b_x { 710 mux { 711 groups = "pwm_b_x"; 712 function = "pwm_b"; 713 }; 714 }; 715 716 pwm_b_z_pins: pwm_b_z { 717 mux { 718 groups = "pwm_b_z"; 719 function = "pwm_b"; 720 }; 721 }; 722 723 pwm_c_a_pins: pwm_c_a { 724 mux { 725 groups = "pwm_c_a"; 726 function = "pwm_c"; 727 }; 728 }; 729 730 pwm_c_x10_pins: pwm_c_x10 { 731 mux { 732 groups = "pwm_c_x10"; 733 function = "pwm_c"; 734 }; 735 }; 736 737 pwm_c_x17_pins: pwm_c_x17 { 738 mux { 739 groups = "pwm_c_x17"; 740 function = "pwm_c"; 741 }; 742 }; 743 744 pwm_d_x11_pins: pwm_d_x11 { 745 mux { 746 groups = "pwm_d_x11"; 747 function = "pwm_d"; 748 }; 749 }; 750 751 pwm_d_x16_pins: pwm_d_x16 { 752 mux { 753 groups = "pwm_d_x16"; 754 function = "pwm_d"; 755 }; 756 }; 757 758 spdif_in_z_pins: spdif_in_z { 759 mux { 760 groups = "spdif_in_z"; 761 function = "spdif_in"; 762 }; 763 }; 764 765 spdif_in_a1_pins: spdif_in_a1 { 766 mux { 767 groups = "spdif_in_a1"; 768 function = "spdif_in"; 769 }; 770 }; 771 772 spdif_in_a7_pins: spdif_in_a7 { 773 mux { 774 groups = "spdif_in_a7"; 775 function = "spdif_in"; 776 }; 777 }; 778 779 spdif_in_a19_pins: spdif_in_a19 { 780 mux { 781 groups = "spdif_in_a19"; 782 function = "spdif_in"; 783 }; 784 }; 785 786 spdif_in_a20_pins: spdif_in_a20 { 787 mux { 788 groups = "spdif_in_a20"; 789 function = "spdif_in"; 790 }; 791 }; 792 793 spdif_out_z_pins: spdif_out_z { 794 mux { 795 groups = "spdif_out_z"; 796 function = "spdif_out"; 797 }; 798 }; 799 800 spdif_out_a1_pins: spdif_out_a1 { 801 mux { 802 groups = "spdif_out_a1"; 803 function = "spdif_out"; 804 }; 805 }; 806 807 spdif_out_a11_pins: spdif_out_a11 { 808 mux { 809 groups = "spdif_out_a11"; 810 function = "spdif_out"; 811 }; 812 }; 813 814 spdif_out_a19_pins: spdif_out_a19 { 815 mux { 816 groups = "spdif_out_a19"; 817 function = "spdif_out"; 818 }; 819 }; 820 821 spdif_out_a20_pins: spdif_out_a20 { 822 mux { 823 groups = "spdif_out_a20"; 824 function = "spdif_out"; 825 }; 826 }; 827 828 spi0_pins: spi0 { 829 mux { 830 groups = "spi0_miso", 831 "spi0_mosi", 832 "spi0_clk"; 833 function = "spi0"; 834 }; 835 }; 836 837 spi0_ss0_pins: spi0_ss0 { 838 mux { 839 groups = "spi0_ss0"; 840 function = "spi0"; 841 }; 842 }; 843 844 spi0_ss1_pins: spi0_ss1 { 845 mux { 846 groups = "spi0_ss1"; 847 function = "spi0"; 848 }; 849 }; 850 851 spi0_ss2_pins: spi0_ss2 { 852 mux { 853 groups = "spi0_ss2"; 854 function = "spi0"; 855 }; 856 }; 857 858 859 spi1_a_pins: spi1_a { 860 mux { 861 groups = "spi1_miso_a", 862 "spi1_mosi_a", 863 "spi1_clk_a"; 864 function = "spi1"; 865 }; 866 }; 867 868 spi1_ss0_a_pins: spi1_ss0_a { 869 mux { 870 groups = "spi1_ss0_a"; 871 function = "spi1"; 872 }; 873 }; 874 875 spi1_ss1_pins: spi1_ss1 { 876 mux { 877 groups = "spi1_ss1"; 878 function = "spi1"; 879 }; 880 }; 881 882 spi1_x_pins: spi1_x { 883 mux { 884 groups = "spi1_miso_x", 885 "spi1_mosi_x", 886 "spi1_clk_x"; 887 function = "spi1"; 888 }; 889 }; 890 891 spi1_ss0_x_pins: spi1_ss0_x { 892 mux { 893 groups = "spi1_ss0_x"; 894 function = "spi1"; 895 }; 896 }; 897 898 i2c0_pins: i2c0 { 899 mux { 900 groups = "i2c0_sck", 901 "i2c0_sda"; 902 function = "i2c0"; 903 }; 904 }; 905 906 i2c1_z_pins: i2c1_z { 907 mux { 908 groups = "i2c1_sck_z", 909 "i2c1_sda_z"; 910 function = "i2c1"; 911 }; 912 }; 913 914 i2c1_x_pins: i2c1_x { 915 mux { 916 groups = "i2c1_sck_x", 917 "i2c1_sda_x"; 918 function = "i2c1"; 919 }; 920 }; 921 922 i2c2_x_pins: i2c2_x { 923 mux { 924 groups = "i2c2_sck_x", 925 "i2c2_sda_x"; 926 function = "i2c2"; 927 }; 928 }; 929 930 i2c2_a_pins: i2c2_a { 931 mux { 932 groups = "i2c2_sck_a", 933 "i2c2_sda_a"; 934 function = "i2c2"; 935 }; 936 }; 937 938 i2c3_a6_pins: i2c3_a6 { 939 mux { 940 groups = "i2c3_sda_a6", 941 "i2c3_sck_a7"; 942 function = "i2c3"; 943 }; 944 }; 945 946 i2c3_a12_pins: i2c3_a12 { 947 mux { 948 groups = "i2c3_sda_a12", 949 "i2c3_sck_a13"; 950 function = "i2c3"; 951 }; 952 }; 953 954 i2c3_a19_pins: i2c3_a19 { 955 mux { 956 groups = "i2c3_sda_a19", 957 "i2c3_sck_a20"; 958 function = "i2c3"; 959 }; 960 }; 961 962 uart_a_pins: uart_a { 963 mux { 964 groups = "uart_tx_a", 965 "uart_rx_a"; 966 function = "uart_a"; 967 }; 968 }; 969 970 uart_a_cts_rts_pins: uart_a_cts_rts { 971 mux { 972 groups = "uart_cts_a", 973 "uart_rts_a"; 974 function = "uart_a"; 975 }; 976 }; 977 978 uart_b_x_pins: uart_b_x { 979 mux { 980 groups = "uart_tx_b_x", 981 "uart_rx_b_x"; 982 function = "uart_b"; 983 }; 984 }; 985 986 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 987 mux { 988 groups = "uart_cts_b_x", 989 "uart_rts_b_x"; 990 function = "uart_b"; 991 }; 992 }; 993 994 uart_b_z_pins: uart_b_z { 995 mux { 996 groups = "uart_tx_b_z", 997 "uart_rx_b_z"; 998 function = "uart_b"; 999 }; 1000 }; 1001 1002 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1003 mux { 1004 groups = "uart_cts_b_z", 1005 "uart_rts_b_z"; 1006 function = "uart_b"; 1007 }; 1008 }; 1009 1010 uart_ao_b_z_pins: uart_ao_b_z { 1011 mux { 1012 groups = "uart_ao_tx_b_z", 1013 "uart_ao_rx_b_z"; 1014 function = "uart_ao_b_z"; 1015 }; 1016 }; 1017 1018 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1019 mux { 1020 groups = "uart_ao_cts_b_z", 1021 "uart_ao_rts_b_z"; 1022 function = "uart_ao_b_z"; 1023 }; 1024 }; 1025 1026 mclk_b_pins: mclk_b { 1027 mux { 1028 groups = "mclk_b"; 1029 function = "mclk_b"; 1030 }; 1031 }; 1032 1033 mclk_c_pins: mclk_c { 1034 mux { 1035 groups = "mclk_c"; 1036 function = "mclk_c"; 1037 }; 1038 }; 1039 1040 tdma_sclk_pins: tdma_sclk { 1041 mux { 1042 groups = "tdma_sclk"; 1043 function = "tdma"; 1044 }; 1045 }; 1046 1047 tdma_sclk_slv_pins: tdma_sclk_slv { 1048 mux { 1049 groups = "tdma_sclk_slv"; 1050 function = "tdma"; 1051 }; 1052 }; 1053 1054 tdma_fs_pins: tdma_fs { 1055 mux { 1056 groups = "tdma_fs"; 1057 function = "tdma"; 1058 }; 1059 }; 1060 1061 tdma_fs_slv_pins: tdma_fs_slv { 1062 mux { 1063 groups = "tdma_fs_slv"; 1064 function = "tdma"; 1065 }; 1066 }; 1067 1068 tdma_din0_pins: tdma_din0 { 1069 mux { 1070 groups = "tdma_din0"; 1071 function = "tdma"; 1072 }; 1073 }; 1074 1075 tdma_dout0_x14_pins: tdma_dout0_x14 { 1076 mux { 1077 groups = "tdma_dout0_x14"; 1078 function = "tdma"; 1079 }; 1080 }; 1081 1082 tdma_dout0_x15_pins: tdma_dout0_x15 { 1083 mux { 1084 groups = "tdma_dout0_x15"; 1085 function = "tdma"; 1086 }; 1087 }; 1088 1089 tdma_dout1_pins: tdma_dout1 { 1090 mux { 1091 groups = "tdma_dout1"; 1092 function = "tdma"; 1093 }; 1094 }; 1095 1096 tdma_din1_pins: tdma_din1 { 1097 mux { 1098 groups = "tdma_din1"; 1099 function = "tdma"; 1100 }; 1101 }; 1102 1103 tdmb_sclk_pins: tdmb_sclk { 1104 mux { 1105 groups = "tdmb_sclk"; 1106 function = "tdmb"; 1107 }; 1108 }; 1109 1110 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1111 mux { 1112 groups = "tdmb_sclk_slv"; 1113 function = "tdmb"; 1114 }; 1115 }; 1116 1117 tdmb_fs_pins: tdmb_fs { 1118 mux { 1119 groups = "tdmb_fs"; 1120 function = "tdmb"; 1121 }; 1122 }; 1123 1124 tdmb_fs_slv_pins: tdmb_fs_slv { 1125 mux { 1126 groups = "tdmb_fs_slv"; 1127 function = "tdmb"; 1128 }; 1129 }; 1130 1131 tdmb_din0_pins: tdmb_din0 { 1132 mux { 1133 groups = "tdmb_din0"; 1134 function = "tdmb"; 1135 }; 1136 }; 1137 1138 tdmb_dout0_pins: tdmb_dout0 { 1139 mux { 1140 groups = "tdmb_dout0"; 1141 function = "tdmb"; 1142 }; 1143 }; 1144 1145 tdmb_din1_pins: tdmb_din1 { 1146 mux { 1147 groups = "tdmb_din1"; 1148 function = "tdmb"; 1149 }; 1150 }; 1151 1152 tdmb_dout1_pins: tdmb_dout1 { 1153 mux { 1154 groups = "tdmb_dout1"; 1155 function = "tdmb"; 1156 }; 1157 }; 1158 1159 tdmb_din2_pins: tdmb_din2 { 1160 mux { 1161 groups = "tdmb_din2"; 1162 function = "tdmb"; 1163 }; 1164 }; 1165 1166 tdmb_dout2_pins: tdmb_dout2 { 1167 mux { 1168 groups = "tdmb_dout2"; 1169 function = "tdmb"; 1170 }; 1171 }; 1172 1173 tdmb_din3_pins: tdmb_din3 { 1174 mux { 1175 groups = "tdmb_din3"; 1176 function = "tdmb"; 1177 }; 1178 }; 1179 1180 tdmb_dout3_pins: tdmb_dout3 { 1181 mux { 1182 groups = "tdmb_dout3"; 1183 function = "tdmb"; 1184 }; 1185 }; 1186 1187 tdmc_sclk_pins: tdmc_sclk { 1188 mux { 1189 groups = "tdmc_sclk"; 1190 function = "tdmc"; 1191 }; 1192 }; 1193 1194 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1195 mux { 1196 groups = "tdmc_sclk_slv"; 1197 function = "tdmc"; 1198 }; 1199 }; 1200 1201 tdmc_fs_pins: tdmc_fs { 1202 mux { 1203 groups = "tdmc_fs"; 1204 function = "tdmc"; 1205 }; 1206 }; 1207 1208 tdmc_fs_slv_pins: tdmc_fs_slv { 1209 mux { 1210 groups = "tdmc_fs_slv"; 1211 function = "tdmc"; 1212 }; 1213 }; 1214 1215 tdmc_din0_pins: tdmc_din0 { 1216 mux { 1217 groups = "tdmc_din0"; 1218 function = "tdmc"; 1219 }; 1220 }; 1221 1222 tdmc_dout0_pins: tdmc_dout0 { 1223 mux { 1224 groups = "tdmc_dout0"; 1225 function = "tdmc"; 1226 }; 1227 }; 1228 1229 tdmc_din1_pins: tdmc_din1 { 1230 mux { 1231 groups = "tdmc_din1"; 1232 function = "tdmc"; 1233 }; 1234 }; 1235 1236 tdmc_dout1_pins: tdmc_dout1 { 1237 mux { 1238 groups = "tdmc_dout1"; 1239 function = "tdmc"; 1240 }; 1241 }; 1242 1243 tdmc_din2_pins: tdmc_din2 { 1244 mux { 1245 groups = "tdmc_din2"; 1246 function = "tdmc"; 1247 }; 1248 }; 1249 1250 tdmc_dout2_pins: tdmc_dout2 { 1251 mux { 1252 groups = "tdmc_dout2"; 1253 function = "tdmc"; 1254 }; 1255 }; 1256 1257 tdmc_din3_pins: tdmc_din3 { 1258 mux { 1259 groups = "tdmc_din3"; 1260 function = "tdmc"; 1261 }; 1262 }; 1263 1264 tdmc_dout3_pins: tdmc_dout3 { 1265 mux { 1266 groups = "tdmc_dout3"; 1267 function = "tdmc"; 1268 }; 1269 }; 1270 }; 1271 }; 1272 1273 sram: sram@fffc0000 { 1274 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1275 reg = <0x0 0xfffc0000 0x0 0x20000>; 1276 #address-cells = <1>; 1277 #size-cells = <1>; 1278 ranges = <0 0x0 0xfffc0000 0x20000>; 1279 1280 cpu_scp_lpri: scp-shmem@0 { 1281 compatible = "amlogic,meson-axg-scp-shmem"; 1282 reg = <0x13000 0x400>; 1283 }; 1284 1285 cpu_scp_hpri: scp-shmem@200 { 1286 compatible = "amlogic,meson-axg-scp-shmem"; 1287 reg = <0x13400 0x400>; 1288 }; 1289 }; 1290 1291 aobus: bus@ff800000 { 1292 compatible = "simple-bus"; 1293 reg = <0x0 0xff800000 0x0 0x100000>; 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1297 1298 sysctrl_AO: sys-ctrl@0 { 1299 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd"; 1300 reg = <0x0 0x0 0x0 0x100>; 1301 1302 clkc_AO: clock-controller { 1303 compatible = "amlogic,meson-axg-aoclkc"; 1304 #clock-cells = <1>; 1305 #reset-cells = <1>; 1306 }; 1307 }; 1308 1309 pinctrl_aobus: pinctrl@14 { 1310 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1311 #address-cells = <2>; 1312 #size-cells = <2>; 1313 ranges; 1314 1315 gpio_ao: bank@14 { 1316 reg = <0x0 0x00014 0x0 0x8>, 1317 <0x0 0x0002c 0x0 0x4>, 1318 <0x0 0x00024 0x0 0x8>; 1319 reg-names = "mux", "pull", "gpio"; 1320 gpio-controller; 1321 #gpio-cells = <2>; 1322 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1323 }; 1324 1325 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1326 mux { 1327 groups = "i2c_ao_sck_4"; 1328 function = "i2c_ao"; 1329 }; 1330 }; 1331 1332 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1333 mux { 1334 groups = "i2c_ao_sck_8"; 1335 function = "i2c_ao"; 1336 }; 1337 }; 1338 1339 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1340 mux { 1341 groups = "i2c_ao_sck_10"; 1342 function = "i2c_ao"; 1343 }; 1344 }; 1345 1346 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1347 mux { 1348 groups = "i2c_ao_sda_5"; 1349 function = "i2c_ao"; 1350 }; 1351 }; 1352 1353 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1354 mux { 1355 groups = "i2c_ao_sda_9"; 1356 function = "i2c_ao"; 1357 }; 1358 }; 1359 1360 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1361 mux { 1362 groups = "i2c_ao_sda_11"; 1363 function = "i2c_ao"; 1364 }; 1365 }; 1366 1367 remote_input_ao_pins: remote_input_ao { 1368 mux { 1369 groups = "remote_input_ao"; 1370 function = "remote_input_ao"; 1371 }; 1372 }; 1373 1374 uart_ao_a_pins: uart_ao_a { 1375 mux { 1376 groups = "uart_ao_tx_a", 1377 "uart_ao_rx_a"; 1378 function = "uart_ao_a"; 1379 }; 1380 }; 1381 1382 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1383 mux { 1384 groups = "uart_ao_cts_a", 1385 "uart_ao_rts_a"; 1386 function = "uart_ao_a"; 1387 }; 1388 }; 1389 1390 uart_ao_b_pins: uart_ao_b { 1391 mux { 1392 groups = "uart_ao_tx_b", 1393 "uart_ao_rx_b"; 1394 function = "uart_ao_b"; 1395 }; 1396 }; 1397 1398 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1399 mux { 1400 groups = "uart_ao_cts_b", 1401 "uart_ao_rts_b"; 1402 function = "uart_ao_b"; 1403 }; 1404 }; 1405 }; 1406 1407 sec_AO: ao-secure@140 { 1408 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1409 reg = <0x0 0x140 0x0 0x140>; 1410 amlogic,has-chip-id; 1411 }; 1412 1413 pwm_AO_ab: pwm@7000 { 1414 compatible = "amlogic,meson-axg-ao-pwm"; 1415 reg = <0x0 0x07000 0x0 0x20>; 1416 #pwm-cells = <3>; 1417 status = "disabled"; 1418 }; 1419 1420 pwm_AO_cd: pwm@2000 { 1421 compatible = "amlogic,meson-axg-ao-pwm"; 1422 reg = <0x0 0x02000 0x0 0x20>; 1423 #pwm-cells = <3>; 1424 status = "disabled"; 1425 }; 1426 1427 i2c_AO: i2c@5000 { 1428 compatible = "amlogic,meson-axg-i2c"; 1429 reg = <0x0 0x05000 0x0 0x20>; 1430 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1431 clocks = <&clkc CLKID_AO_I2C>; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 1437 uart_AO: serial@3000 { 1438 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1439 reg = <0x0 0x3000 0x0 0x18>; 1440 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1441 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1442 clock-names = "xtal", "pclk", "baud"; 1443 status = "disabled"; 1444 }; 1445 1446 uart_AO_B: serial@4000 { 1447 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1448 reg = <0x0 0x4000 0x0 0x18>; 1449 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1450 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1451 clock-names = "xtal", "pclk", "baud"; 1452 status = "disabled"; 1453 }; 1454 1455 ir: ir@8000 { 1456 compatible = "amlogic,meson-gxbb-ir"; 1457 reg = <0x0 0x8000 0x0 0x20>; 1458 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1459 status = "disabled"; 1460 }; 1461 1462 saradc: adc@9000 { 1463 compatible = "amlogic,meson-axg-saradc", 1464 "amlogic,meson-saradc"; 1465 reg = <0x0 0x9000 0x0 0x38>; 1466 #io-channel-cells = <1>; 1467 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1468 clocks = <&xtal>, 1469 <&clkc_AO CLKID_AO_SAR_ADC>, 1470 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1471 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1472 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 }; 1477}; 1478