1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15
16/ {
17	compatible = "amlogic,meson-axg";
18
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	tdmif_a: audio-controller-0 {
24		compatible = "amlogic,axg-tdm-iface";
25		#sound-dai-cells = <0>;
26		sound-name-prefix = "TDM_A";
27		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30		clock-names = "mclk", "sclk", "lrclk";
31		status = "disabled";
32	};
33
34	tdmif_b: audio-controller-1 {
35		compatible = "amlogic,axg-tdm-iface";
36		#sound-dai-cells = <0>;
37		sound-name-prefix = "TDM_B";
38		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41		clock-names = "mclk", "sclk", "lrclk";
42		status = "disabled";
43	};
44
45	tdmif_c: audio-controller-2 {
46		compatible = "amlogic,axg-tdm-iface";
47		#sound-dai-cells = <0>;
48		sound-name-prefix = "TDM_C";
49		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52		clock-names = "mclk", "sclk", "lrclk";
53		status = "disabled";
54	};
55
56	arm-pmu {
57		compatible = "arm,cortex-a53-pmu";
58		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
59			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
62		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
63	};
64
65	cpus {
66		#address-cells = <0x2>;
67		#size-cells = <0x0>;
68
69		cpu0: cpu@0 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53";
72			reg = <0x0 0x0>;
73			enable-method = "psci";
74			next-level-cache = <&l2>;
75			clocks = <&scpi_dvfs 0>;
76		};
77
78		cpu1: cpu@1 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a53";
81			reg = <0x0 0x1>;
82			enable-method = "psci";
83			next-level-cache = <&l2>;
84			clocks = <&scpi_dvfs 0>;
85		};
86
87		cpu2: cpu@2 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a53";
90			reg = <0x0 0x2>;
91			enable-method = "psci";
92			next-level-cache = <&l2>;
93			clocks = <&scpi_dvfs 0>;
94		};
95
96		cpu3: cpu@3 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a53";
99			reg = <0x0 0x3>;
100			enable-method = "psci";
101			next-level-cache = <&l2>;
102			clocks = <&scpi_dvfs 0>;
103		};
104
105		l2: l2-cache0 {
106			compatible = "cache";
107		};
108	};
109
110	sm: secure-monitor {
111		compatible = "amlogic,meson-gxbb-sm";
112	};
113
114	efuse: efuse {
115		compatible = "amlogic,meson-gxbb-efuse";
116		clocks = <&clkc CLKID_EFUSE>;
117		#address-cells = <1>;
118		#size-cells = <1>;
119		read-only;
120		secure-monitor = <&sm>;
121	};
122
123	psci {
124		compatible = "arm,psci-1.0";
125		method = "smc";
126	};
127
128	reserved-memory {
129		#address-cells = <2>;
130		#size-cells = <2>;
131		ranges;
132
133		/* 16 MiB reserved for Hardware ROM Firmware */
134		hwrom_reserved: hwrom@0 {
135			reg = <0x0 0x0 0x0 0x1000000>;
136			no-map;
137		};
138
139		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
140		secmon_reserved: secmon@5000000 {
141			reg = <0x0 0x05000000 0x0 0x300000>;
142			no-map;
143		};
144	};
145
146	scpi {
147		compatible = "arm,scpi-pre-1.0";
148		mboxes = <&mailbox 1 &mailbox 2>;
149		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
150
151		scpi_clocks: clocks {
152			compatible = "arm,scpi-clocks";
153
154			scpi_dvfs: clock-controller {
155				compatible = "arm,scpi-dvfs-clocks";
156				#clock-cells = <1>;
157				clock-indices = <0>;
158				clock-output-names = "vcpu";
159			};
160		};
161
162		scpi_sensors: sensors {
163			compatible = "amlogic,meson-gxbb-scpi-sensors";
164			#thermal-sensor-cells = <1>;
165		};
166	};
167
168	soc {
169		compatible = "simple-bus";
170		#address-cells = <2>;
171		#size-cells = <2>;
172		ranges;
173
174		usb: usb@ffe09080 {
175			compatible = "amlogic,meson-axg-usb-ctrl";
176			reg = <0x0 0xffe09080 0x0 0x20>;
177			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
178			#address-cells = <2>;
179			#size-cells = <2>;
180			ranges;
181
182			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
183			clock-names = "usb_ctrl", "ddr";
184			resets = <&reset RESET_USB_OTG>;
185
186			dr_mode = "otg";
187
188			phys = <&usb2_phy1>;
189			phy-names = "usb2-phy1";
190
191			dwc2: usb@ff400000 {
192				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
193				reg = <0x0 0xff400000 0x0 0x40000>;
194				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
195				clocks = <&clkc CLKID_USB1>;
196				clock-names = "otg";
197				phys = <&usb2_phy1>;
198				dr_mode = "peripheral";
199				g-rx-fifo-size = <192>;
200				g-np-tx-fifo-size = <128>;
201				g-tx-fifo-size = <128 128 16 16 16>;
202			};
203
204			dwc3: usb@ff500000 {
205				compatible = "snps,dwc3";
206				reg = <0x0 0xff500000 0x0 0x100000>;
207				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
208				dr_mode = "host";
209				maximum-speed = "high-speed";
210				snps,dis_u2_susphy_quirk;
211			};
212		};
213
214		ethmac: ethernet@ff3f0000 {
215			compatible = "amlogic,meson-axg-dwmac",
216				     "snps,dwmac-3.70a",
217				     "snps,dwmac";
218			reg = <0x0 0xff3f0000 0x0 0x10000>,
219			      <0x0 0xff634540 0x0 0x8>;
220			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
221			interrupt-names = "macirq";
222			clocks = <&clkc CLKID_ETH>,
223				 <&clkc CLKID_FCLK_DIV2>,
224				 <&clkc CLKID_MPLL2>,
225				 <&clkc CLKID_FCLK_DIV2>;
226			clock-names = "stmmaceth", "clkin0", "clkin1",
227				      "timing-adjustment";
228			rx-fifo-depth = <4096>;
229			tx-fifo-depth = <2048>;
230			resets = <&reset RESET_ETHERNET>;
231			reset-names = "stmmaceth";
232			status = "disabled";
233		};
234
235		pdm: audio-controller@ff632000 {
236			compatible = "amlogic,axg-pdm";
237			reg = <0x0 0xff632000 0x0 0x34>;
238			#sound-dai-cells = <0>;
239			sound-name-prefix = "PDM";
240			clocks = <&clkc_audio AUD_CLKID_PDM>,
241				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
242				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
243			clock-names = "pclk", "dclk", "sysclk";
244			status = "disabled";
245		};
246
247		periphs: bus@ff634000 {
248			compatible = "simple-bus";
249			reg = <0x0 0xff634000 0x0 0x2000>;
250			#address-cells = <2>;
251			#size-cells = <2>;
252			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
253
254			hwrng: rng@18 {
255				compatible = "amlogic,meson-rng";
256				reg = <0x0 0x18 0x0 0x4>;
257				clocks = <&clkc CLKID_RNG0>;
258				clock-names = "core";
259			};
260
261			pinctrl_periphs: pinctrl@480 {
262				compatible = "amlogic,meson-axg-periphs-pinctrl";
263				#address-cells = <2>;
264				#size-cells = <2>;
265				ranges;
266
267				gpio: bank@480 {
268					reg = <0x0 0x00480 0x0 0x40>,
269					      <0x0 0x004e8 0x0 0x14>,
270					      <0x0 0x00520 0x0 0x14>,
271					      <0x0 0x00430 0x0 0x3c>;
272					reg-names = "mux", "pull", "pull-enable", "gpio";
273					gpio-controller;
274					#gpio-cells = <2>;
275					gpio-ranges = <&pinctrl_periphs 0 0 86>;
276				};
277
278				i2c0_pins: i2c0 {
279					mux {
280						groups = "i2c0_sck",
281							 "i2c0_sda";
282						function = "i2c0";
283						bias-disable;
284					};
285				};
286
287				i2c1_x_pins: i2c1_x {
288					mux {
289						groups = "i2c1_sck_x",
290							 "i2c1_sda_x";
291						function = "i2c1";
292						bias-disable;
293					};
294				};
295
296				i2c1_z_pins: i2c1_z {
297					mux {
298						groups = "i2c1_sck_z",
299							 "i2c1_sda_z";
300						function = "i2c1";
301						bias-disable;
302					};
303				};
304
305				i2c2_a_pins: i2c2_a {
306					mux {
307						groups = "i2c2_sck_a",
308							 "i2c2_sda_a";
309						function = "i2c2";
310						bias-disable;
311					};
312				};
313
314				i2c2_x_pins: i2c2_x {
315					mux {
316						groups = "i2c2_sck_x",
317							 "i2c2_sda_x";
318						function = "i2c2";
319						bias-disable;
320					};
321				};
322
323				i2c3_a6_pins: i2c3_a6 {
324					mux {
325						groups = "i2c3_sda_a6",
326							 "i2c3_sck_a7";
327						function = "i2c3";
328						bias-disable;
329					};
330				};
331
332				i2c3_a12_pins: i2c3_a12 {
333					mux {
334						groups = "i2c3_sda_a12",
335							 "i2c3_sck_a13";
336						function = "i2c3";
337						bias-disable;
338					};
339				};
340
341				i2c3_a19_pins: i2c3_a19 {
342					mux {
343						groups = "i2c3_sda_a19",
344							 "i2c3_sck_a20";
345						function = "i2c3";
346						bias-disable;
347					};
348				};
349
350				emmc_pins: emmc {
351					mux-0 {
352						groups = "emmc_nand_d0",
353							 "emmc_nand_d1",
354							 "emmc_nand_d2",
355							 "emmc_nand_d3",
356							 "emmc_nand_d4",
357							 "emmc_nand_d5",
358							 "emmc_nand_d6",
359							 "emmc_nand_d7",
360							 "emmc_cmd";
361						function = "emmc";
362						bias-pull-up;
363					};
364
365					mux-1 {
366						groups = "emmc_clk";
367						function = "emmc";
368						bias-disable;
369					};
370				};
371
372				emmc_ds_pins: emmc_ds {
373					mux {
374						groups = "emmc_ds";
375						function = "emmc";
376						bias-pull-down;
377					};
378				};
379
380				emmc_clk_gate_pins: emmc_clk_gate {
381					mux {
382						groups = "BOOT_8";
383						function = "gpio_periphs";
384						bias-pull-down;
385					};
386				};
387
388				eth_rgmii_x_pins: eth-x-rgmii {
389					mux {
390						groups = "eth_mdio_x",
391							 "eth_mdc_x",
392							 "eth_rgmii_rx_clk_x",
393							 "eth_rx_dv_x",
394							 "eth_rxd0_x",
395							 "eth_rxd1_x",
396							 "eth_rxd2_rgmii",
397							 "eth_rxd3_rgmii",
398							 "eth_rgmii_tx_clk",
399							 "eth_txen_x",
400							 "eth_txd0_x",
401							 "eth_txd1_x",
402							 "eth_txd2_rgmii",
403							 "eth_txd3_rgmii";
404						function = "eth";
405						bias-disable;
406					};
407				};
408
409				eth_rgmii_y_pins: eth-y-rgmii {
410					mux {
411						groups = "eth_mdio_y",
412							 "eth_mdc_y",
413							 "eth_rgmii_rx_clk_y",
414							 "eth_rx_dv_y",
415							 "eth_rxd0_y",
416							 "eth_rxd1_y",
417							 "eth_rxd2_rgmii",
418							 "eth_rxd3_rgmii",
419							 "eth_rgmii_tx_clk",
420							 "eth_txen_y",
421							 "eth_txd0_y",
422							 "eth_txd1_y",
423							 "eth_txd2_rgmii",
424							 "eth_txd3_rgmii";
425						function = "eth";
426						bias-disable;
427					};
428				};
429
430				eth_rmii_x_pins: eth-x-rmii {
431					mux {
432						groups = "eth_mdio_x",
433							 "eth_mdc_x",
434							 "eth_rgmii_rx_clk_x",
435							 "eth_rx_dv_x",
436							 "eth_rxd0_x",
437							 "eth_rxd1_x",
438							 "eth_txen_x",
439							 "eth_txd0_x",
440							 "eth_txd1_x";
441						function = "eth";
442						bias-disable;
443					};
444				};
445
446				eth_rmii_y_pins: eth-y-rmii {
447					mux {
448						groups = "eth_mdio_y",
449							 "eth_mdc_y",
450							 "eth_rgmii_rx_clk_y",
451							 "eth_rx_dv_y",
452							 "eth_rxd0_y",
453							 "eth_rxd1_y",
454							 "eth_txen_y",
455							 "eth_txd0_y",
456							 "eth_txd1_y";
457						function = "eth";
458						bias-disable;
459					};
460				};
461
462				mclk_b_pins: mclk_b {
463					mux {
464						groups = "mclk_b";
465						function = "mclk_b";
466						bias-disable;
467					};
468				};
469
470				mclk_c_pins: mclk_c {
471					mux {
472						groups = "mclk_c";
473						function = "mclk_c";
474						bias-disable;
475					};
476				};
477
478				pdm_dclk_a14_pins: pdm_dclk_a14 {
479					mux {
480						groups = "pdm_dclk_a14";
481						function = "pdm";
482						bias-disable;
483					};
484				};
485
486				pdm_dclk_a19_pins: pdm_dclk_a19 {
487					mux {
488						groups = "pdm_dclk_a19";
489						function = "pdm";
490						bias-disable;
491					};
492				};
493
494				pdm_din0_pins: pdm_din0 {
495					mux {
496						groups = "pdm_din0";
497						function = "pdm";
498						bias-disable;
499					};
500				};
501
502				pdm_din1_pins: pdm_din1 {
503					mux {
504						groups = "pdm_din1";
505						function = "pdm";
506						bias-disable;
507					};
508				};
509
510				pdm_din2_pins: pdm_din2 {
511					mux {
512						groups = "pdm_din2";
513						function = "pdm";
514						bias-disable;
515					};
516				};
517
518				pdm_din3_pins: pdm_din3 {
519					mux {
520						groups = "pdm_din3";
521						function = "pdm";
522						bias-disable;
523					};
524				};
525
526				pwm_a_a_pins: pwm_a_a {
527					mux {
528						groups = "pwm_a_a";
529						function = "pwm_a";
530						bias-disable;
531					};
532				};
533
534				pwm_a_x18_pins: pwm_a_x18 {
535					mux {
536						groups = "pwm_a_x18";
537						function = "pwm_a";
538						bias-disable;
539					};
540				};
541
542				pwm_a_x20_pins: pwm_a_x20 {
543					mux {
544						groups = "pwm_a_x20";
545						function = "pwm_a";
546						bias-disable;
547					};
548				};
549
550				pwm_a_z_pins: pwm_a_z {
551					mux {
552						groups = "pwm_a_z";
553						function = "pwm_a";
554						bias-disable;
555					};
556				};
557
558				pwm_b_a_pins: pwm_b_a {
559					mux {
560						groups = "pwm_b_a";
561						function = "pwm_b";
562						bias-disable;
563					};
564				};
565
566				pwm_b_x_pins: pwm_b_x {
567					mux {
568						groups = "pwm_b_x";
569						function = "pwm_b";
570						bias-disable;
571					};
572				};
573
574				pwm_b_z_pins: pwm_b_z {
575					mux {
576						groups = "pwm_b_z";
577						function = "pwm_b";
578						bias-disable;
579					};
580				};
581
582				pwm_c_a_pins: pwm_c_a {
583					mux {
584						groups = "pwm_c_a";
585						function = "pwm_c";
586						bias-disable;
587					};
588				};
589
590				pwm_c_x10_pins: pwm_c_x10 {
591					mux {
592						groups = "pwm_c_x10";
593						function = "pwm_c";
594						bias-disable;
595					};
596				};
597
598				pwm_c_x17_pins: pwm_c_x17 {
599					mux {
600						groups = "pwm_c_x17";
601						function = "pwm_c";
602						bias-disable;
603					};
604				};
605
606				pwm_d_x11_pins: pwm_d_x11 {
607					mux {
608						groups = "pwm_d_x11";
609						function = "pwm_d";
610						bias-disable;
611					};
612				};
613
614				pwm_d_x16_pins: pwm_d_x16 {
615					mux {
616						groups = "pwm_d_x16";
617						function = "pwm_d";
618						bias-disable;
619					};
620				};
621
622				sdio_pins: sdio {
623					mux-0 {
624						groups = "sdio_d0",
625							 "sdio_d1",
626							 "sdio_d2",
627							 "sdio_d3",
628							 "sdio_cmd";
629						function = "sdio";
630						bias-pull-up;
631					};
632
633					mux-1 {
634						groups = "sdio_clk";
635						function = "sdio";
636						bias-disable;
637					};
638				};
639
640				sdio_clk_gate_pins: sdio_clk_gate {
641					mux {
642						groups = "GPIOX_4";
643						function = "gpio_periphs";
644						bias-pull-down;
645					};
646				};
647
648				spdif_in_z_pins: spdif_in_z {
649					mux {
650						groups = "spdif_in_z";
651						function = "spdif_in";
652						bias-disable;
653					};
654				};
655
656				spdif_in_a1_pins: spdif_in_a1 {
657					mux {
658						groups = "spdif_in_a1";
659						function = "spdif_in";
660						bias-disable;
661					};
662				};
663
664				spdif_in_a7_pins: spdif_in_a7 {
665					mux {
666						groups = "spdif_in_a7";
667						function = "spdif_in";
668						bias-disable;
669					};
670				};
671
672				spdif_in_a19_pins: spdif_in_a19 {
673					mux {
674						groups = "spdif_in_a19";
675						function = "spdif_in";
676						bias-disable;
677					};
678				};
679
680				spdif_in_a20_pins: spdif_in_a20 {
681					mux {
682						groups = "spdif_in_a20";
683						function = "spdif_in";
684						bias-disable;
685					};
686				};
687
688				spdif_out_a1_pins: spdif_out_a1 {
689					mux {
690						groups = "spdif_out_a1";
691						function = "spdif_out";
692						bias-disable;
693					};
694				};
695
696				spdif_out_a11_pins: spdif_out_a11 {
697					mux {
698						groups = "spdif_out_a11";
699						function = "spdif_out";
700						bias-disable;
701					};
702				};
703
704				spdif_out_a19_pins: spdif_out_a19 {
705					mux {
706						groups = "spdif_out_a19";
707						function = "spdif_out";
708						bias-disable;
709					};
710				};
711
712				spdif_out_a20_pins: spdif_out_a20 {
713					mux {
714						groups = "spdif_out_a20";
715						function = "spdif_out";
716						bias-disable;
717					};
718				};
719
720				spdif_out_z_pins: spdif_out_z {
721					mux {
722						groups = "spdif_out_z";
723						function = "spdif_out";
724						bias-disable;
725					};
726				};
727
728				spi0_pins: spi0 {
729					mux {
730						groups = "spi0_miso",
731							 "spi0_mosi",
732							 "spi0_clk";
733						function = "spi0";
734						bias-disable;
735					};
736				};
737
738				spi0_ss0_pins: spi0_ss0 {
739					mux {
740						groups = "spi0_ss0";
741						function = "spi0";
742						bias-disable;
743					};
744				};
745
746				spi0_ss1_pins: spi0_ss1 {
747					mux {
748						groups = "spi0_ss1";
749						function = "spi0";
750						bias-disable;
751					};
752				};
753
754				spi0_ss2_pins: spi0_ss2 {
755					mux {
756						groups = "spi0_ss2";
757						function = "spi0";
758						bias-disable;
759					};
760				};
761
762				spi1_a_pins: spi1_a {
763					mux {
764						groups = "spi1_miso_a",
765							 "spi1_mosi_a",
766							 "spi1_clk_a";
767						function = "spi1";
768						bias-disable;
769					};
770				};
771
772				spi1_ss0_a_pins: spi1_ss0_a {
773					mux {
774						groups = "spi1_ss0_a";
775						function = "spi1";
776						bias-disable;
777					};
778				};
779
780				spi1_ss1_pins: spi1_ss1 {
781					mux {
782						groups = "spi1_ss1";
783						function = "spi1";
784						bias-disable;
785					};
786				};
787
788				spi1_x_pins: spi1_x {
789					mux {
790						groups = "spi1_miso_x",
791							 "spi1_mosi_x",
792							 "spi1_clk_x";
793						function = "spi1";
794						bias-disable;
795					};
796				};
797
798				spi1_ss0_x_pins: spi1_ss0_x {
799					mux {
800						groups = "spi1_ss0_x";
801						function = "spi1";
802						bias-disable;
803					};
804				};
805
806				tdma_din0_pins: tdma_din0 {
807					mux {
808						groups = "tdma_din0";
809						function = "tdma";
810						bias-disable;
811					};
812				};
813
814				tdma_dout0_x14_pins: tdma_dout0_x14 {
815					mux {
816						groups = "tdma_dout0_x14";
817						function = "tdma";
818						bias-disable;
819					};
820				};
821
822				tdma_dout0_x15_pins: tdma_dout0_x15 {
823					mux {
824						groups = "tdma_dout0_x15";
825						function = "tdma";
826						bias-disable;
827					};
828				};
829
830				tdma_dout1_pins: tdma_dout1 {
831					mux {
832						groups = "tdma_dout1";
833						function = "tdma";
834						bias-disable;
835					};
836				};
837
838				tdma_din1_pins: tdma_din1 {
839					mux {
840						groups = "tdma_din1";
841						function = "tdma";
842						bias-disable;
843					};
844				};
845
846				tdma_fs_pins: tdma_fs {
847					mux {
848						groups = "tdma_fs";
849						function = "tdma";
850						bias-disable;
851					};
852				};
853
854				tdma_fs_slv_pins: tdma_fs_slv {
855					mux {
856						groups = "tdma_fs_slv";
857						function = "tdma";
858						bias-disable;
859					};
860				};
861
862				tdma_sclk_pins: tdma_sclk {
863					mux {
864						groups = "tdma_sclk";
865						function = "tdma";
866						bias-disable;
867					};
868				};
869
870				tdma_sclk_slv_pins: tdma_sclk_slv {
871					mux {
872						groups = "tdma_sclk_slv";
873						function = "tdma";
874						bias-disable;
875					};
876				};
877
878				tdmb_din0_pins: tdmb_din0 {
879					mux {
880						groups = "tdmb_din0";
881						function = "tdmb";
882						bias-disable;
883					};
884				};
885
886				tdmb_din1_pins: tdmb_din1 {
887					mux {
888						groups = "tdmb_din1";
889						function = "tdmb";
890						bias-disable;
891					};
892				};
893
894				tdmb_din2_pins: tdmb_din2 {
895					mux {
896						groups = "tdmb_din2";
897						function = "tdmb";
898						bias-disable;
899					};
900				};
901
902				tdmb_din3_pins: tdmb_din3 {
903					mux {
904						groups = "tdmb_din3";
905						function = "tdmb";
906						bias-disable;
907					};
908				};
909
910				tdmb_dout0_pins: tdmb_dout0 {
911					mux {
912						groups = "tdmb_dout0";
913						function = "tdmb";
914						bias-disable;
915					};
916				};
917
918				tdmb_dout1_pins: tdmb_dout1 {
919					mux {
920						groups = "tdmb_dout1";
921						function = "tdmb";
922						bias-disable;
923					};
924				};
925
926				tdmb_dout2_pins: tdmb_dout2 {
927					mux {
928						groups = "tdmb_dout2";
929						function = "tdmb";
930						bias-disable;
931					};
932				};
933
934				tdmb_dout3_pins: tdmb_dout3 {
935					mux {
936						groups = "tdmb_dout3";
937						function = "tdmb";
938						bias-disable;
939					};
940				};
941
942				tdmb_fs_pins: tdmb_fs {
943					mux {
944						groups = "tdmb_fs";
945						function = "tdmb";
946						bias-disable;
947					};
948				};
949
950				tdmb_fs_slv_pins: tdmb_fs_slv {
951					mux {
952						groups = "tdmb_fs_slv";
953						function = "tdmb";
954						bias-disable;
955					};
956				};
957
958				tdmb_sclk_pins: tdmb_sclk {
959					mux {
960						groups = "tdmb_sclk";
961						function = "tdmb";
962						bias-disable;
963					};
964				};
965
966				tdmb_sclk_slv_pins: tdmb_sclk_slv {
967					mux {
968						groups = "tdmb_sclk_slv";
969						function = "tdmb";
970						bias-disable;
971					};
972				};
973
974				tdmc_fs_pins: tdmc_fs {
975					mux {
976						groups = "tdmc_fs";
977						function = "tdmc";
978						bias-disable;
979					};
980				};
981
982				tdmc_fs_slv_pins: tdmc_fs_slv {
983					mux {
984						groups = "tdmc_fs_slv";
985						function = "tdmc";
986						bias-disable;
987					};
988				};
989
990				tdmc_sclk_pins: tdmc_sclk {
991					mux {
992						groups = "tdmc_sclk";
993						function = "tdmc";
994						bias-disable;
995					};
996				};
997
998				tdmc_sclk_slv_pins: tdmc_sclk_slv {
999					mux {
1000						groups = "tdmc_sclk_slv";
1001						function = "tdmc";
1002						bias-disable;
1003					};
1004				};
1005
1006				tdmc_din0_pins: tdmc_din0 {
1007					mux {
1008						groups = "tdmc_din0";
1009						function = "tdmc";
1010						bias-disable;
1011					};
1012				};
1013
1014				tdmc_din1_pins: tdmc_din1 {
1015					mux {
1016						groups = "tdmc_din1";
1017						function = "tdmc";
1018						bias-disable;
1019					};
1020				};
1021
1022				tdmc_din2_pins: tdmc_din2 {
1023					mux {
1024						groups = "tdmc_din2";
1025						function = "tdmc";
1026						bias-disable;
1027					};
1028				};
1029
1030				tdmc_din3_pins: tdmc_din3 {
1031					mux {
1032						groups = "tdmc_din3";
1033						function = "tdmc";
1034						bias-disable;
1035					};
1036				};
1037
1038				tdmc_dout0_pins: tdmc_dout0 {
1039					mux {
1040						groups = "tdmc_dout0";
1041						function = "tdmc";
1042						bias-disable;
1043					};
1044				};
1045
1046				tdmc_dout1_pins: tdmc_dout1 {
1047					mux {
1048						groups = "tdmc_dout1";
1049						function = "tdmc";
1050						bias-disable;
1051					};
1052				};
1053
1054				tdmc_dout2_pins: tdmc_dout2 {
1055					mux {
1056						groups = "tdmc_dout2";
1057						function = "tdmc";
1058						bias-disable;
1059					};
1060				};
1061
1062				tdmc_dout3_pins: tdmc_dout3 {
1063					mux {
1064						groups = "tdmc_dout3";
1065						function = "tdmc";
1066						bias-disable;
1067					};
1068				};
1069
1070				uart_a_pins: uart_a {
1071					mux {
1072						groups = "uart_tx_a",
1073							 "uart_rx_a";
1074						function = "uart_a";
1075						bias-disable;
1076					};
1077				};
1078
1079				uart_a_cts_rts_pins: uart_a_cts_rts {
1080					mux {
1081						groups = "uart_cts_a",
1082							 "uart_rts_a";
1083						function = "uart_a";
1084						bias-disable;
1085					};
1086				};
1087
1088				uart_b_x_pins: uart_b_x {
1089					mux {
1090						groups = "uart_tx_b_x",
1091							 "uart_rx_b_x";
1092						function = "uart_b";
1093						bias-disable;
1094					};
1095				};
1096
1097				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1098					mux {
1099						groups = "uart_cts_b_x",
1100							 "uart_rts_b_x";
1101						function = "uart_b";
1102						bias-disable;
1103					};
1104				};
1105
1106				uart_b_z_pins: uart_b_z {
1107					mux {
1108						groups = "uart_tx_b_z",
1109							 "uart_rx_b_z";
1110						function = "uart_b";
1111						bias-disable;
1112					};
1113				};
1114
1115				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1116					mux {
1117						groups = "uart_cts_b_z",
1118							 "uart_rts_b_z";
1119						function = "uart_b";
1120						bias-disable;
1121					};
1122				};
1123
1124				uart_ao_b_z_pins: uart_ao_b_z {
1125					mux {
1126						groups = "uart_ao_tx_b_z",
1127							 "uart_ao_rx_b_z";
1128						function = "uart_ao_b_z";
1129						bias-disable;
1130					};
1131				};
1132
1133				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1134					mux {
1135						groups = "uart_ao_cts_b_z",
1136							 "uart_ao_rts_b_z";
1137						function = "uart_ao_b_z";
1138						bias-disable;
1139					};
1140				};
1141			};
1142		};
1143
1144		hiubus: bus@ff63c000 {
1145			compatible = "simple-bus";
1146			reg = <0x0 0xff63c000 0x0 0x1c00>;
1147			#address-cells = <2>;
1148			#size-cells = <2>;
1149			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1150
1151			sysctrl: system-controller@0 {
1152				compatible = "amlogic,meson-axg-hhi-sysctrl",
1153					     "simple-mfd", "syscon";
1154				reg = <0 0 0 0x400>;
1155
1156				clkc: clock-controller {
1157					compatible = "amlogic,axg-clkc";
1158					#clock-cells = <1>;
1159					clocks = <&xtal>;
1160					clock-names = "xtal";
1161				};
1162			};
1163		};
1164
1165		mailbox: mailbox@ff63c404 {
1166			compatible = "amlogic,meson-gxbb-mhu";
1167			reg = <0 0xff63c404 0 0x4c>;
1168			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1169				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1170				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1171			#mbox-cells = <1>;
1172		};
1173
1174		audio: bus@ff642000 {
1175			compatible = "simple-bus";
1176			reg = <0x0 0xff642000 0x0 0x2000>;
1177			#address-cells = <2>;
1178			#size-cells = <2>;
1179			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1180
1181			clkc_audio: clock-controller@0 {
1182				compatible = "amlogic,axg-audio-clkc";
1183				reg = <0x0 0x0 0x0 0xb4>;
1184				#clock-cells = <1>;
1185
1186				clocks = <&clkc CLKID_AUDIO>,
1187					 <&clkc CLKID_MPLL0>,
1188					 <&clkc CLKID_MPLL1>,
1189					 <&clkc CLKID_MPLL2>,
1190					 <&clkc CLKID_MPLL3>,
1191					 <&clkc CLKID_HIFI_PLL>,
1192					 <&clkc CLKID_FCLK_DIV3>,
1193					 <&clkc CLKID_FCLK_DIV4>,
1194					 <&clkc CLKID_GP0_PLL>;
1195				clock-names = "pclk",
1196					      "mst_in0",
1197					      "mst_in1",
1198					      "mst_in2",
1199					      "mst_in3",
1200					      "mst_in4",
1201					      "mst_in5",
1202					      "mst_in6",
1203					      "mst_in7";
1204
1205				resets = <&reset RESET_AUDIO>;
1206			};
1207
1208			toddr_a: audio-controller@100 {
1209				compatible = "amlogic,axg-toddr";
1210				reg = <0x0 0x100 0x0 0x2c>;
1211				#sound-dai-cells = <0>;
1212				sound-name-prefix = "TODDR_A";
1213				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1214				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1215				resets = <&arb AXG_ARB_TODDR_A>;
1216				amlogic,fifo-depth = <512>;
1217				status = "disabled";
1218			};
1219
1220			toddr_b: audio-controller@140 {
1221				compatible = "amlogic,axg-toddr";
1222				reg = <0x0 0x140 0x0 0x2c>;
1223				#sound-dai-cells = <0>;
1224				sound-name-prefix = "TODDR_B";
1225				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1226				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1227				resets = <&arb AXG_ARB_TODDR_B>;
1228				amlogic,fifo-depth = <256>;
1229				status = "disabled";
1230			};
1231
1232			toddr_c: audio-controller@180 {
1233				compatible = "amlogic,axg-toddr";
1234				reg = <0x0 0x180 0x0 0x2c>;
1235				#sound-dai-cells = <0>;
1236				sound-name-prefix = "TODDR_C";
1237				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1238				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1239				resets = <&arb AXG_ARB_TODDR_C>;
1240				amlogic,fifo-depth = <256>;
1241				status = "disabled";
1242			};
1243
1244			frddr_a: audio-controller@1c0 {
1245				compatible = "amlogic,axg-frddr";
1246				reg = <0x0 0x1c0 0x0 0x2c>;
1247				#sound-dai-cells = <0>;
1248				sound-name-prefix = "FRDDR_A";
1249				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1250				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1251				resets = <&arb AXG_ARB_FRDDR_A>;
1252				amlogic,fifo-depth = <512>;
1253				status = "disabled";
1254			};
1255
1256			frddr_b: audio-controller@200 {
1257				compatible = "amlogic,axg-frddr";
1258				reg = <0x0 0x200 0x0 0x2c>;
1259				#sound-dai-cells = <0>;
1260				sound-name-prefix = "FRDDR_B";
1261				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1262				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1263				resets = <&arb AXG_ARB_FRDDR_B>;
1264				amlogic,fifo-depth = <256>;
1265				status = "disabled";
1266			};
1267
1268			frddr_c: audio-controller@240 {
1269				compatible = "amlogic,axg-frddr";
1270				reg = <0x0 0x240 0x0 0x2c>;
1271				#sound-dai-cells = <0>;
1272				sound-name-prefix = "FRDDR_C";
1273				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1274				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1275				resets = <&arb AXG_ARB_FRDDR_C>;
1276				amlogic,fifo-depth = <256>;
1277				status = "disabled";
1278			};
1279
1280			arb: reset-controller@280 {
1281				compatible = "amlogic,meson-axg-audio-arb";
1282				reg = <0x0 0x280 0x0 0x4>;
1283				#reset-cells = <1>;
1284				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1285			};
1286
1287			tdmin_a: audio-controller@300 {
1288				compatible = "amlogic,axg-tdmin";
1289				reg = <0x0 0x300 0x0 0x40>;
1290				sound-name-prefix = "TDMIN_A";
1291				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1292					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1293					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1294					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1295					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1296				clock-names = "pclk", "sclk", "sclk_sel",
1297					      "lrclk", "lrclk_sel";
1298				status = "disabled";
1299			};
1300
1301			tdmin_b: audio-controller@340 {
1302				compatible = "amlogic,axg-tdmin";
1303				reg = <0x0 0x340 0x0 0x40>;
1304				sound-name-prefix = "TDMIN_B";
1305				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1306					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1307					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1308					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1309					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1310				clock-names = "pclk", "sclk", "sclk_sel",
1311					      "lrclk", "lrclk_sel";
1312				status = "disabled";
1313			};
1314
1315			tdmin_c: audio-controller@380 {
1316				compatible = "amlogic,axg-tdmin";
1317				reg = <0x0 0x380 0x0 0x40>;
1318				sound-name-prefix = "TDMIN_C";
1319				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1320					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1321					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1322					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1323					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1324				clock-names = "pclk", "sclk", "sclk_sel",
1325					      "lrclk", "lrclk_sel";
1326				status = "disabled";
1327			};
1328
1329			tdmin_lb: audio-controller@3c0 {
1330				compatible = "amlogic,axg-tdmin";
1331				reg = <0x0 0x3c0 0x0 0x40>;
1332				sound-name-prefix = "TDMIN_LB";
1333				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1334					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1335					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1336					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1337					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1338				clock-names = "pclk", "sclk", "sclk_sel",
1339					      "lrclk", "lrclk_sel";
1340				status = "disabled";
1341			};
1342
1343			spdifin: audio-controller@400 {
1344				compatible = "amlogic,axg-spdifin";
1345				reg = <0x0 0x400 0x0 0x30>;
1346				#sound-dai-cells = <0>;
1347				sound-name-prefix = "SPDIFIN";
1348				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1349				clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1350					 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1351				clock-names = "pclk", "refclk";
1352				status = "disabled";
1353			};
1354
1355			spdifout: audio-controller@480 {
1356				compatible = "amlogic,axg-spdifout";
1357				reg = <0x0 0x480 0x0 0x50>;
1358				#sound-dai-cells = <0>;
1359				sound-name-prefix = "SPDIFOUT";
1360				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1361					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1362				clock-names = "pclk", "mclk";
1363				status = "disabled";
1364			};
1365
1366			tdmout_a: audio-controller@500 {
1367				compatible = "amlogic,axg-tdmout";
1368				reg = <0x0 0x500 0x0 0x40>;
1369				sound-name-prefix = "TDMOUT_A";
1370				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1371					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1372					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1373					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1374					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1375				clock-names = "pclk", "sclk", "sclk_sel",
1376					      "lrclk", "lrclk_sel";
1377				status = "disabled";
1378			};
1379
1380			tdmout_b: audio-controller@540 {
1381				compatible = "amlogic,axg-tdmout";
1382				reg = <0x0 0x540 0x0 0x40>;
1383				sound-name-prefix = "TDMOUT_B";
1384				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1385					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1386					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1387					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1388					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1389				clock-names = "pclk", "sclk", "sclk_sel",
1390					      "lrclk", "lrclk_sel";
1391				status = "disabled";
1392			};
1393
1394			tdmout_c: audio-controller@580 {
1395				compatible = "amlogic,axg-tdmout";
1396				reg = <0x0 0x580 0x0 0x40>;
1397				sound-name-prefix = "TDMOUT_C";
1398				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1399					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1400					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1401					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1402					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1403				clock-names = "pclk", "sclk", "sclk_sel",
1404					      "lrclk", "lrclk_sel";
1405				status = "disabled";
1406			};
1407		};
1408
1409		aobus: bus@ff800000 {
1410			compatible = "simple-bus";
1411			reg = <0x0 0xff800000 0x0 0x100000>;
1412			#address-cells = <2>;
1413			#size-cells = <2>;
1414			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1415
1416			sysctrl_AO: sys-ctrl@0 {
1417				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1418				reg =  <0x0 0x0 0x0 0x100>;
1419
1420				clkc_AO: clock-controller {
1421					compatible = "amlogic,meson-axg-aoclkc";
1422					#clock-cells = <1>;
1423					#reset-cells = <1>;
1424					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1425					clock-names = "xtal", "mpeg-clk";
1426				};
1427			};
1428
1429			pinctrl_aobus: pinctrl@14 {
1430				compatible = "amlogic,meson-axg-aobus-pinctrl";
1431				#address-cells = <2>;
1432				#size-cells = <2>;
1433				ranges;
1434
1435				gpio_ao: bank@14 {
1436					reg = <0x0 0x00014 0x0 0x8>,
1437					      <0x0 0x0002c 0x0 0x4>,
1438					      <0x0 0x00024 0x0 0x8>;
1439					reg-names = "mux", "pull", "gpio";
1440					gpio-controller;
1441					#gpio-cells = <2>;
1442					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1443				};
1444
1445				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1446					mux {
1447						groups = "i2c_ao_sck_4";
1448						function = "i2c_ao";
1449						bias-disable;
1450					};
1451				};
1452
1453				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1454					mux {
1455						groups = "i2c_ao_sck_8";
1456						function = "i2c_ao";
1457						bias-disable;
1458					};
1459				};
1460
1461				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1462					mux {
1463						groups = "i2c_ao_sck_10";
1464						function = "i2c_ao";
1465						bias-disable;
1466					};
1467				};
1468
1469				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1470					mux {
1471						groups = "i2c_ao_sda_5";
1472						function = "i2c_ao";
1473						bias-disable;
1474					};
1475				};
1476
1477				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1478					mux {
1479						groups = "i2c_ao_sda_9";
1480						function = "i2c_ao";
1481						bias-disable;
1482					};
1483				};
1484
1485				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1486					mux {
1487						groups = "i2c_ao_sda_11";
1488						function = "i2c_ao";
1489						bias-disable;
1490					};
1491				};
1492
1493				remote_input_ao_pins: remote_input_ao {
1494					mux {
1495						groups = "remote_input_ao";
1496						function = "remote_input_ao";
1497						bias-disable;
1498					};
1499				};
1500
1501				uart_ao_a_pins: uart_ao_a {
1502					mux {
1503						groups = "uart_ao_tx_a",
1504							 "uart_ao_rx_a";
1505						function = "uart_ao_a";
1506						bias-disable;
1507					};
1508				};
1509
1510				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1511					mux {
1512						groups = "uart_ao_cts_a",
1513							 "uart_ao_rts_a";
1514						function = "uart_ao_a";
1515						bias-disable;
1516					};
1517				};
1518
1519				uart_ao_b_pins: uart_ao_b {
1520					mux {
1521						groups = "uart_ao_tx_b",
1522							 "uart_ao_rx_b";
1523						function = "uart_ao_b";
1524						bias-disable;
1525					};
1526				};
1527
1528				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1529					mux {
1530						groups = "uart_ao_cts_b",
1531							 "uart_ao_rts_b";
1532						function = "uart_ao_b";
1533						bias-disable;
1534					};
1535				};
1536			};
1537
1538			sec_AO: ao-secure@140 {
1539				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1540				reg = <0x0 0x140 0x0 0x140>;
1541				amlogic,has-chip-id;
1542			};
1543
1544			pwm_AO_cd: pwm@2000 {
1545				compatible = "amlogic,meson-axg-ao-pwm";
1546				reg = <0x0 0x02000  0x0 0x20>;
1547				#pwm-cells = <3>;
1548				status = "disabled";
1549			};
1550
1551			uart_AO: serial@3000 {
1552				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1553				reg = <0x0 0x3000 0x0 0x18>;
1554				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1555				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1556				clock-names = "xtal", "pclk", "baud";
1557				status = "disabled";
1558			};
1559
1560			uart_AO_B: serial@4000 {
1561				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1562				reg = <0x0 0x4000 0x0 0x18>;
1563				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1564				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1565				clock-names = "xtal", "pclk", "baud";
1566				status = "disabled";
1567			};
1568
1569			i2c_AO: i2c@5000 {
1570				compatible = "amlogic,meson-axg-i2c";
1571				reg = <0x0 0x05000 0x0 0x20>;
1572				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1573				clocks = <&clkc CLKID_AO_I2C>;
1574				#address-cells = <1>;
1575				#size-cells = <0>;
1576				status = "disabled";
1577			};
1578
1579			pwm_AO_ab: pwm@7000 {
1580				compatible = "amlogic,meson-axg-ao-pwm";
1581				reg = <0x0 0x07000 0x0 0x20>;
1582				#pwm-cells = <3>;
1583				status = "disabled";
1584			};
1585
1586			ir: ir@8000 {
1587				compatible = "amlogic,meson-gxbb-ir";
1588				reg = <0x0 0x8000 0x0 0x20>;
1589				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1590				status = "disabled";
1591			};
1592
1593			saradc: adc@9000 {
1594				compatible = "amlogic,meson-axg-saradc",
1595					"amlogic,meson-saradc";
1596				reg = <0x0 0x9000 0x0 0x38>;
1597				#io-channel-cells = <1>;
1598				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1599				clocks = <&xtal>,
1600					 <&clkc_AO CLKID_AO_SAR_ADC>,
1601					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1602					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1603				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1604				status = "disabled";
1605			};
1606		};
1607
1608		gic: interrupt-controller@ffc01000 {
1609			compatible = "arm,gic-400";
1610			reg = <0x0 0xffc01000 0 0x1000>,
1611			      <0x0 0xffc02000 0 0x2000>,
1612			      <0x0 0xffc04000 0 0x2000>,
1613			      <0x0 0xffc06000 0 0x2000>;
1614			interrupt-controller;
1615			interrupts = <GIC_PPI 9
1616				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1617			#interrupt-cells = <3>;
1618			#address-cells = <0>;
1619		};
1620
1621		cbus: bus@ffd00000 {
1622			compatible = "simple-bus";
1623			reg = <0x0 0xffd00000 0x0 0x25000>;
1624			#address-cells = <2>;
1625			#size-cells = <2>;
1626			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1627
1628			reset: reset-controller@1004 {
1629				compatible = "amlogic,meson-axg-reset";
1630				reg = <0x0 0x01004 0x0 0x9c>;
1631				#reset-cells = <1>;
1632			};
1633
1634			gpio_intc: interrupt-controller@f080 {
1635				compatible = "amlogic,meson-axg-gpio-intc",
1636					     "amlogic,meson-gpio-intc";
1637				reg = <0x0 0xf080 0x0 0x10>;
1638				interrupt-controller;
1639				#interrupt-cells = <2>;
1640				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1641			};
1642
1643			watchdog@f0d0 {
1644				compatible = "amlogic,meson-gxbb-wdt";
1645				reg = <0x0 0xf0d0 0x0 0x10>;
1646				clocks = <&xtal>;
1647			};
1648
1649			pwm_ab: pwm@1b000 {
1650				compatible = "amlogic,meson-axg-ee-pwm";
1651				reg = <0x0 0x1b000 0x0 0x20>;
1652				#pwm-cells = <3>;
1653				status = "disabled";
1654			};
1655
1656			pwm_cd: pwm@1a000 {
1657				compatible = "amlogic,meson-axg-ee-pwm";
1658				reg = <0x0 0x1a000 0x0 0x20>;
1659				#pwm-cells = <3>;
1660				status = "disabled";
1661			};
1662
1663			spicc0: spi@13000 {
1664				compatible = "amlogic,meson-axg-spicc";
1665				reg = <0x0 0x13000 0x0 0x3c>;
1666				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1667				clocks = <&clkc CLKID_SPICC0>;
1668				clock-names = "core";
1669				#address-cells = <1>;
1670				#size-cells = <0>;
1671				status = "disabled";
1672			};
1673
1674			spicc1: spi@15000 {
1675				compatible = "amlogic,meson-axg-spicc";
1676				reg = <0x0 0x15000 0x0 0x3c>;
1677				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1678				clocks = <&clkc CLKID_SPICC1>;
1679				clock-names = "core";
1680				#address-cells = <1>;
1681				#size-cells = <0>;
1682				status = "disabled";
1683			};
1684
1685			clk_msr: clock-measure@18000 {
1686				compatible = "amlogic,meson-axg-clk-measure";
1687				reg = <0x0 0x18000 0x0 0x10>;
1688			};
1689
1690			i2c3: i2c@1c000 {
1691				compatible = "amlogic,meson-axg-i2c";
1692				reg = <0x0 0x1c000 0x0 0x20>;
1693				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1694				clocks = <&clkc CLKID_I2C>;
1695				#address-cells = <1>;
1696				#size-cells = <0>;
1697				status = "disabled";
1698			};
1699
1700			i2c2: i2c@1d000 {
1701				compatible = "amlogic,meson-axg-i2c";
1702				reg = <0x0 0x1d000 0x0 0x20>;
1703				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1704				clocks = <&clkc CLKID_I2C>;
1705				#address-cells = <1>;
1706				#size-cells = <0>;
1707				status = "disabled";
1708			};
1709
1710			i2c1: i2c@1e000 {
1711				compatible = "amlogic,meson-axg-i2c";
1712				reg = <0x0 0x1e000 0x0 0x20>;
1713				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1714				clocks = <&clkc CLKID_I2C>;
1715				#address-cells = <1>;
1716				#size-cells = <0>;
1717				status = "disabled";
1718			};
1719
1720			i2c0: i2c@1f000 {
1721				compatible = "amlogic,meson-axg-i2c";
1722				reg = <0x0 0x1f000 0x0 0x20>;
1723				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1724				clocks = <&clkc CLKID_I2C>;
1725				#address-cells = <1>;
1726				#size-cells = <0>;
1727				status = "disabled";
1728			};
1729
1730			uart_B: serial@23000 {
1731				compatible = "amlogic,meson-gx-uart";
1732				reg = <0x0 0x23000 0x0 0x18>;
1733				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1734				status = "disabled";
1735				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1736				clock-names = "xtal", "pclk", "baud";
1737			};
1738
1739			uart_A: serial@24000 {
1740				compatible = "amlogic,meson-gx-uart";
1741				reg = <0x0 0x24000 0x0 0x18>;
1742				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1743				status = "disabled";
1744				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1745				clock-names = "xtal", "pclk", "baud";
1746			};
1747		};
1748
1749		apb: bus@ffe00000 {
1750			compatible = "simple-bus";
1751			reg = <0x0 0xffe00000 0x0 0x200000>;
1752			#address-cells = <2>;
1753			#size-cells = <2>;
1754			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1755
1756			sd_emmc_b: sd@5000 {
1757				compatible = "amlogic,meson-axg-mmc";
1758				reg = <0x0 0x5000 0x0 0x800>;
1759				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1760				status = "disabled";
1761				clocks = <&clkc CLKID_SD_EMMC_B>,
1762					<&clkc CLKID_SD_EMMC_B_CLK0>,
1763					<&clkc CLKID_FCLK_DIV2>;
1764				clock-names = "core", "clkin0", "clkin1";
1765				resets = <&reset RESET_SD_EMMC_B>;
1766			};
1767
1768			sd_emmc_c: mmc@7000 {
1769				compatible = "amlogic,meson-axg-mmc";
1770				reg = <0x0 0x7000 0x0 0x800>;
1771				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1772				status = "disabled";
1773				clocks = <&clkc CLKID_SD_EMMC_C>,
1774					<&clkc CLKID_SD_EMMC_C_CLK0>,
1775					<&clkc CLKID_FCLK_DIV2>;
1776				clock-names = "core", "clkin0", "clkin1";
1777				resets = <&reset RESET_SD_EMMC_C>;
1778			};
1779
1780			usb2_phy1: phy@9020 {
1781				compatible = "amlogic,meson-gxl-usb2-phy";
1782				#phy-cells = <0>;
1783				reg = <0x0 0x9020 0x0 0x20>;
1784				clocks = <&clkc CLKID_USB>;
1785				clock-names = "phy";
1786				resets = <&reset RESET_USB_OTG>;
1787				reset-names = "phy";
1788			};
1789		};
1790
1791		sram: sram@fffc0000 {
1792			compatible = "mmio-sram";
1793			reg = <0x0 0xfffc0000 0x0 0x20000>;
1794			#address-cells = <1>;
1795			#size-cells = <1>;
1796			ranges = <0 0x0 0xfffc0000 0x20000>;
1797
1798			cpu_scp_lpri: scp-sram@13000 {
1799				compatible = "amlogic,meson-axg-scp-shmem";
1800				reg = <0x13000 0x400>;
1801			};
1802
1803			cpu_scp_hpri: scp-sram@13400 {
1804				compatible = "amlogic,meson-axg-scp-shmem";
1805				reg = <0x13400 0x400>;
1806			};
1807		};
1808	};
1809
1810	timer {
1811		compatible = "arm,armv8-timer";
1812		interrupts = <GIC_PPI 13
1813			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1814			     <GIC_PPI 14
1815			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1816			     <GIC_PPI 11
1817			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1818			     <GIC_PPI 10
1819			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1820	};
1821
1822	xtal: xtal-clk {
1823		compatible = "fixed-clock";
1824		clock-frequency = <24000000>;
1825		clock-output-names = "xtal";
1826		#clock-cells = <0>;
1827	};
1828};
1829