1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-audio-clkc.h> 10#include <dt-bindings/clock/axg-clkc.h> 11#include <dt-bindings/clock/axg-aoclkc.h> 12#include <dt-bindings/gpio/meson-axg-gpio.h> 13#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 14#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 /* 16 MiB reserved for Hardware ROM Firmware */ 29 hwrom_reserved: hwrom@0 { 30 reg = <0x0 0x0 0x0 0x1000000>; 31 no-map; 32 }; 33 34 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 35 secmon_reserved: secmon@5000000 { 36 reg = <0x0 0x05000000 0x0 0x300000>; 37 no-map; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <0x2>; 43 #size-cells = <0x0>; 44 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&l2>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53", "arm,armv8"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 }; 60 61 cpu2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53", "arm,armv8"; 64 reg = <0x0 0x2>; 65 enable-method = "psci"; 66 next-level-cache = <&l2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0x0 0x3>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 }; 76 77 l2: l2-cache0 { 78 compatible = "cache"; 79 }; 80 }; 81 82 arm-pmu { 83 compatible = "arm,cortex-a53-pmu"; 84 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 89 }; 90 91 psci { 92 compatible = "arm,psci-1.0"; 93 method = "smc"; 94 }; 95 96 tdmif_a: audio-controller@0 { 97 compatible = "amlogic,axg-tdm-iface"; 98 #sound-dai-cells = <0>; 99 sound-name-prefix = "TDM_A"; 100 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 101 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 102 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 103 clock-names = "mclk", "sclk", "lrclk"; 104 status = "disabled"; 105 }; 106 107 tdmif_b: audio-controller@1 { 108 compatible = "amlogic,axg-tdm-iface"; 109 #sound-dai-cells = <0>; 110 sound-name-prefix = "TDM_B"; 111 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 112 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 113 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 114 clock-names = "mclk", "sclk", "lrclk"; 115 status = "disabled"; 116 }; 117 118 tdmif_c: audio-controller@2 { 119 compatible = "amlogic,axg-tdm-iface"; 120 #sound-dai-cells = <0>; 121 sound-name-prefix = "TDM_C"; 122 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 123 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 124 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 125 clock-names = "mclk", "sclk", "lrclk"; 126 status = "disabled"; 127 }; 128 129 timer { 130 compatible = "arm,armv8-timer"; 131 interrupts = <GIC_PPI 13 132 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 14 134 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 136 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 10 138 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 139 }; 140 141 xtal: xtal-clk { 142 compatible = "fixed-clock"; 143 clock-frequency = <24000000>; 144 clock-output-names = "xtal"; 145 #clock-cells = <0>; 146 }; 147 148 ao_alt_xtal: ao_alt_xtal-clk { 149 compatible = "fixed-clock"; 150 clock-frequency = <32000000>; 151 clock-output-names = "ao_alt_xtal"; 152 #clock-cells = <0>; 153 }; 154 155 soc { 156 compatible = "simple-bus"; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 apb: apb@ffe00000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xffe00000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 167 168 sd_emmc_b: sd@5000 { 169 compatible = "amlogic,meson-axg-mmc"; 170 reg = <0x0 0x5000 0x0 0x800>; 171 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 172 status = "disabled"; 173 clocks = <&clkc CLKID_SD_EMMC_B>, 174 <&clkc CLKID_SD_EMMC_B_CLK0>, 175 <&clkc CLKID_FCLK_DIV2>; 176 clock-names = "core", "clkin0", "clkin1"; 177 resets = <&reset RESET_SD_EMMC_B>; 178 }; 179 180 sd_emmc_c: mmc@7000 { 181 compatible = "amlogic,meson-axg-mmc"; 182 reg = <0x0 0x7000 0x0 0x800>; 183 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 184 status = "disabled"; 185 clocks = <&clkc CLKID_SD_EMMC_C>, 186 <&clkc CLKID_SD_EMMC_C_CLK0>, 187 <&clkc CLKID_FCLK_DIV2>; 188 clock-names = "core", "clkin0", "clkin1"; 189 resets = <&reset RESET_SD_EMMC_C>; 190 }; 191 }; 192 193 audio: bus@ff642000 { 194 compatible = "simple-bus"; 195 reg = <0x0 0xff642000 0x0 0x2000>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 199 200 clkc_audio: clock-controller@0 { 201 compatible = "amlogic,axg-audio-clkc"; 202 reg = <0x0 0x0 0x0 0xb4>; 203 #clock-cells = <1>; 204 205 clocks = <&clkc CLKID_AUDIO>, 206 <&clkc CLKID_MPLL0>, 207 <&clkc CLKID_MPLL1>, 208 <&clkc CLKID_MPLL2>, 209 <&clkc CLKID_MPLL3>, 210 <&clkc CLKID_HIFI_PLL>, 211 <&clkc CLKID_FCLK_DIV3>, 212 <&clkc CLKID_FCLK_DIV4>, 213 <&clkc CLKID_GP0_PLL>; 214 clock-names = "pclk", 215 "mst_in0", 216 "mst_in1", 217 "mst_in2", 218 "mst_in3", 219 "mst_in4", 220 "mst_in5", 221 "mst_in6", 222 "mst_in7"; 223 224 resets = <&reset RESET_AUDIO>; 225 }; 226 227 toddr_a: audio-controller@100 { 228 compatible = "amlogic,axg-toddr"; 229 reg = <0x0 0x100 0x0 0x1c>; 230 #sound-dai-cells = <0>; 231 sound-name-prefix = "TODDR_A"; 232 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 233 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 234 resets = <&arb AXG_ARB_TODDR_A>; 235 status = "disabled"; 236 }; 237 238 toddr_b: audio-controller@140 { 239 compatible = "amlogic,axg-toddr"; 240 reg = <0x0 0x140 0x0 0x1c>; 241 #sound-dai-cells = <0>; 242 sound-name-prefix = "TODDR_B"; 243 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 244 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 245 resets = <&arb AXG_ARB_TODDR_B>; 246 status = "disabled"; 247 }; 248 249 toddr_c: audio-controller@180 { 250 compatible = "amlogic,axg-toddr"; 251 reg = <0x0 0x180 0x0 0x1c>; 252 #sound-dai-cells = <0>; 253 sound-name-prefix = "TODDR_C"; 254 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 255 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 256 resets = <&arb AXG_ARB_TODDR_C>; 257 status = "disabled"; 258 }; 259 260 frddr_a: audio-controller@1c0 { 261 compatible = "amlogic,axg-frddr"; 262 reg = <0x0 0x1c0 0x0 0x1c>; 263 #sound-dai-cells = <0>; 264 sound-name-prefix = "FRDDR_A"; 265 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 266 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 267 resets = <&arb AXG_ARB_FRDDR_A>; 268 status = "disabled"; 269 }; 270 271 frddr_b: audio-controller@200 { 272 compatible = "amlogic,axg-frddr"; 273 reg = <0x0 0x200 0x0 0x1c>; 274 #sound-dai-cells = <0>; 275 sound-name-prefix = "FRDDR_B"; 276 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 277 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 278 resets = <&arb AXG_ARB_FRDDR_B>; 279 status = "disabled"; 280 }; 281 282 frddr_c: audio-controller@240 { 283 compatible = "amlogic,axg-frddr"; 284 reg = <0x0 0x240 0x0 0x1c>; 285 #sound-dai-cells = <0>; 286 sound-name-prefix = "FRDDR_C"; 287 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 288 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 289 resets = <&arb AXG_ARB_FRDDR_C>; 290 status = "disabled"; 291 }; 292 293 arb: reset-controller@280 { 294 compatible = "amlogic,meson-axg-audio-arb"; 295 reg = <0x0 0x280 0x0 0x4>; 296 #reset-cells = <1>; 297 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 298 }; 299 300 tdmin_a: audio-controller@300 { 301 compatible = "amlogic,axg-tdmin"; 302 reg = <0x0 0x300 0x0 0x40>; 303 sound-name-prefix = "TDMIN_A"; 304 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 305 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 306 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 307 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 308 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 309 clock-names = "pclk", "sclk", "sclk_sel", 310 "lrclk", "lrclk_sel"; 311 status = "disabled"; 312 }; 313 314 tdmin_b: audio-controller@340 { 315 compatible = "amlogic,axg-tdmin"; 316 reg = <0x0 0x340 0x0 0x40>; 317 sound-name-prefix = "TDMIN_B"; 318 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 319 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 320 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 321 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 322 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 323 clock-names = "pclk", "sclk", "sclk_sel", 324 "lrclk", "lrclk_sel"; 325 status = "disabled"; 326 }; 327 328 tdmin_c: audio-controller@380 { 329 compatible = "amlogic,axg-tdmin"; 330 reg = <0x0 0x380 0x0 0x40>; 331 sound-name-prefix = "TDMIN_C"; 332 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 333 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 334 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 335 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 336 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 337 clock-names = "pclk", "sclk", "sclk_sel", 338 "lrclk", "lrclk_sel"; 339 status = "disabled"; 340 }; 341 342 tdmin_lb: audio-controller@3c0 { 343 compatible = "amlogic,axg-tdmin"; 344 reg = <0x0 0x3c0 0x0 0x40>; 345 sound-name-prefix = "TDMIN_LB"; 346 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 347 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 348 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 349 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 350 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 351 clock-names = "pclk", "sclk", "sclk_sel", 352 "lrclk", "lrclk_sel"; 353 status = "disabled"; 354 }; 355 356 spdifout: audio-controller@480 { 357 compatible = "amlogic,axg-spdifout"; 358 reg = <0x0 0x480 0x0 0x50>; 359 #sound-dai-cells = <0>; 360 sound-name-prefix = "SPDIFOUT"; 361 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 362 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 363 clock-names = "pclk", "mclk"; 364 status = "disabled"; 365 }; 366 367 tdmout_a: audio-controller@500 { 368 compatible = "amlogic,axg-tdmout"; 369 reg = <0x0 0x500 0x0 0x40>; 370 sound-name-prefix = "TDMOUT_A"; 371 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 372 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 373 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 374 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 375 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 376 clock-names = "pclk", "sclk", "sclk_sel", 377 "lrclk", "lrclk_sel"; 378 status = "disabled"; 379 }; 380 381 tdmout_b: audio-controller@540 { 382 compatible = "amlogic,axg-tdmout"; 383 reg = <0x0 0x540 0x0 0x40>; 384 sound-name-prefix = "TDMOUT_B"; 385 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 386 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 387 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 388 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 389 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 390 clock-names = "pclk", "sclk", "sclk_sel", 391 "lrclk", "lrclk_sel"; 392 status = "disabled"; 393 }; 394 395 tdmout_c: audio-controller@580 { 396 compatible = "amlogic,axg-tdmout"; 397 reg = <0x0 0x580 0x0 0x40>; 398 sound-name-prefix = "TDMOUT_C"; 399 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 400 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 401 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 402 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 403 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 404 clock-names = "pclk", "sclk", "sclk_sel", 405 "lrclk", "lrclk_sel"; 406 status = "disabled"; 407 }; 408 }; 409 410 cbus: bus@ffd00000 { 411 compatible = "simple-bus"; 412 reg = <0x0 0xffd00000 0x0 0x25000>; 413 #address-cells = <2>; 414 #size-cells = <2>; 415 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 416 417 gpio_intc: interrupt-controller@f080 { 418 compatible = "amlogic,meson-gpio-intc"; 419 reg = <0x0 0xf080 0x0 0x10>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 423 status = "disabled"; 424 }; 425 426 pwm_ab: pwm@1b000 { 427 compatible = "amlogic,meson-axg-ee-pwm"; 428 reg = <0x0 0x1b000 0x0 0x20>; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 pwm_cd: pwm@1a000 { 434 compatible = "amlogic,meson-axg-ee-pwm"; 435 reg = <0x0 0x1a000 0x0 0x20>; 436 #pwm-cells = <3>; 437 status = "disabled"; 438 }; 439 440 reset: reset-controller@1004 { 441 compatible = "amlogic,meson-axg-reset"; 442 reg = <0x0 0x01004 0x0 0x9c>; 443 #reset-cells = <1>; 444 }; 445 446 spicc0: spi@13000 { 447 compatible = "amlogic,meson-axg-spicc"; 448 reg = <0x0 0x13000 0x0 0x3c>; 449 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clkc CLKID_SPICC0>; 451 clock-names = "core"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 spicc1: spi@15000 { 458 compatible = "amlogic,meson-axg-spicc"; 459 reg = <0x0 0x15000 0x0 0x3c>; 460 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clkc CLKID_SPICC1>; 462 clock-names = "core"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c0: i2c@1f000 { 469 compatible = "amlogic,meson-axg-i2c"; 470 reg = <0x0 0x1f000 0x0 0x20>; 471 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 472 clocks = <&clkc CLKID_I2C>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 i2c1: i2c@1e000 { 479 compatible = "amlogic,meson-axg-i2c"; 480 reg = <0x0 0x1e000 0x0 0x20>; 481 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 482 clocks = <&clkc CLKID_I2C>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@1d000 { 489 compatible = "amlogic,meson-axg-i2c"; 490 reg = <0x0 0x1d000 0x0 0x20>; 491 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 492 clocks = <&clkc CLKID_I2C>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 i2c3: i2c@1c000 { 499 compatible = "amlogic,meson-axg-i2c"; 500 reg = <0x0 0x1c000 0x0 0x20>; 501 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 502 clocks = <&clkc CLKID_I2C>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 uart_A: serial@24000 { 509 compatible = "amlogic,meson-gx-uart"; 510 reg = <0x0 0x24000 0x0 0x18>; 511 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 512 status = "disabled"; 513 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 514 clock-names = "xtal", "pclk", "baud"; 515 }; 516 517 uart_B: serial@23000 { 518 compatible = "amlogic,meson-gx-uart"; 519 reg = <0x0 0x23000 0x0 0x18>; 520 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 521 status = "disabled"; 522 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 523 clock-names = "xtal", "pclk", "baud"; 524 }; 525 }; 526 527 ethmac: ethernet@ff3f0000 { 528 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 529 reg = <0x0 0xff3f0000 0x0 0x10000 530 0x0 0xff634540 0x0 0x8>; 531 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 532 interrupt-names = "macirq"; 533 clocks = <&clkc CLKID_ETH>, 534 <&clkc CLKID_FCLK_DIV2>, 535 <&clkc CLKID_MPLL2>; 536 clock-names = "stmmaceth", "clkin0", "clkin1"; 537 status = "disabled"; 538 }; 539 540 gic: interrupt-controller@ffc01000 { 541 compatible = "arm,gic-400"; 542 reg = <0x0 0xffc01000 0 0x1000>, 543 <0x0 0xffc02000 0 0x2000>, 544 <0x0 0xffc04000 0 0x2000>, 545 <0x0 0xffc06000 0 0x2000>; 546 interrupt-controller; 547 interrupts = <GIC_PPI 9 548 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 549 #interrupt-cells = <3>; 550 #address-cells = <0>; 551 }; 552 553 hiubus: bus@ff63c000 { 554 compatible = "simple-bus"; 555 reg = <0x0 0xff63c000 0x0 0x1c00>; 556 #address-cells = <2>; 557 #size-cells = <2>; 558 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 559 560 sysctrl: system-controller@0 { 561 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 562 reg = <0 0 0 0x400>; 563 564 clkc: clock-controller { 565 compatible = "amlogic,axg-clkc"; 566 #clock-cells = <1>; 567 }; 568 }; 569 }; 570 571 mailbox: mailbox@ff63dc00 { 572 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 573 reg = <0 0xff63dc00 0 0x400>; 574 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 577 #mbox-cells = <1>; 578 }; 579 580 periphs: periphs@ff634000 { 581 compatible = "simple-bus"; 582 reg = <0x0 0xff634000 0x0 0x2000>; 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 586 587 hwrng: rng { 588 compatible = "amlogic,meson-rng"; 589 reg = <0x0 0x18 0x0 0x4>; 590 clocks = <&clkc CLKID_RNG0>; 591 clock-names = "core"; 592 }; 593 594 pinctrl_periphs: pinctrl@480 { 595 compatible = "amlogic,meson-axg-periphs-pinctrl"; 596 #address-cells = <2>; 597 #size-cells = <2>; 598 ranges; 599 600 gpio: bank@480 { 601 reg = <0x0 0x00480 0x0 0x40>, 602 <0x0 0x004e8 0x0 0x14>, 603 <0x0 0x00520 0x0 0x14>, 604 <0x0 0x00430 0x0 0x3c>; 605 reg-names = "mux", "pull", "pull-enable", "gpio"; 606 gpio-controller; 607 #gpio-cells = <2>; 608 gpio-ranges = <&pinctrl_periphs 0 0 86>; 609 }; 610 611 emmc_pins: emmc { 612 mux { 613 groups = "emmc_nand_d0", 614 "emmc_nand_d1", 615 "emmc_nand_d2", 616 "emmc_nand_d3", 617 "emmc_nand_d4", 618 "emmc_nand_d5", 619 "emmc_nand_d6", 620 "emmc_nand_d7", 621 "emmc_clk", 622 "emmc_cmd", 623 "emmc_ds"; 624 function = "emmc"; 625 }; 626 }; 627 628 emmc_clk_gate_pins: emmc_clk_gate { 629 mux { 630 groups = "BOOT_8"; 631 function = "gpio_periphs"; 632 }; 633 cfg-pull-down { 634 pins = "BOOT_8"; 635 bias-pull-down; 636 }; 637 }; 638 639 sdio_pins: sdio { 640 mux { 641 groups = "sdio_d0", 642 "sdio_d1", 643 "sdio_d2", 644 "sdio_d3", 645 "sdio_cmd", 646 "sdio_clk"; 647 function = "sdio"; 648 }; 649 }; 650 651 sdio_clk_gate_pins: sdio_clk_gate { 652 mux { 653 groups = "GPIOX_4"; 654 function = "gpio_periphs"; 655 }; 656 cfg-pull-down { 657 pins = "GPIOX_4"; 658 bias-pull-down; 659 }; 660 }; 661 662 eth_rmii_x_pins: eth-x-rmii { 663 mux { 664 groups = "eth_mdio_x", 665 "eth_mdc_x", 666 "eth_rgmii_rx_clk_x", 667 "eth_rx_dv_x", 668 "eth_rxd0_x", 669 "eth_rxd1_x", 670 "eth_txen_x", 671 "eth_txd0_x", 672 "eth_txd1_x"; 673 function = "eth"; 674 }; 675 }; 676 677 eth_rmii_y_pins: eth-y-rmii { 678 mux { 679 groups = "eth_mdio_y", 680 "eth_mdc_y", 681 "eth_rgmii_rx_clk_y", 682 "eth_rx_dv_y", 683 "eth_rxd0_y", 684 "eth_rxd1_y", 685 "eth_txen_y", 686 "eth_txd0_y", 687 "eth_txd1_y"; 688 function = "eth"; 689 }; 690 }; 691 692 eth_rgmii_x_pins: eth-x-rgmii { 693 mux { 694 groups = "eth_mdio_x", 695 "eth_mdc_x", 696 "eth_rgmii_rx_clk_x", 697 "eth_rx_dv_x", 698 "eth_rxd0_x", 699 "eth_rxd1_x", 700 "eth_rxd2_rgmii", 701 "eth_rxd3_rgmii", 702 "eth_rgmii_tx_clk", 703 "eth_txen_x", 704 "eth_txd0_x", 705 "eth_txd1_x", 706 "eth_txd2_rgmii", 707 "eth_txd3_rgmii"; 708 function = "eth"; 709 }; 710 }; 711 712 eth_rgmii_y_pins: eth-y-rgmii { 713 mux { 714 groups = "eth_mdio_y", 715 "eth_mdc_y", 716 "eth_rgmii_rx_clk_y", 717 "eth_rx_dv_y", 718 "eth_rxd0_y", 719 "eth_rxd1_y", 720 "eth_rxd2_rgmii", 721 "eth_rxd3_rgmii", 722 "eth_rgmii_tx_clk", 723 "eth_txen_y", 724 "eth_txd0_y", 725 "eth_txd1_y", 726 "eth_txd2_rgmii", 727 "eth_txd3_rgmii"; 728 function = "eth"; 729 }; 730 }; 731 732 pdm_dclk_a14_pins: pdm_dclk_a14 { 733 mux { 734 groups = "pdm_dclk_a14"; 735 function = "pdm"; 736 }; 737 }; 738 739 pdm_dclk_a19_pins: pdm_dclk_a19 { 740 mux { 741 groups = "pdm_dclk_a19"; 742 function = "pdm"; 743 }; 744 }; 745 746 pdm_din0_pins: pdm_din0 { 747 mux { 748 groups = "pdm_din0"; 749 function = "pdm"; 750 }; 751 }; 752 753 pdm_din1_pins: pdm_din1 { 754 mux { 755 groups = "pdm_din1"; 756 function = "pdm"; 757 }; 758 }; 759 760 pdm_din2_pins: pdm_din2 { 761 mux { 762 groups = "pdm_din2"; 763 function = "pdm"; 764 }; 765 }; 766 767 pdm_din3_pins: pdm_din3 { 768 mux { 769 groups = "pdm_din3"; 770 function = "pdm"; 771 }; 772 }; 773 774 pwm_a_a_pins: pwm_a_a { 775 mux { 776 groups = "pwm_a_a"; 777 function = "pwm_a"; 778 }; 779 }; 780 781 pwm_a_x18_pins: pwm_a_x18 { 782 mux { 783 groups = "pwm_a_x18"; 784 function = "pwm_a"; 785 }; 786 }; 787 788 pwm_a_x20_pins: pwm_a_x20 { 789 mux { 790 groups = "pwm_a_x20"; 791 function = "pwm_a"; 792 }; 793 }; 794 795 pwm_a_z_pins: pwm_a_z { 796 mux { 797 groups = "pwm_a_z"; 798 function = "pwm_a"; 799 }; 800 }; 801 802 pwm_b_a_pins: pwm_b_a { 803 mux { 804 groups = "pwm_b_a"; 805 function = "pwm_b"; 806 }; 807 }; 808 809 pwm_b_x_pins: pwm_b_x { 810 mux { 811 groups = "pwm_b_x"; 812 function = "pwm_b"; 813 }; 814 }; 815 816 pwm_b_z_pins: pwm_b_z { 817 mux { 818 groups = "pwm_b_z"; 819 function = "pwm_b"; 820 }; 821 }; 822 823 pwm_c_a_pins: pwm_c_a { 824 mux { 825 groups = "pwm_c_a"; 826 function = "pwm_c"; 827 }; 828 }; 829 830 pwm_c_x10_pins: pwm_c_x10 { 831 mux { 832 groups = "pwm_c_x10"; 833 function = "pwm_c"; 834 }; 835 }; 836 837 pwm_c_x17_pins: pwm_c_x17 { 838 mux { 839 groups = "pwm_c_x17"; 840 function = "pwm_c"; 841 }; 842 }; 843 844 pwm_d_x11_pins: pwm_d_x11 { 845 mux { 846 groups = "pwm_d_x11"; 847 function = "pwm_d"; 848 }; 849 }; 850 851 pwm_d_x16_pins: pwm_d_x16 { 852 mux { 853 groups = "pwm_d_x16"; 854 function = "pwm_d"; 855 }; 856 }; 857 858 spdif_in_z_pins: spdif_in_z { 859 mux { 860 groups = "spdif_in_z"; 861 function = "spdif_in"; 862 }; 863 }; 864 865 spdif_in_a1_pins: spdif_in_a1 { 866 mux { 867 groups = "spdif_in_a1"; 868 function = "spdif_in"; 869 }; 870 }; 871 872 spdif_in_a7_pins: spdif_in_a7 { 873 mux { 874 groups = "spdif_in_a7"; 875 function = "spdif_in"; 876 }; 877 }; 878 879 spdif_in_a19_pins: spdif_in_a19 { 880 mux { 881 groups = "spdif_in_a19"; 882 function = "spdif_in"; 883 }; 884 }; 885 886 spdif_in_a20_pins: spdif_in_a20 { 887 mux { 888 groups = "spdif_in_a20"; 889 function = "spdif_in"; 890 }; 891 }; 892 893 spdif_out_z_pins: spdif_out_z { 894 mux { 895 groups = "spdif_out_z"; 896 function = "spdif_out"; 897 }; 898 }; 899 900 spdif_out_a1_pins: spdif_out_a1 { 901 mux { 902 groups = "spdif_out_a1"; 903 function = "spdif_out"; 904 }; 905 }; 906 907 spdif_out_a11_pins: spdif_out_a11 { 908 mux { 909 groups = "spdif_out_a11"; 910 function = "spdif_out"; 911 }; 912 }; 913 914 spdif_out_a19_pins: spdif_out_a19 { 915 mux { 916 groups = "spdif_out_a19"; 917 function = "spdif_out"; 918 }; 919 }; 920 921 spdif_out_a20_pins: spdif_out_a20 { 922 mux { 923 groups = "spdif_out_a20"; 924 function = "spdif_out"; 925 }; 926 }; 927 928 spi0_pins: spi0 { 929 mux { 930 groups = "spi0_miso", 931 "spi0_mosi", 932 "spi0_clk"; 933 function = "spi0"; 934 }; 935 }; 936 937 spi0_ss0_pins: spi0_ss0 { 938 mux { 939 groups = "spi0_ss0"; 940 function = "spi0"; 941 }; 942 }; 943 944 spi0_ss1_pins: spi0_ss1 { 945 mux { 946 groups = "spi0_ss1"; 947 function = "spi0"; 948 }; 949 }; 950 951 spi0_ss2_pins: spi0_ss2 { 952 mux { 953 groups = "spi0_ss2"; 954 function = "spi0"; 955 }; 956 }; 957 958 959 spi1_a_pins: spi1_a { 960 mux { 961 groups = "spi1_miso_a", 962 "spi1_mosi_a", 963 "spi1_clk_a"; 964 function = "spi1"; 965 }; 966 }; 967 968 spi1_ss0_a_pins: spi1_ss0_a { 969 mux { 970 groups = "spi1_ss0_a"; 971 function = "spi1"; 972 }; 973 }; 974 975 spi1_ss1_pins: spi1_ss1 { 976 mux { 977 groups = "spi1_ss1"; 978 function = "spi1"; 979 }; 980 }; 981 982 spi1_x_pins: spi1_x { 983 mux { 984 groups = "spi1_miso_x", 985 "spi1_mosi_x", 986 "spi1_clk_x"; 987 function = "spi1"; 988 }; 989 }; 990 991 spi1_ss0_x_pins: spi1_ss0_x { 992 mux { 993 groups = "spi1_ss0_x"; 994 function = "spi1"; 995 }; 996 }; 997 998 i2c0_pins: i2c0 { 999 mux { 1000 groups = "i2c0_sck", 1001 "i2c0_sda"; 1002 function = "i2c0"; 1003 }; 1004 }; 1005 1006 i2c1_z_pins: i2c1_z { 1007 mux { 1008 groups = "i2c1_sck_z", 1009 "i2c1_sda_z"; 1010 function = "i2c1"; 1011 }; 1012 }; 1013 1014 i2c1_x_pins: i2c1_x { 1015 mux { 1016 groups = "i2c1_sck_x", 1017 "i2c1_sda_x"; 1018 function = "i2c1"; 1019 }; 1020 }; 1021 1022 i2c2_x_pins: i2c2_x { 1023 mux { 1024 groups = "i2c2_sck_x", 1025 "i2c2_sda_x"; 1026 function = "i2c2"; 1027 }; 1028 }; 1029 1030 i2c2_a_pins: i2c2_a { 1031 mux { 1032 groups = "i2c2_sck_a", 1033 "i2c2_sda_a"; 1034 function = "i2c2"; 1035 }; 1036 }; 1037 1038 i2c3_a6_pins: i2c3_a6 { 1039 mux { 1040 groups = "i2c3_sda_a6", 1041 "i2c3_sck_a7"; 1042 function = "i2c3"; 1043 }; 1044 }; 1045 1046 i2c3_a12_pins: i2c3_a12 { 1047 mux { 1048 groups = "i2c3_sda_a12", 1049 "i2c3_sck_a13"; 1050 function = "i2c3"; 1051 }; 1052 }; 1053 1054 i2c3_a19_pins: i2c3_a19 { 1055 mux { 1056 groups = "i2c3_sda_a19", 1057 "i2c3_sck_a20"; 1058 function = "i2c3"; 1059 }; 1060 }; 1061 1062 uart_a_pins: uart_a { 1063 mux { 1064 groups = "uart_tx_a", 1065 "uart_rx_a"; 1066 function = "uart_a"; 1067 }; 1068 }; 1069 1070 uart_a_cts_rts_pins: uart_a_cts_rts { 1071 mux { 1072 groups = "uart_cts_a", 1073 "uart_rts_a"; 1074 function = "uart_a"; 1075 }; 1076 }; 1077 1078 uart_b_x_pins: uart_b_x { 1079 mux { 1080 groups = "uart_tx_b_x", 1081 "uart_rx_b_x"; 1082 function = "uart_b"; 1083 }; 1084 }; 1085 1086 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1087 mux { 1088 groups = "uart_cts_b_x", 1089 "uart_rts_b_x"; 1090 function = "uart_b"; 1091 }; 1092 }; 1093 1094 uart_b_z_pins: uart_b_z { 1095 mux { 1096 groups = "uart_tx_b_z", 1097 "uart_rx_b_z"; 1098 function = "uart_b"; 1099 }; 1100 }; 1101 1102 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1103 mux { 1104 groups = "uart_cts_b_z", 1105 "uart_rts_b_z"; 1106 function = "uart_b"; 1107 }; 1108 }; 1109 1110 uart_ao_b_z_pins: uart_ao_b_z { 1111 mux { 1112 groups = "uart_ao_tx_b_z", 1113 "uart_ao_rx_b_z"; 1114 function = "uart_ao_b_z"; 1115 }; 1116 }; 1117 1118 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1119 mux { 1120 groups = "uart_ao_cts_b_z", 1121 "uart_ao_rts_b_z"; 1122 function = "uart_ao_b_z"; 1123 }; 1124 }; 1125 1126 mclk_b_pins: mclk_b { 1127 mux { 1128 groups = "mclk_b"; 1129 function = "mclk_b"; 1130 }; 1131 }; 1132 1133 mclk_c_pins: mclk_c { 1134 mux { 1135 groups = "mclk_c"; 1136 function = "mclk_c"; 1137 }; 1138 }; 1139 1140 tdma_sclk_pins: tdma_sclk { 1141 mux { 1142 groups = "tdma_sclk"; 1143 function = "tdma"; 1144 }; 1145 }; 1146 1147 tdma_sclk_slv_pins: tdma_sclk_slv { 1148 mux { 1149 groups = "tdma_sclk_slv"; 1150 function = "tdma"; 1151 }; 1152 }; 1153 1154 tdma_fs_pins: tdma_fs { 1155 mux { 1156 groups = "tdma_fs"; 1157 function = "tdma"; 1158 }; 1159 }; 1160 1161 tdma_fs_slv_pins: tdma_fs_slv { 1162 mux { 1163 groups = "tdma_fs_slv"; 1164 function = "tdma"; 1165 }; 1166 }; 1167 1168 tdma_din0_pins: tdma_din0 { 1169 mux { 1170 groups = "tdma_din0"; 1171 function = "tdma"; 1172 }; 1173 }; 1174 1175 tdma_dout0_x14_pins: tdma_dout0_x14 { 1176 mux { 1177 groups = "tdma_dout0_x14"; 1178 function = "tdma"; 1179 }; 1180 }; 1181 1182 tdma_dout0_x15_pins: tdma_dout0_x15 { 1183 mux { 1184 groups = "tdma_dout0_x15"; 1185 function = "tdma"; 1186 }; 1187 }; 1188 1189 tdma_dout1_pins: tdma_dout1 { 1190 mux { 1191 groups = "tdma_dout1"; 1192 function = "tdma"; 1193 }; 1194 }; 1195 1196 tdma_din1_pins: tdma_din1 { 1197 mux { 1198 groups = "tdma_din1"; 1199 function = "tdma"; 1200 }; 1201 }; 1202 1203 tdmb_sclk_pins: tdmb_sclk { 1204 mux { 1205 groups = "tdmb_sclk"; 1206 function = "tdmb"; 1207 }; 1208 }; 1209 1210 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1211 mux { 1212 groups = "tdmb_sclk_slv"; 1213 function = "tdmb"; 1214 }; 1215 }; 1216 1217 tdmb_fs_pins: tdmb_fs { 1218 mux { 1219 groups = "tdmb_fs"; 1220 function = "tdmb"; 1221 }; 1222 }; 1223 1224 tdmb_fs_slv_pins: tdmb_fs_slv { 1225 mux { 1226 groups = "tdmb_fs_slv"; 1227 function = "tdmb"; 1228 }; 1229 }; 1230 1231 tdmb_din0_pins: tdmb_din0 { 1232 mux { 1233 groups = "tdmb_din0"; 1234 function = "tdmb"; 1235 }; 1236 }; 1237 1238 tdmb_dout0_pins: tdmb_dout0 { 1239 mux { 1240 groups = "tdmb_dout0"; 1241 function = "tdmb"; 1242 }; 1243 }; 1244 1245 tdmb_din1_pins: tdmb_din1 { 1246 mux { 1247 groups = "tdmb_din1"; 1248 function = "tdmb"; 1249 }; 1250 }; 1251 1252 tdmb_dout1_pins: tdmb_dout1 { 1253 mux { 1254 groups = "tdmb_dout1"; 1255 function = "tdmb"; 1256 }; 1257 }; 1258 1259 tdmb_din2_pins: tdmb_din2 { 1260 mux { 1261 groups = "tdmb_din2"; 1262 function = "tdmb"; 1263 }; 1264 }; 1265 1266 tdmb_dout2_pins: tdmb_dout2 { 1267 mux { 1268 groups = "tdmb_dout2"; 1269 function = "tdmb"; 1270 }; 1271 }; 1272 1273 tdmb_din3_pins: tdmb_din3 { 1274 mux { 1275 groups = "tdmb_din3"; 1276 function = "tdmb"; 1277 }; 1278 }; 1279 1280 tdmb_dout3_pins: tdmb_dout3 { 1281 mux { 1282 groups = "tdmb_dout3"; 1283 function = "tdmb"; 1284 }; 1285 }; 1286 1287 tdmc_sclk_pins: tdmc_sclk { 1288 mux { 1289 groups = "tdmc_sclk"; 1290 function = "tdmc"; 1291 }; 1292 }; 1293 1294 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1295 mux { 1296 groups = "tdmc_sclk_slv"; 1297 function = "tdmc"; 1298 }; 1299 }; 1300 1301 tdmc_fs_pins: tdmc_fs { 1302 mux { 1303 groups = "tdmc_fs"; 1304 function = "tdmc"; 1305 }; 1306 }; 1307 1308 tdmc_fs_slv_pins: tdmc_fs_slv { 1309 mux { 1310 groups = "tdmc_fs_slv"; 1311 function = "tdmc"; 1312 }; 1313 }; 1314 1315 tdmc_din0_pins: tdmc_din0 { 1316 mux { 1317 groups = "tdmc_din0"; 1318 function = "tdmc"; 1319 }; 1320 }; 1321 1322 tdmc_dout0_pins: tdmc_dout0 { 1323 mux { 1324 groups = "tdmc_dout0"; 1325 function = "tdmc"; 1326 }; 1327 }; 1328 1329 tdmc_din1_pins: tdmc_din1 { 1330 mux { 1331 groups = "tdmc_din1"; 1332 function = "tdmc"; 1333 }; 1334 }; 1335 1336 tdmc_dout1_pins: tdmc_dout1 { 1337 mux { 1338 groups = "tdmc_dout1"; 1339 function = "tdmc"; 1340 }; 1341 }; 1342 1343 tdmc_din2_pins: tdmc_din2 { 1344 mux { 1345 groups = "tdmc_din2"; 1346 function = "tdmc"; 1347 }; 1348 }; 1349 1350 tdmc_dout2_pins: tdmc_dout2 { 1351 mux { 1352 groups = "tdmc_dout2"; 1353 function = "tdmc"; 1354 }; 1355 }; 1356 1357 tdmc_din3_pins: tdmc_din3 { 1358 mux { 1359 groups = "tdmc_din3"; 1360 function = "tdmc"; 1361 }; 1362 }; 1363 1364 tdmc_dout3_pins: tdmc_dout3 { 1365 mux { 1366 groups = "tdmc_dout3"; 1367 function = "tdmc"; 1368 }; 1369 }; 1370 }; 1371 }; 1372 1373 sram: sram@fffc0000 { 1374 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1375 reg = <0x0 0xfffc0000 0x0 0x20000>; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 ranges = <0 0x0 0xfffc0000 0x20000>; 1379 1380 cpu_scp_lpri: scp-shmem@0 { 1381 compatible = "amlogic,meson-axg-scp-shmem"; 1382 reg = <0x13000 0x400>; 1383 }; 1384 1385 cpu_scp_hpri: scp-shmem@200 { 1386 compatible = "amlogic,meson-axg-scp-shmem"; 1387 reg = <0x13400 0x400>; 1388 }; 1389 }; 1390 1391 aobus: bus@ff800000 { 1392 compatible = "simple-bus"; 1393 reg = <0x0 0xff800000 0x0 0x100000>; 1394 #address-cells = <2>; 1395 #size-cells = <2>; 1396 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1397 1398 sysctrl_AO: sys-ctrl@0 { 1399 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd"; 1400 reg = <0x0 0x0 0x0 0x100>; 1401 1402 clkc_AO: clock-controller { 1403 compatible = "amlogic,meson-axg-aoclkc"; 1404 #clock-cells = <1>; 1405 #reset-cells = <1>; 1406 }; 1407 }; 1408 1409 pinctrl_aobus: pinctrl@14 { 1410 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1411 #address-cells = <2>; 1412 #size-cells = <2>; 1413 ranges; 1414 1415 gpio_ao: bank@14 { 1416 reg = <0x0 0x00014 0x0 0x8>, 1417 <0x0 0x0002c 0x0 0x4>, 1418 <0x0 0x00024 0x0 0x8>; 1419 reg-names = "mux", "pull", "gpio"; 1420 gpio-controller; 1421 #gpio-cells = <2>; 1422 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1423 }; 1424 1425 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1426 mux { 1427 groups = "i2c_ao_sck_4"; 1428 function = "i2c_ao"; 1429 }; 1430 }; 1431 1432 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1433 mux { 1434 groups = "i2c_ao_sck_8"; 1435 function = "i2c_ao"; 1436 }; 1437 }; 1438 1439 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1440 mux { 1441 groups = "i2c_ao_sck_10"; 1442 function = "i2c_ao"; 1443 }; 1444 }; 1445 1446 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1447 mux { 1448 groups = "i2c_ao_sda_5"; 1449 function = "i2c_ao"; 1450 }; 1451 }; 1452 1453 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1454 mux { 1455 groups = "i2c_ao_sda_9"; 1456 function = "i2c_ao"; 1457 }; 1458 }; 1459 1460 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1461 mux { 1462 groups = "i2c_ao_sda_11"; 1463 function = "i2c_ao"; 1464 }; 1465 }; 1466 1467 remote_input_ao_pins: remote_input_ao { 1468 mux { 1469 groups = "remote_input_ao"; 1470 function = "remote_input_ao"; 1471 }; 1472 }; 1473 1474 uart_ao_a_pins: uart_ao_a { 1475 mux { 1476 groups = "uart_ao_tx_a", 1477 "uart_ao_rx_a"; 1478 function = "uart_ao_a"; 1479 }; 1480 }; 1481 1482 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1483 mux { 1484 groups = "uart_ao_cts_a", 1485 "uart_ao_rts_a"; 1486 function = "uart_ao_a"; 1487 }; 1488 }; 1489 1490 uart_ao_b_pins: uart_ao_b { 1491 mux { 1492 groups = "uart_ao_tx_b", 1493 "uart_ao_rx_b"; 1494 function = "uart_ao_b"; 1495 }; 1496 }; 1497 1498 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1499 mux { 1500 groups = "uart_ao_cts_b", 1501 "uart_ao_rts_b"; 1502 function = "uart_ao_b"; 1503 }; 1504 }; 1505 }; 1506 1507 sec_AO: ao-secure@140 { 1508 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1509 reg = <0x0 0x140 0x0 0x140>; 1510 amlogic,has-chip-id; 1511 }; 1512 1513 pwm_AO_ab: pwm@7000 { 1514 compatible = "amlogic,meson-axg-ao-pwm"; 1515 reg = <0x0 0x07000 0x0 0x20>; 1516 #pwm-cells = <3>; 1517 status = "disabled"; 1518 }; 1519 1520 pwm_AO_cd: pwm@2000 { 1521 compatible = "amlogic,meson-axg-ao-pwm"; 1522 reg = <0x0 0x02000 0x0 0x20>; 1523 #pwm-cells = <3>; 1524 status = "disabled"; 1525 }; 1526 1527 i2c_AO: i2c@5000 { 1528 compatible = "amlogic,meson-axg-i2c"; 1529 reg = <0x0 0x05000 0x0 0x20>; 1530 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1531 clocks = <&clkc CLKID_AO_I2C>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 uart_AO: serial@3000 { 1538 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1539 reg = <0x0 0x3000 0x0 0x18>; 1540 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1541 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1542 clock-names = "xtal", "pclk", "baud"; 1543 status = "disabled"; 1544 }; 1545 1546 uart_AO_B: serial@4000 { 1547 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1548 reg = <0x0 0x4000 0x0 0x18>; 1549 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1550 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1551 clock-names = "xtal", "pclk", "baud"; 1552 status = "disabled"; 1553 }; 1554 1555 ir: ir@8000 { 1556 compatible = "amlogic,meson-gxbb-ir"; 1557 reg = <0x0 0x8000 0x0 0x20>; 1558 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1559 status = "disabled"; 1560 }; 1561 1562 saradc: adc@9000 { 1563 compatible = "amlogic,meson-axg-saradc", 1564 "amlogic,meson-saradc"; 1565 reg = <0x0 0x9000 0x0 0x38>; 1566 #io-channel-cells = <1>; 1567 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1568 clocks = <&xtal>, 1569 <&clkc_AO CLKID_AO_SAR_ADC>, 1570 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1571 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1572 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1573 status = "disabled"; 1574 }; 1575 }; 1576 }; 1577}; 1578