1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-audio-clkc.h> 10#include <dt-bindings/clock/axg-clkc.h> 11#include <dt-bindings/clock/axg-aoclkc.h> 12#include <dt-bindings/gpio/meson-axg-gpio.h> 13#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 14 15/ { 16 compatible = "amlogic,meson-axg"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 reserved-memory { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 /* 16 MiB reserved for Hardware ROM Firmware */ 28 hwrom_reserved: hwrom@0 { 29 reg = <0x0 0x0 0x0 0x1000000>; 30 no-map; 31 }; 32 33 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 34 secmon_reserved: secmon@5000000 { 35 reg = <0x0 0x05000000 0x0 0x300000>; 36 no-map; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <0x2>; 42 #size-cells = <0x0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 }; 51 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <0x0 0x1>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0x0 0x2>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 reg = <0x0 0x3>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 l2: l2-cache0 { 77 compatible = "cache"; 78 }; 79 }; 80 81 arm-pmu { 82 compatible = "arm,cortex-a53-pmu"; 83 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 102 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 105 }; 106 107 xtal: xtal-clk { 108 compatible = "fixed-clock"; 109 clock-frequency = <24000000>; 110 clock-output-names = "xtal"; 111 #clock-cells = <0>; 112 }; 113 114 ao_alt_xtal: ao_alt_xtal-clk { 115 compatible = "fixed-clock"; 116 clock-frequency = <32000000>; 117 clock-output-names = "ao_alt_xtal"; 118 #clock-cells = <0>; 119 }; 120 121 soc { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 apb: apb@ffe00000 { 128 compatible = "simple-bus"; 129 reg = <0x0 0xffe00000 0x0 0x200000>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 133 134 sd_emmc_b: sd@5000 { 135 compatible = "amlogic,meson-axg-mmc"; 136 reg = <0x0 0x5000 0x0 0x2000>; 137 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 138 status = "disabled"; 139 clocks = <&clkc CLKID_SD_EMMC_B>, 140 <&clkc CLKID_SD_EMMC_B_CLK0>, 141 <&clkc CLKID_FCLK_DIV2>; 142 clock-names = "core", "clkin0", "clkin1"; 143 resets = <&reset RESET_SD_EMMC_B>; 144 }; 145 146 sd_emmc_c: mmc@7000 { 147 compatible = "amlogic,meson-axg-mmc"; 148 reg = <0x0 0x7000 0x0 0x2000>; 149 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 150 status = "disabled"; 151 clocks = <&clkc CLKID_SD_EMMC_C>, 152 <&clkc CLKID_SD_EMMC_C_CLK0>, 153 <&clkc CLKID_FCLK_DIV2>; 154 clock-names = "core", "clkin0", "clkin1"; 155 resets = <&reset RESET_SD_EMMC_C>; 156 }; 157 }; 158 159 audio: bus@ff642000 { 160 compatible = "simple-bus"; 161 reg = <0x0 0xff642000 0x0 0x2000>; 162 #address-cells = <2>; 163 #size-cells = <2>; 164 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 165 166 clkc_audio: clock-controller@0 { 167 compatible = "amlogic,axg-audio-clkc"; 168 reg = <0x0 0x0 0x0 0xb4>; 169 #clock-cells = <1>; 170 171 clocks = <&clkc CLKID_AUDIO>, 172 <&clkc CLKID_MPLL0>, 173 <&clkc CLKID_MPLL1>, 174 <&clkc CLKID_MPLL2>, 175 <&clkc CLKID_MPLL3>, 176 <&clkc CLKID_HIFI_PLL>, 177 <&clkc CLKID_FCLK_DIV3>, 178 <&clkc CLKID_FCLK_DIV4>, 179 <&clkc CLKID_GP0_PLL>; 180 clock-names = "pclk", 181 "mst_in0", 182 "mst_in1", 183 "mst_in2", 184 "mst_in3", 185 "mst_in4", 186 "mst_in5", 187 "mst_in6", 188 "mst_in7"; 189 190 resets = <&reset RESET_AUDIO>; 191 }; 192 193 arb: reset-controller@280 { 194 compatible = "amlogic,meson-axg-audio-arb"; 195 reg = <0x0 0x280 0x0 0x4>; 196 #reset-cells = <1>; 197 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 198 }; 199 200 spdifout: audio-controller@480 { 201 compatible = "amlogic,axg-spdifout"; 202 reg = <0x0 0x480 0x0 0x50>; 203 #sound-dai-cells = <0>; 204 sound-name-prefix = "SPDIFOUT"; 205 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 206 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 207 clock-names = "pclk", "mclk"; 208 status = "disabled"; 209 }; 210 }; 211 212 cbus: bus@ffd00000 { 213 compatible = "simple-bus"; 214 reg = <0x0 0xffd00000 0x0 0x25000>; 215 #address-cells = <2>; 216 #size-cells = <2>; 217 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 218 219 gpio_intc: interrupt-controller@f080 { 220 compatible = "amlogic,meson-gpio-intc"; 221 reg = <0x0 0xf080 0x0 0x10>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 225 status = "disabled"; 226 }; 227 228 pwm_ab: pwm@1b000 { 229 compatible = "amlogic,meson-axg-ee-pwm"; 230 reg = <0x0 0x1b000 0x0 0x20>; 231 #pwm-cells = <3>; 232 status = "disabled"; 233 }; 234 235 pwm_cd: pwm@1a000 { 236 compatible = "amlogic,meson-axg-ee-pwm"; 237 reg = <0x0 0x1a000 0x0 0x20>; 238 #pwm-cells = <3>; 239 status = "disabled"; 240 }; 241 242 reset: reset-controller@1004 { 243 compatible = "amlogic,meson-axg-reset"; 244 reg = <0x0 0x01004 0x0 0x9c>; 245 #reset-cells = <1>; 246 }; 247 248 spicc0: spi@13000 { 249 compatible = "amlogic,meson-axg-spicc"; 250 reg = <0x0 0x13000 0x0 0x3c>; 251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&clkc CLKID_SPICC0>; 253 clock-names = "core"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 status = "disabled"; 257 }; 258 259 spicc1: spi@15000 { 260 compatible = "amlogic,meson-axg-spicc"; 261 reg = <0x0 0x15000 0x0 0x3c>; 262 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clkc CLKID_SPICC1>; 264 clock-names = "core"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 status = "disabled"; 268 }; 269 270 i2c0: i2c@1f000 { 271 compatible = "amlogic,meson-axg-i2c"; 272 reg = <0x0 0x1f000 0x0 0x20>; 273 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 274 clocks = <&clkc CLKID_I2C>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 i2c1: i2c@1e000 { 281 compatible = "amlogic,meson-axg-i2c"; 282 reg = <0x0 0x1e000 0x0 0x20>; 283 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 284 clocks = <&clkc CLKID_I2C>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 status = "disabled"; 288 }; 289 290 i2c2: i2c@1d000 { 291 compatible = "amlogic,meson-axg-i2c"; 292 reg = <0x0 0x1d000 0x0 0x20>; 293 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 294 clocks = <&clkc CLKID_I2C>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 i2c3: i2c@1c000 { 301 compatible = "amlogic,meson-axg-i2c"; 302 reg = <0x0 0x1c000 0x0 0x20>; 303 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 304 clocks = <&clkc CLKID_I2C>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 status = "disabled"; 308 }; 309 310 uart_A: serial@24000 { 311 compatible = "amlogic,meson-gx-uart"; 312 reg = <0x0 0x24000 0x0 0x18>; 313 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 314 status = "disabled"; 315 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 316 clock-names = "xtal", "pclk", "baud"; 317 }; 318 319 uart_B: serial@23000 { 320 compatible = "amlogic,meson-gx-uart"; 321 reg = <0x0 0x23000 0x0 0x18>; 322 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 323 status = "disabled"; 324 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 325 clock-names = "xtal", "pclk", "baud"; 326 }; 327 }; 328 329 ethmac: ethernet@ff3f0000 { 330 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 331 reg = <0x0 0xff3f0000 0x0 0x10000 332 0x0 0xff634540 0x0 0x8>; 333 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 334 interrupt-names = "macirq"; 335 clocks = <&clkc CLKID_ETH>, 336 <&clkc CLKID_FCLK_DIV2>, 337 <&clkc CLKID_MPLL2>; 338 clock-names = "stmmaceth", "clkin0", "clkin1"; 339 status = "disabled"; 340 }; 341 342 gic: interrupt-controller@ffc01000 { 343 compatible = "arm,gic-400"; 344 reg = <0x0 0xffc01000 0 0x1000>, 345 <0x0 0xffc02000 0 0x2000>, 346 <0x0 0xffc04000 0 0x2000>, 347 <0x0 0xffc06000 0 0x2000>; 348 interrupt-controller; 349 interrupts = <GIC_PPI 9 350 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 351 #interrupt-cells = <3>; 352 #address-cells = <0>; 353 }; 354 355 hiubus: bus@ff63c000 { 356 compatible = "simple-bus"; 357 reg = <0x0 0xff63c000 0x0 0x1c00>; 358 #address-cells = <2>; 359 #size-cells = <2>; 360 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 361 362 sysctrl: system-controller@0 { 363 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 364 reg = <0 0 0 0x400>; 365 366 clkc: clock-controller { 367 compatible = "amlogic,axg-clkc"; 368 #clock-cells = <1>; 369 }; 370 }; 371 }; 372 373 mailbox: mailbox@ff63dc00 { 374 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 375 reg = <0 0xff63dc00 0 0x400>; 376 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 379 #mbox-cells = <1>; 380 }; 381 382 periphs: periphs@ff634000 { 383 compatible = "simple-bus"; 384 reg = <0x0 0xff634000 0x0 0x2000>; 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 388 389 hwrng: rng { 390 compatible = "amlogic,meson-rng"; 391 reg = <0x0 0x18 0x0 0x4>; 392 clocks = <&clkc CLKID_RNG0>; 393 clock-names = "core"; 394 }; 395 396 pinctrl_periphs: pinctrl@480 { 397 compatible = "amlogic,meson-axg-periphs-pinctrl"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 402 gpio: bank@480 { 403 reg = <0x0 0x00480 0x0 0x40>, 404 <0x0 0x004e8 0x0 0x14>, 405 <0x0 0x00520 0x0 0x14>, 406 <0x0 0x00430 0x0 0x3c>; 407 reg-names = "mux", "pull", "pull-enable", "gpio"; 408 gpio-controller; 409 #gpio-cells = <2>; 410 gpio-ranges = <&pinctrl_periphs 0 0 86>; 411 }; 412 413 emmc_pins: emmc { 414 mux { 415 groups = "emmc_nand_d0", 416 "emmc_nand_d1", 417 "emmc_nand_d2", 418 "emmc_nand_d3", 419 "emmc_nand_d4", 420 "emmc_nand_d5", 421 "emmc_nand_d6", 422 "emmc_nand_d7", 423 "emmc_clk", 424 "emmc_cmd", 425 "emmc_ds"; 426 function = "emmc"; 427 }; 428 }; 429 430 emmc_clk_gate_pins: emmc_clk_gate { 431 mux { 432 groups = "BOOT_8"; 433 function = "gpio_periphs"; 434 }; 435 cfg-pull-down { 436 pins = "BOOT_8"; 437 bias-pull-down; 438 }; 439 }; 440 441 sdio_pins: sdio { 442 mux { 443 groups = "sdio_d0", 444 "sdio_d1", 445 "sdio_d2", 446 "sdio_d3", 447 "sdio_cmd", 448 "sdio_clk"; 449 function = "sdio"; 450 }; 451 }; 452 453 sdio_clk_gate_pins: sdio_clk_gate { 454 mux { 455 groups = "GPIOX_4"; 456 function = "gpio_periphs"; 457 }; 458 cfg-pull-down { 459 pins = "GPIOX_4"; 460 bias-pull-down; 461 }; 462 }; 463 464 eth_rmii_x_pins: eth-x-rmii { 465 mux { 466 groups = "eth_mdio_x", 467 "eth_mdc_x", 468 "eth_rgmii_rx_clk_x", 469 "eth_rx_dv_x", 470 "eth_rxd0_x", 471 "eth_rxd1_x", 472 "eth_txen_x", 473 "eth_txd0_x", 474 "eth_txd1_x"; 475 function = "eth"; 476 }; 477 }; 478 479 eth_rmii_y_pins: eth-y-rmii { 480 mux { 481 groups = "eth_mdio_y", 482 "eth_mdc_y", 483 "eth_rgmii_rx_clk_y", 484 "eth_rx_dv_y", 485 "eth_rxd0_y", 486 "eth_rxd1_y", 487 "eth_txen_y", 488 "eth_txd0_y", 489 "eth_txd1_y"; 490 function = "eth"; 491 }; 492 }; 493 494 eth_rgmii_x_pins: eth-x-rgmii { 495 mux { 496 groups = "eth_mdio_x", 497 "eth_mdc_x", 498 "eth_rgmii_rx_clk_x", 499 "eth_rx_dv_x", 500 "eth_rxd0_x", 501 "eth_rxd1_x", 502 "eth_rxd2_rgmii", 503 "eth_rxd3_rgmii", 504 "eth_rgmii_tx_clk", 505 "eth_txen_x", 506 "eth_txd0_x", 507 "eth_txd1_x", 508 "eth_txd2_rgmii", 509 "eth_txd3_rgmii"; 510 function = "eth"; 511 }; 512 }; 513 514 eth_rgmii_y_pins: eth-y-rgmii { 515 mux { 516 groups = "eth_mdio_y", 517 "eth_mdc_y", 518 "eth_rgmii_rx_clk_y", 519 "eth_rx_dv_y", 520 "eth_rxd0_y", 521 "eth_rxd1_y", 522 "eth_rxd2_rgmii", 523 "eth_rxd3_rgmii", 524 "eth_rgmii_tx_clk", 525 "eth_txen_y", 526 "eth_txd0_y", 527 "eth_txd1_y", 528 "eth_txd2_rgmii", 529 "eth_txd3_rgmii"; 530 function = "eth"; 531 }; 532 }; 533 534 pdm_dclk_a14_pins: pdm_dclk_a14 { 535 mux { 536 groups = "pdm_dclk_a14"; 537 function = "pdm"; 538 }; 539 }; 540 541 pdm_dclk_a19_pins: pdm_dclk_a19 { 542 mux { 543 groups = "pdm_dclk_a19"; 544 function = "pdm"; 545 }; 546 }; 547 548 pdm_din0_pins: pdm_din0 { 549 mux { 550 groups = "pdm_din0"; 551 function = "pdm"; 552 }; 553 }; 554 555 pdm_din1_pins: pdm_din1 { 556 mux { 557 groups = "pdm_din1"; 558 function = "pdm"; 559 }; 560 }; 561 562 pdm_din2_pins: pdm_din2 { 563 mux { 564 groups = "pdm_din2"; 565 function = "pdm"; 566 }; 567 }; 568 569 pdm_din3_pins: pdm_din3 { 570 mux { 571 groups = "pdm_din3"; 572 function = "pdm"; 573 }; 574 }; 575 576 pwm_a_a_pins: pwm_a_a { 577 mux { 578 groups = "pwm_a_a"; 579 function = "pwm_a"; 580 }; 581 }; 582 583 pwm_a_x18_pins: pwm_a_x18 { 584 mux { 585 groups = "pwm_a_x18"; 586 function = "pwm_a"; 587 }; 588 }; 589 590 pwm_a_x20_pins: pwm_a_x20 { 591 mux { 592 groups = "pwm_a_x20"; 593 function = "pwm_a"; 594 }; 595 }; 596 597 pwm_a_z_pins: pwm_a_z { 598 mux { 599 groups = "pwm_a_z"; 600 function = "pwm_a"; 601 }; 602 }; 603 604 pwm_b_a_pins: pwm_b_a { 605 mux { 606 groups = "pwm_b_a"; 607 function = "pwm_b"; 608 }; 609 }; 610 611 pwm_b_x_pins: pwm_b_x { 612 mux { 613 groups = "pwm_b_x"; 614 function = "pwm_b"; 615 }; 616 }; 617 618 pwm_b_z_pins: pwm_b_z { 619 mux { 620 groups = "pwm_b_z"; 621 function = "pwm_b"; 622 }; 623 }; 624 625 pwm_c_a_pins: pwm_c_a { 626 mux { 627 groups = "pwm_c_a"; 628 function = "pwm_c"; 629 }; 630 }; 631 632 pwm_c_x10_pins: pwm_c_x10 { 633 mux { 634 groups = "pwm_c_x10"; 635 function = "pwm_c"; 636 }; 637 }; 638 639 pwm_c_x17_pins: pwm_c_x17 { 640 mux { 641 groups = "pwm_c_x17"; 642 function = "pwm_c"; 643 }; 644 }; 645 646 pwm_d_x11_pins: pwm_d_x11 { 647 mux { 648 groups = "pwm_d_x11"; 649 function = "pwm_d"; 650 }; 651 }; 652 653 pwm_d_x16_pins: pwm_d_x16 { 654 mux { 655 groups = "pwm_d_x16"; 656 function = "pwm_d"; 657 }; 658 }; 659 660 spdif_in_z_pins: spdif_in_z { 661 mux { 662 groups = "spdif_in_z"; 663 function = "spdif_in"; 664 }; 665 }; 666 667 spdif_in_a1_pins: spdif_in_a1 { 668 mux { 669 groups = "spdif_in_a1"; 670 function = "spdif_in"; 671 }; 672 }; 673 674 spdif_in_a7_pins: spdif_in_a7 { 675 mux { 676 groups = "spdif_in_a7"; 677 function = "spdif_in"; 678 }; 679 }; 680 681 spdif_in_a19_pins: spdif_in_a19 { 682 mux { 683 groups = "spdif_in_a19"; 684 function = "spdif_in"; 685 }; 686 }; 687 688 spdif_in_a20_pins: spdif_in_a20 { 689 mux { 690 groups = "spdif_in_a20"; 691 function = "spdif_in"; 692 }; 693 }; 694 695 spdif_out_z_pins: spdif_out_z { 696 mux { 697 groups = "spdif_out_z"; 698 function = "spdif_out"; 699 }; 700 }; 701 702 spdif_out_a1_pins: spdif_out_a1 { 703 mux { 704 groups = "spdif_out_a1"; 705 function = "spdif_out"; 706 }; 707 }; 708 709 spdif_out_a11_pins: spdif_out_a11 { 710 mux { 711 groups = "spdif_out_a11"; 712 function = "spdif_out"; 713 }; 714 }; 715 716 spdif_out_a19_pins: spdif_out_a19 { 717 mux { 718 groups = "spdif_out_a19"; 719 function = "spdif_out"; 720 }; 721 }; 722 723 spdif_out_a20_pins: spdif_out_a20 { 724 mux { 725 groups = "spdif_out_a20"; 726 function = "spdif_out"; 727 }; 728 }; 729 730 spi0_pins: spi0 { 731 mux { 732 groups = "spi0_miso", 733 "spi0_mosi", 734 "spi0_clk"; 735 function = "spi0"; 736 }; 737 }; 738 739 spi0_ss0_pins: spi0_ss0 { 740 mux { 741 groups = "spi0_ss0"; 742 function = "spi0"; 743 }; 744 }; 745 746 spi0_ss1_pins: spi0_ss1 { 747 mux { 748 groups = "spi0_ss1"; 749 function = "spi0"; 750 }; 751 }; 752 753 spi0_ss2_pins: spi0_ss2 { 754 mux { 755 groups = "spi0_ss2"; 756 function = "spi0"; 757 }; 758 }; 759 760 761 spi1_a_pins: spi1_a { 762 mux { 763 groups = "spi1_miso_a", 764 "spi1_mosi_a", 765 "spi1_clk_a"; 766 function = "spi1"; 767 }; 768 }; 769 770 spi1_ss0_a_pins: spi1_ss0_a { 771 mux { 772 groups = "spi1_ss0_a"; 773 function = "spi1"; 774 }; 775 }; 776 777 spi1_ss1_pins: spi1_ss1 { 778 mux { 779 groups = "spi1_ss1"; 780 function = "spi1"; 781 }; 782 }; 783 784 spi1_x_pins: spi1_x { 785 mux { 786 groups = "spi1_miso_x", 787 "spi1_mosi_x", 788 "spi1_clk_x"; 789 function = "spi1"; 790 }; 791 }; 792 793 spi1_ss0_x_pins: spi1_ss0_x { 794 mux { 795 groups = "spi1_ss0_x"; 796 function = "spi1"; 797 }; 798 }; 799 800 i2c0_pins: i2c0 { 801 mux { 802 groups = "i2c0_sck", 803 "i2c0_sda"; 804 function = "i2c0"; 805 }; 806 }; 807 808 i2c1_z_pins: i2c1_z { 809 mux { 810 groups = "i2c1_sck_z", 811 "i2c1_sda_z"; 812 function = "i2c1"; 813 }; 814 }; 815 816 i2c1_x_pins: i2c1_x { 817 mux { 818 groups = "i2c1_sck_x", 819 "i2c1_sda_x"; 820 function = "i2c1"; 821 }; 822 }; 823 824 i2c2_x_pins: i2c2_x { 825 mux { 826 groups = "i2c2_sck_x", 827 "i2c2_sda_x"; 828 function = "i2c2"; 829 }; 830 }; 831 832 i2c2_a_pins: i2c2_a { 833 mux { 834 groups = "i2c2_sck_a", 835 "i2c2_sda_a"; 836 function = "i2c2"; 837 }; 838 }; 839 840 i2c3_a6_pins: i2c3_a6 { 841 mux { 842 groups = "i2c3_sda_a6", 843 "i2c3_sck_a7"; 844 function = "i2c3"; 845 }; 846 }; 847 848 i2c3_a12_pins: i2c3_a12 { 849 mux { 850 groups = "i2c3_sda_a12", 851 "i2c3_sck_a13"; 852 function = "i2c3"; 853 }; 854 }; 855 856 i2c3_a19_pins: i2c3_a19 { 857 mux { 858 groups = "i2c3_sda_a19", 859 "i2c3_sck_a20"; 860 function = "i2c3"; 861 }; 862 }; 863 864 uart_a_pins: uart_a { 865 mux { 866 groups = "uart_tx_a", 867 "uart_rx_a"; 868 function = "uart_a"; 869 }; 870 }; 871 872 uart_a_cts_rts_pins: uart_a_cts_rts { 873 mux { 874 groups = "uart_cts_a", 875 "uart_rts_a"; 876 function = "uart_a"; 877 }; 878 }; 879 880 uart_b_x_pins: uart_b_x { 881 mux { 882 groups = "uart_tx_b_x", 883 "uart_rx_b_x"; 884 function = "uart_b"; 885 }; 886 }; 887 888 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 889 mux { 890 groups = "uart_cts_b_x", 891 "uart_rts_b_x"; 892 function = "uart_b"; 893 }; 894 }; 895 896 uart_b_z_pins: uart_b_z { 897 mux { 898 groups = "uart_tx_b_z", 899 "uart_rx_b_z"; 900 function = "uart_b"; 901 }; 902 }; 903 904 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 905 mux { 906 groups = "uart_cts_b_z", 907 "uart_rts_b_z"; 908 function = "uart_b"; 909 }; 910 }; 911 912 uart_ao_b_z_pins: uart_ao_b_z { 913 mux { 914 groups = "uart_ao_tx_b_z", 915 "uart_ao_rx_b_z"; 916 function = "uart_ao_b_z"; 917 }; 918 }; 919 920 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 921 mux { 922 groups = "uart_ao_cts_b_z", 923 "uart_ao_rts_b_z"; 924 function = "uart_ao_b_z"; 925 }; 926 }; 927 928 mclk_b_pins: mclk_b { 929 mux { 930 groups = "mclk_b"; 931 function = "mclk_b"; 932 }; 933 }; 934 935 mclk_c_pins: mclk_c { 936 mux { 937 groups = "mclk_c"; 938 function = "mclk_c"; 939 }; 940 }; 941 942 tdma_sclk_pins: tdma_sclk { 943 mux { 944 groups = "tdma_sclk"; 945 function = "tdma"; 946 }; 947 }; 948 949 tdma_sclk_slv_pins: tdma_sclk_slv { 950 mux { 951 groups = "tdma_sclk_slv"; 952 function = "tdma"; 953 }; 954 }; 955 956 tdma_fs_pins: tdma_fs { 957 mux { 958 groups = "tdma_fs"; 959 function = "tdma"; 960 }; 961 }; 962 963 tdma_fs_slv_pins: tdma_fs_slv { 964 mux { 965 groups = "tdma_fs_slv"; 966 function = "tdma"; 967 }; 968 }; 969 970 tdma_din0_pins: tdma_din0 { 971 mux { 972 groups = "tdma_din0"; 973 function = "tdma"; 974 }; 975 }; 976 977 tdma_dout0_x14_pins: tdma_dout0_x14 { 978 mux { 979 groups = "tdma_dout0_x14"; 980 function = "tdma"; 981 }; 982 }; 983 984 tdma_dout0_x15_pins: tdma_dout0_x15 { 985 mux { 986 groups = "tdma_dout0_x15"; 987 function = "tdma"; 988 }; 989 }; 990 991 tdma_dout1_pins: tdma_dout1 { 992 mux { 993 groups = "tdma_dout1"; 994 function = "tdma"; 995 }; 996 }; 997 998 tdma_din1_pins: tdma_din1 { 999 mux { 1000 groups = "tdma_din1"; 1001 function = "tdma"; 1002 }; 1003 }; 1004 1005 tdmb_sclk_pins: tdmb_sclk { 1006 mux { 1007 groups = "tdmb_sclk"; 1008 function = "tdmb"; 1009 }; 1010 }; 1011 1012 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1013 mux { 1014 groups = "tdmb_sclk_slv"; 1015 function = "tdmb"; 1016 }; 1017 }; 1018 1019 tdmb_fs_pins: tdmb_fs { 1020 mux { 1021 groups = "tdmb_fs"; 1022 function = "tdmb"; 1023 }; 1024 }; 1025 1026 tdmb_fs_slv_pins: tdmb_fs_slv { 1027 mux { 1028 groups = "tdmb_fs_slv"; 1029 function = "tdmb"; 1030 }; 1031 }; 1032 1033 tdmb_din0_pins: tdmb_din0 { 1034 mux { 1035 groups = "tdmb_din0"; 1036 function = "tdmb"; 1037 }; 1038 }; 1039 1040 tdmb_dout0_pins: tdmb_dout0 { 1041 mux { 1042 groups = "tdmb_dout0"; 1043 function = "tdmb"; 1044 }; 1045 }; 1046 1047 tdmb_din1_pins: tdmb_din1 { 1048 mux { 1049 groups = "tdmb_din1"; 1050 function = "tdmb"; 1051 }; 1052 }; 1053 1054 tdmb_dout1_pins: tdmb_dout1 { 1055 mux { 1056 groups = "tdmb_dout1"; 1057 function = "tdmb"; 1058 }; 1059 }; 1060 1061 tdmb_din2_pins: tdmb_din2 { 1062 mux { 1063 groups = "tdmb_din2"; 1064 function = "tdmb"; 1065 }; 1066 }; 1067 1068 tdmb_dout2_pins: tdmb_dout2 { 1069 mux { 1070 groups = "tdmb_dout2"; 1071 function = "tdmb"; 1072 }; 1073 }; 1074 1075 tdmb_din3_pins: tdmb_din3 { 1076 mux { 1077 groups = "tdmb_din3"; 1078 function = "tdmb"; 1079 }; 1080 }; 1081 1082 tdmb_dout3_pins: tdmb_dout3 { 1083 mux { 1084 groups = "tdmb_dout3"; 1085 function = "tdmb"; 1086 }; 1087 }; 1088 1089 tdmc_sclk_pins: tdmc_sclk { 1090 mux { 1091 groups = "tdmc_sclk"; 1092 function = "tdmc"; 1093 }; 1094 }; 1095 1096 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1097 mux { 1098 groups = "tdmc_sclk_slv"; 1099 function = "tdmc"; 1100 }; 1101 }; 1102 1103 tdmc_fs_pins: tdmc_fs { 1104 mux { 1105 groups = "tdmc_fs"; 1106 function = "tdmc"; 1107 }; 1108 }; 1109 1110 tdmc_fs_slv_pins: tdmc_fs_slv { 1111 mux { 1112 groups = "tdmc_fs_slv"; 1113 function = "tdmc"; 1114 }; 1115 }; 1116 1117 tdmc_din0_pins: tdmc_din0 { 1118 mux { 1119 groups = "tdmc_din0"; 1120 function = "tdmc"; 1121 }; 1122 }; 1123 1124 tdmc_dout0_pins: tdmc_dout0 { 1125 mux { 1126 groups = "tdmc_dout0"; 1127 function = "tdmc"; 1128 }; 1129 }; 1130 1131 tdmc_din1_pins: tdmc_din1 { 1132 mux { 1133 groups = "tdmc_din1"; 1134 function = "tdmc"; 1135 }; 1136 }; 1137 1138 tdmc_dout1_pins: tdmc_dout1 { 1139 mux { 1140 groups = "tdmc_dout1"; 1141 function = "tdmc"; 1142 }; 1143 }; 1144 1145 tdmc_din2_pins: tdmc_din2 { 1146 mux { 1147 groups = "tdmc_din2"; 1148 function = "tdmc"; 1149 }; 1150 }; 1151 1152 tdmc_dout2_pins: tdmc_dout2 { 1153 mux { 1154 groups = "tdmc_dout2"; 1155 function = "tdmc"; 1156 }; 1157 }; 1158 1159 tdmc_din3_pins: tdmc_din3 { 1160 mux { 1161 groups = "tdmc_din3"; 1162 function = "tdmc"; 1163 }; 1164 }; 1165 1166 tdmc_dout3_pins: tdmc_dout3 { 1167 mux { 1168 groups = "tdmc_dout3"; 1169 function = "tdmc"; 1170 }; 1171 }; 1172 }; 1173 }; 1174 1175 sram: sram@fffc0000 { 1176 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1177 reg = <0x0 0xfffc0000 0x0 0x20000>; 1178 #address-cells = <1>; 1179 #size-cells = <1>; 1180 ranges = <0 0x0 0xfffc0000 0x20000>; 1181 1182 cpu_scp_lpri: scp-shmem@0 { 1183 compatible = "amlogic,meson-axg-scp-shmem"; 1184 reg = <0x13000 0x400>; 1185 }; 1186 1187 cpu_scp_hpri: scp-shmem@200 { 1188 compatible = "amlogic,meson-axg-scp-shmem"; 1189 reg = <0x13400 0x400>; 1190 }; 1191 }; 1192 1193 aobus: bus@ff800000 { 1194 compatible = "simple-bus"; 1195 reg = <0x0 0xff800000 0x0 0x100000>; 1196 #address-cells = <2>; 1197 #size-cells = <2>; 1198 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1199 1200 sysctrl_AO: sys-ctrl@0 { 1201 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd"; 1202 reg = <0x0 0x0 0x0 0x100>; 1203 1204 clkc_AO: clock-controller { 1205 compatible = "amlogic,meson-axg-aoclkc"; 1206 #clock-cells = <1>; 1207 #reset-cells = <1>; 1208 }; 1209 }; 1210 1211 pinctrl_aobus: pinctrl@14 { 1212 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1213 #address-cells = <2>; 1214 #size-cells = <2>; 1215 ranges; 1216 1217 gpio_ao: bank@14 { 1218 reg = <0x0 0x00014 0x0 0x8>, 1219 <0x0 0x0002c 0x0 0x4>, 1220 <0x0 0x00024 0x0 0x8>; 1221 reg-names = "mux", "pull", "gpio"; 1222 gpio-controller; 1223 #gpio-cells = <2>; 1224 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1225 }; 1226 1227 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1228 mux { 1229 groups = "i2c_ao_sck_4"; 1230 function = "i2c_ao"; 1231 }; 1232 }; 1233 1234 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1235 mux { 1236 groups = "i2c_ao_sck_8"; 1237 function = "i2c_ao"; 1238 }; 1239 }; 1240 1241 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1242 mux { 1243 groups = "i2c_ao_sck_10"; 1244 function = "i2c_ao"; 1245 }; 1246 }; 1247 1248 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1249 mux { 1250 groups = "i2c_ao_sda_5"; 1251 function = "i2c_ao"; 1252 }; 1253 }; 1254 1255 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1256 mux { 1257 groups = "i2c_ao_sda_9"; 1258 function = "i2c_ao"; 1259 }; 1260 }; 1261 1262 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1263 mux { 1264 groups = "i2c_ao_sda_11"; 1265 function = "i2c_ao"; 1266 }; 1267 }; 1268 1269 remote_input_ao_pins: remote_input_ao { 1270 mux { 1271 groups = "remote_input_ao"; 1272 function = "remote_input_ao"; 1273 }; 1274 }; 1275 1276 uart_ao_a_pins: uart_ao_a { 1277 mux { 1278 groups = "uart_ao_tx_a", 1279 "uart_ao_rx_a"; 1280 function = "uart_ao_a"; 1281 }; 1282 }; 1283 1284 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1285 mux { 1286 groups = "uart_ao_cts_a", 1287 "uart_ao_rts_a"; 1288 function = "uart_ao_a"; 1289 }; 1290 }; 1291 1292 uart_ao_b_pins: uart_ao_b { 1293 mux { 1294 groups = "uart_ao_tx_b", 1295 "uart_ao_rx_b"; 1296 function = "uart_ao_b"; 1297 }; 1298 }; 1299 1300 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1301 mux { 1302 groups = "uart_ao_cts_b", 1303 "uart_ao_rts_b"; 1304 function = "uart_ao_b"; 1305 }; 1306 }; 1307 }; 1308 1309 sec_AO: ao-secure@140 { 1310 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1311 reg = <0x0 0x140 0x0 0x140>; 1312 amlogic,has-chip-id; 1313 }; 1314 1315 pwm_AO_ab: pwm@7000 { 1316 compatible = "amlogic,meson-axg-ao-pwm"; 1317 reg = <0x0 0x07000 0x0 0x20>; 1318 #pwm-cells = <3>; 1319 status = "disabled"; 1320 }; 1321 1322 pwm_AO_cd: pwm@2000 { 1323 compatible = "amlogic,meson-axg-ao-pwm"; 1324 reg = <0x0 0x02000 0x0 0x20>; 1325 #pwm-cells = <3>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c_AO: i2c@5000 { 1330 compatible = "amlogic,meson-axg-i2c"; 1331 reg = <0x0 0x05000 0x0 0x20>; 1332 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1333 clocks = <&clkc CLKID_AO_I2C>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 uart_AO: serial@3000 { 1340 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1341 reg = <0x0 0x3000 0x0 0x18>; 1342 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1343 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1344 clock-names = "xtal", "pclk", "baud"; 1345 status = "disabled"; 1346 }; 1347 1348 uart_AO_B: serial@4000 { 1349 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1350 reg = <0x0 0x4000 0x0 0x18>; 1351 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1352 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1353 clock-names = "xtal", "pclk", "baud"; 1354 status = "disabled"; 1355 }; 1356 1357 ir: ir@8000 { 1358 compatible = "amlogic,meson-gxbb-ir"; 1359 reg = <0x0 0x8000 0x0 0x20>; 1360 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1361 status = "disabled"; 1362 }; 1363 1364 saradc: adc@9000 { 1365 compatible = "amlogic,meson-axg-saradc", 1366 "amlogic,meson-saradc"; 1367 reg = <0x0 0x9000 0x0 0x38>; 1368 #io-channel-cells = <1>; 1369 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1370 clocks = <&xtal>, 1371 <&clkc_AO CLKID_AO_SAR_ADC>, 1372 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1373 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1374 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1375 status = "disabled"; 1376 }; 1377 }; 1378 }; 1379}; 1380