1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		cbus: bus@ffd00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffd00000 0x0 0x25000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
123
124			pwm_ab: pwm@1b000 {
125				compatible = "amlogic,meson-axg-ee-pwm";
126				reg = <0x0 0x1b000 0x0 0x20>;
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			pwm_cd: pwm@1a000 {
132				compatible = "amlogic,meson-axg-ee-pwm";
133				reg = <0x0 0x1a000 0x0 0x20>;
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			reset: reset-controller@1004 {
139				compatible = "amlogic,meson-axg-reset";
140				reg = <0x0 0x01004 0x0 0x9c>;
141				#reset-cells = <1>;
142			};
143
144			spicc0: spi@13000 {
145				compatible = "amlogic,meson-axg-spicc";
146				reg = <0x0 0x13000 0x0 0x3c>;
147				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clkc CLKID_SPICC0>;
149				clock-names = "core";
150				#address-cells = <1>;
151				#size-cells = <0>;
152				status = "disabled";
153			};
154
155			spicc1: spi@15000 {
156				compatible = "amlogic,meson-axg-spicc";
157				reg = <0x0 0x15000 0x0 0x3c>;
158				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159				clocks = <&clkc CLKID_SPICC1>;
160				clock-names = "core";
161				#address-cells = <1>;
162				#size-cells = <0>;
163				status = "disabled";
164			};
165
166			uart_A: serial@24000 {
167				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
168				reg = <0x0 0x24000 0x0 0x18>;
169				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
170				status = "disabled";
171			};
172
173			uart_B: serial@23000 {
174				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
175				reg = <0x0 0x23000 0x0 0x18>;
176				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
177				status = "disabled";
178			};
179		};
180
181		ethmac: ethernet@ff3f0000 {
182			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
183			reg = <0x0 0xff3f0000 0x0 0x10000
184				0x0 0xff634540 0x0 0x8>;
185			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
186			interrupt-names = "macirq";
187			clocks = <&clkc CLKID_ETH>,
188				 <&clkc CLKID_FCLK_DIV2>,
189				 <&clkc CLKID_MPLL2>;
190			clock-names = "stmmaceth", "clkin0", "clkin1";
191			status = "disabled";
192		};
193
194		gic: interrupt-controller@ffc01000 {
195			compatible = "arm,gic-400";
196			reg = <0x0 0xffc01000 0 0x1000>,
197			      <0x0 0xffc02000 0 0x2000>,
198			      <0x0 0xffc04000 0 0x2000>,
199			      <0x0 0xffc06000 0 0x2000>;
200			interrupt-controller;
201			interrupts = <GIC_PPI 9
202				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
203			#interrupt-cells = <3>;
204			#address-cells = <0>;
205		};
206
207		hiubus: bus@ff63c000 {
208			compatible = "simple-bus";
209			reg = <0x0 0xff63c000 0x0 0x1c00>;
210			#address-cells = <2>;
211			#size-cells = <2>;
212			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
213
214			clkc: clock-controller@0 {
215				compatible = "amlogic,axg-clkc";
216				#clock-cells = <1>;
217				reg = <0x0 0x0 0x0 0x320>;
218			};
219		};
220
221		mailbox: mailbox@ff63dc00 {
222			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
223			reg = <0 0xff63dc00 0 0x400>;
224			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
225				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
226				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
227			#mbox-cells = <1>;
228		};
229
230		periphs: periphs@ff634000 {
231			compatible = "simple-bus";
232			reg = <0x0 0xff634000 0x0 0x2000>;
233			#address-cells = <2>;
234			#size-cells = <2>;
235			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
236
237			hwrng: rng {
238				compatible = "amlogic,meson-rng";
239				reg = <0x0 0x18 0x0 0x4>;
240				clocks = <&clkc CLKID_RNG0>;
241				clock-names = "core";
242			};
243
244			pinctrl_periphs: pinctrl@480 {
245				compatible = "amlogic,meson-axg-periphs-pinctrl";
246				#address-cells = <2>;
247				#size-cells = <2>;
248				ranges;
249
250				gpio: bank@480 {
251					reg = <0x0 0x00480 0x0 0x40>,
252						<0x0 0x004e8 0x0 0x14>,
253						<0x0 0x00520 0x0 0x14>,
254						<0x0 0x00430 0x0 0x3c>;
255					reg-names = "mux", "pull", "pull-enable", "gpio";
256					gpio-controller;
257					#gpio-cells = <2>;
258					gpio-ranges = <&pinctrl_periphs 0 0 86>;
259				};
260
261				eth_rgmii_x_pins: eth-x-rgmii {
262					mux {
263						groups = "eth_mdio_x",
264						       "eth_mdc_x",
265						       "eth_rgmii_rx_clk_x",
266						       "eth_rx_dv_x",
267						       "eth_rxd0_x",
268						       "eth_rxd1_x",
269						       "eth_rxd2_rgmii",
270						       "eth_rxd3_rgmii",
271						       "eth_rgmii_tx_clk",
272						       "eth_txen_x",
273						       "eth_txd0_x",
274						       "eth_txd1_x",
275						       "eth_txd2_rgmii",
276						       "eth_txd3_rgmii";
277						function = "eth";
278					};
279				};
280
281				eth_rgmii_y_pins: eth-y-rgmii {
282					mux {
283						groups = "eth_mdio_y",
284						       "eth_mdc_y",
285						       "eth_rgmii_rx_clk_y",
286						       "eth_rx_dv_y",
287						       "eth_rxd0_y",
288						       "eth_rxd1_y",
289						       "eth_rxd2_rgmii",
290						       "eth_rxd3_rgmii",
291						       "eth_rgmii_tx_clk",
292						       "eth_txen_y",
293						       "eth_txd0_y",
294						       "eth_txd1_y",
295						       "eth_txd2_rgmii",
296						       "eth_txd3_rgmii";
297						function = "eth";
298					};
299				};
300
301				pwm_a_a_pins: pwm_a_a {
302					mux {
303						groups = "pwm_a_a";
304						function = "pwm_a";
305					};
306				};
307
308				pwm_a_x18_pins: pwm_a_x18 {
309					mux {
310						groups = "pwm_a_x18";
311						function = "pwm_a";
312					};
313				};
314
315				pwm_a_x20_pins: pwm_a_x20 {
316					mux {
317						groups = "pwm_a_x20";
318						function = "pwm_a";
319					};
320				};
321
322				pwm_a_z_pins: pwm_a_z {
323					mux {
324						groups = "pwm_a_z";
325						function = "pwm_a";
326					};
327				};
328
329				pwm_b_a_pins: pwm_b_a {
330					mux {
331						groups = "pwm_b_a";
332						function = "pwm_b";
333					};
334				};
335
336				pwm_b_x_pins: pwm_b_x {
337					mux {
338						groups = "pwm_b_x";
339						function = "pwm_b";
340					};
341				};
342
343				pwm_b_z_pins: pwm_b_z {
344					mux {
345						groups = "pwm_b_z";
346						function = "pwm_b";
347					};
348				};
349
350				pwm_c_a_pins: pwm_c_a {
351					mux {
352						groups = "pwm_c_a";
353						function = "pwm_c";
354					};
355				};
356
357				pwm_c_x10_pins: pwm_c_x10 {
358					mux {
359						groups = "pwm_c_x10";
360						function = "pwm_c";
361					};
362				};
363
364				pwm_c_x17_pins: pwm_c_x17 {
365					mux {
366						groups = "pwm_c_x17";
367						function = "pwm_c";
368					};
369				};
370
371				pwm_d_x11_pins: pwm_d_x11 {
372					mux {
373						groups = "pwm_d_x11";
374						function = "pwm_d";
375					};
376				};
377
378				pwm_d_x16_pins: pwm_d_x16 {
379					mux {
380						groups = "pwm_d_x16";
381						function = "pwm_d";
382					};
383				};
384
385				spi0_pins: spi0 {
386					mux {
387						groups = "spi0_miso",
388							"spi0_mosi",
389							"spi0_clk";
390						function = "spi0";
391					};
392				};
393
394				spi0_ss0_pins: spi0_ss0 {
395					mux {
396						groups = "spi0_ss0";
397						function = "spi0";
398					};
399				};
400
401				spi0_ss1_pins: spi0_ss1 {
402					mux {
403						groups = "spi0_ss1";
404						function = "spi0";
405					};
406				};
407
408				spi0_ss2_pins: spi0_ss2 {
409					mux {
410						groups = "spi0_ss2";
411						function = "spi0";
412					};
413				};
414
415
416				spi1_a_pins: spi1_a {
417					mux {
418						groups = "spi1_miso_a",
419							"spi1_mosi_a",
420							"spi1_clk_a";
421						function = "spi1";
422					};
423				};
424
425				spi1_ss0_a_pins: spi1_ss0_a {
426					mux {
427						groups = "spi1_ss0_a";
428						function = "spi1";
429					};
430				};
431
432				spi1_ss1_pins: spi1_ss1 {
433					mux {
434						groups = "spi1_ss1";
435						function = "spi1";
436					};
437				};
438
439				spi1_x_pins: spi1_x {
440					mux {
441						groups = "spi1_miso_x",
442							"spi1_mosi_x",
443							"spi1_clk_x";
444						function = "spi1";
445					};
446				};
447
448				spi1_ss0_x_pins: spi1_ss0_x {
449					mux {
450						groups = "spi1_ss0_x";
451						function = "spi1";
452					};
453				};
454			};
455		};
456
457		sram: sram@fffc0000 {
458			compatible = "amlogic,meson-axg-sram", "mmio-sram";
459			reg = <0x0 0xfffc0000 0x0 0x20000>;
460			#address-cells = <1>;
461			#size-cells = <1>;
462			ranges = <0 0x0 0xfffc0000 0x20000>;
463
464			cpu_scp_lpri: scp-shmem@0 {
465				compatible = "amlogic,meson-axg-scp-shmem";
466				reg = <0x13000 0x400>;
467			};
468
469			cpu_scp_hpri: scp-shmem@200 {
470				compatible = "amlogic,meson-axg-scp-shmem";
471				reg = <0x13400 0x400>;
472			};
473		};
474
475		aobus: bus@ff800000 {
476			compatible = "simple-bus";
477			reg = <0x0 0xff800000 0x0 0x100000>;
478			#address-cells = <2>;
479			#size-cells = <2>;
480			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
481
482			pinctrl_aobus: pinctrl@14 {
483				compatible = "amlogic,meson-axg-aobus-pinctrl";
484				#address-cells = <2>;
485				#size-cells = <2>;
486				ranges;
487
488				gpio_ao: bank@14 {
489					reg = <0x0 0x00014 0x0 0x8>,
490						<0x0 0x0002c 0x0 0x4>,
491						<0x0 0x00024 0x0 0x8>;
492					reg-names = "mux", "pull", "gpio";
493					gpio-controller;
494					#gpio-cells = <2>;
495					gpio-ranges = <&pinctrl_aobus 0 0 15>;
496				};
497
498				remote_input_ao_pins: remote_input_ao {
499					mux {
500						groups = "remote_input_ao";
501						function = "remote_input_ao";
502					};
503				};
504			};
505
506			pwm_AO_ab: pwm@7000 {
507				compatible = "amlogic,meson-axg-ao-pwm";
508				reg = <0x0 0x07000 0x0 0x20>;
509				#pwm-cells = <3>;
510				status = "disabled";
511			};
512
513			pwm_AO_cd: pwm@2000 {
514				compatible = "amlogic,axg-ao-pwm";
515				reg = <0x0 0x02000  0x0 0x20>;
516				#pwm-cells = <3>;
517				status = "disabled";
518			};
519
520			uart_AO: serial@3000 {
521				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
522				reg = <0x0 0x3000 0x0 0x18>;
523				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
524				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
525				clock-names = "xtal", "pclk", "baud";
526				status = "disabled";
527			};
528
529			uart_AO_B: serial@4000 {
530				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
531				reg = <0x0 0x4000 0x0 0x18>;
532				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
533				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
534				clock-names = "xtal", "pclk", "baud";
535				status = "disabled";
536			};
537
538			ir: ir@8000 {
539				compatible = "amlogic,meson-gxbb-ir";
540				reg = <0x0 0x8000 0x0 0x20>;
541				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
542				status = "disabled";
543			};
544		};
545	};
546};
547