1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 reserved-memory { 128 #address-cells = <2>; 129 #size-cells = <2>; 130 ranges; 131 132 /* 16 MiB reserved for Hardware ROM Firmware */ 133 hwrom_reserved: hwrom@0 { 134 reg = <0x0 0x0 0x0 0x1000000>; 135 no-map; 136 }; 137 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 139 secmon_reserved: secmon@5000000 { 140 reg = <0x0 0x05000000 0x0 0x300000>; 141 no-map; 142 }; 143 }; 144 145 scpi { 146 compatible = "arm,scpi-pre-1.0"; 147 mboxes = <&mailbox 1 &mailbox 2>; 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 149 150 scpi_clocks: clocks { 151 compatible = "arm,scpi-clocks"; 152 153 scpi_dvfs: clock-controller { 154 compatible = "arm,scpi-dvfs-clocks"; 155 #clock-cells = <1>; 156 clock-indices = <0>; 157 clock-output-names = "vcpu"; 158 }; 159 }; 160 161 scpi_sensors: sensors { 162 compatible = "amlogic,meson-gxbb-scpi-sensors"; 163 #thermal-sensor-cells = <1>; 164 }; 165 }; 166 167 soc { 168 compatible = "simple-bus"; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 ethmac: ethernet@ff3f0000 { 174 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 175 reg = <0x0 0xff3f0000 0x0 0x10000 176 0x0 0xff634540 0x0 0x8>; 177 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "macirq"; 179 clocks = <&clkc CLKID_ETH>, 180 <&clkc CLKID_FCLK_DIV2>, 181 <&clkc CLKID_MPLL2>; 182 clock-names = "stmmaceth", "clkin0", "clkin1"; 183 status = "disabled"; 184 }; 185 186 pdm: audio-controller@ff632000 { 187 compatible = "amlogic,axg-pdm"; 188 reg = <0x0 0xff632000 0x0 0x34>; 189 #sound-dai-cells = <0>; 190 sound-name-prefix = "PDM"; 191 clocks = <&clkc_audio AUD_CLKID_PDM>, 192 <&clkc_audio AUD_CLKID_PDM_DCLK>, 193 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 194 clock-names = "pclk", "dclk", "sysclk"; 195 status = "disabled"; 196 }; 197 198 periphs: bus@ff634000 { 199 compatible = "simple-bus"; 200 reg = <0x0 0xff634000 0x0 0x2000>; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 204 205 hwrng: rng@18 { 206 compatible = "amlogic,meson-rng"; 207 reg = <0x0 0x18 0x0 0x4>; 208 clocks = <&clkc CLKID_RNG0>; 209 clock-names = "core"; 210 }; 211 212 pinctrl_periphs: pinctrl@480 { 213 compatible = "amlogic,meson-axg-periphs-pinctrl"; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 ranges; 217 218 gpio: bank@480 { 219 reg = <0x0 0x00480 0x0 0x40>, 220 <0x0 0x004e8 0x0 0x14>, 221 <0x0 0x00520 0x0 0x14>, 222 <0x0 0x00430 0x0 0x3c>; 223 reg-names = "mux", "pull", "pull-enable", "gpio"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&pinctrl_periphs 0 0 86>; 227 }; 228 229 i2c0_pins: i2c0 { 230 mux { 231 groups = "i2c0_sck", 232 "i2c0_sda"; 233 function = "i2c0"; 234 bias-disable; 235 }; 236 }; 237 238 i2c1_x_pins: i2c1_x { 239 mux { 240 groups = "i2c1_sck_x", 241 "i2c1_sda_x"; 242 function = "i2c1"; 243 bias-disable; 244 }; 245 }; 246 247 i2c1_z_pins: i2c1_z { 248 mux { 249 groups = "i2c1_sck_z", 250 "i2c1_sda_z"; 251 function = "i2c1"; 252 bias-disable; 253 }; 254 }; 255 256 i2c2_a_pins: i2c2_a { 257 mux { 258 groups = "i2c2_sck_a", 259 "i2c2_sda_a"; 260 function = "i2c2"; 261 bias-disable; 262 }; 263 }; 264 265 i2c2_x_pins: i2c2_x { 266 mux { 267 groups = "i2c2_sck_x", 268 "i2c2_sda_x"; 269 function = "i2c2"; 270 bias-disable; 271 }; 272 }; 273 274 i2c3_a6_pins: i2c3_a6 { 275 mux { 276 groups = "i2c3_sda_a6", 277 "i2c3_sck_a7"; 278 function = "i2c3"; 279 bias-disable; 280 }; 281 }; 282 283 i2c3_a12_pins: i2c3_a12 { 284 mux { 285 groups = "i2c3_sda_a12", 286 "i2c3_sck_a13"; 287 function = "i2c3"; 288 bias-disable; 289 }; 290 }; 291 292 i2c3_a19_pins: i2c3_a19 { 293 mux { 294 groups = "i2c3_sda_a19", 295 "i2c3_sck_a20"; 296 function = "i2c3"; 297 bias-disable; 298 }; 299 }; 300 301 emmc_pins: emmc { 302 mux { 303 groups = "emmc_nand_d0", 304 "emmc_nand_d1", 305 "emmc_nand_d2", 306 "emmc_nand_d3", 307 "emmc_nand_d4", 308 "emmc_nand_d5", 309 "emmc_nand_d6", 310 "emmc_nand_d7", 311 "emmc_clk", 312 "emmc_cmd", 313 "emmc_ds"; 314 function = "emmc"; 315 bias-disable; 316 }; 317 }; 318 319 emmc_clk_gate_pins: emmc_clk_gate { 320 mux { 321 groups = "BOOT_8"; 322 function = "gpio_periphs"; 323 bias-pull-down; 324 }; 325 }; 326 327 eth_rgmii_x_pins: eth-x-rgmii { 328 mux { 329 groups = "eth_mdio_x", 330 "eth_mdc_x", 331 "eth_rgmii_rx_clk_x", 332 "eth_rx_dv_x", 333 "eth_rxd0_x", 334 "eth_rxd1_x", 335 "eth_rxd2_rgmii", 336 "eth_rxd3_rgmii", 337 "eth_rgmii_tx_clk", 338 "eth_txen_x", 339 "eth_txd0_x", 340 "eth_txd1_x", 341 "eth_txd2_rgmii", 342 "eth_txd3_rgmii"; 343 function = "eth"; 344 bias-disable; 345 }; 346 }; 347 348 eth_rgmii_y_pins: eth-y-rgmii { 349 mux { 350 groups = "eth_mdio_y", 351 "eth_mdc_y", 352 "eth_rgmii_rx_clk_y", 353 "eth_rx_dv_y", 354 "eth_rxd0_y", 355 "eth_rxd1_y", 356 "eth_rxd2_rgmii", 357 "eth_rxd3_rgmii", 358 "eth_rgmii_tx_clk", 359 "eth_txen_y", 360 "eth_txd0_y", 361 "eth_txd1_y", 362 "eth_txd2_rgmii", 363 "eth_txd3_rgmii"; 364 function = "eth"; 365 bias-disable; 366 }; 367 }; 368 369 eth_rmii_x_pins: eth-x-rmii { 370 mux { 371 groups = "eth_mdio_x", 372 "eth_mdc_x", 373 "eth_rgmii_rx_clk_x", 374 "eth_rx_dv_x", 375 "eth_rxd0_x", 376 "eth_rxd1_x", 377 "eth_txen_x", 378 "eth_txd0_x", 379 "eth_txd1_x"; 380 function = "eth"; 381 bias-disable; 382 }; 383 }; 384 385 eth_rmii_y_pins: eth-y-rmii { 386 mux { 387 groups = "eth_mdio_y", 388 "eth_mdc_y", 389 "eth_rgmii_rx_clk_y", 390 "eth_rx_dv_y", 391 "eth_rxd0_y", 392 "eth_rxd1_y", 393 "eth_txen_y", 394 "eth_txd0_y", 395 "eth_txd1_y"; 396 function = "eth"; 397 bias-disable; 398 }; 399 }; 400 401 mclk_b_pins: mclk_b { 402 mux { 403 groups = "mclk_b"; 404 function = "mclk_b"; 405 bias-disable; 406 }; 407 }; 408 409 mclk_c_pins: mclk_c { 410 mux { 411 groups = "mclk_c"; 412 function = "mclk_c"; 413 bias-disable; 414 }; 415 }; 416 417 pdm_dclk_a14_pins: pdm_dclk_a14 { 418 mux { 419 groups = "pdm_dclk_a14"; 420 function = "pdm"; 421 bias-disable; 422 }; 423 }; 424 425 pdm_dclk_a19_pins: pdm_dclk_a19 { 426 mux { 427 groups = "pdm_dclk_a19"; 428 function = "pdm"; 429 bias-disable; 430 }; 431 }; 432 433 pdm_din0_pins: pdm_din0 { 434 mux { 435 groups = "pdm_din0"; 436 function = "pdm"; 437 bias-disable; 438 }; 439 }; 440 441 pdm_din1_pins: pdm_din1 { 442 mux { 443 groups = "pdm_din1"; 444 function = "pdm"; 445 bias-disable; 446 }; 447 }; 448 449 pdm_din2_pins: pdm_din2 { 450 mux { 451 groups = "pdm_din2"; 452 function = "pdm"; 453 bias-disable; 454 }; 455 }; 456 457 pdm_din3_pins: pdm_din3 { 458 mux { 459 groups = "pdm_din3"; 460 function = "pdm"; 461 bias-disable; 462 }; 463 }; 464 465 pwm_a_a_pins: pwm_a_a { 466 mux { 467 groups = "pwm_a_a"; 468 function = "pwm_a"; 469 bias-disable; 470 }; 471 }; 472 473 pwm_a_x18_pins: pwm_a_x18 { 474 mux { 475 groups = "pwm_a_x18"; 476 function = "pwm_a"; 477 bias-disable; 478 }; 479 }; 480 481 pwm_a_x20_pins: pwm_a_x20 { 482 mux { 483 groups = "pwm_a_x20"; 484 function = "pwm_a"; 485 bias-disable; 486 }; 487 }; 488 489 pwm_a_z_pins: pwm_a_z { 490 mux { 491 groups = "pwm_a_z"; 492 function = "pwm_a"; 493 bias-disable; 494 }; 495 }; 496 497 pwm_b_a_pins: pwm_b_a { 498 mux { 499 groups = "pwm_b_a"; 500 function = "pwm_b"; 501 bias-disable; 502 }; 503 }; 504 505 pwm_b_x_pins: pwm_b_x { 506 mux { 507 groups = "pwm_b_x"; 508 function = "pwm_b"; 509 bias-disable; 510 }; 511 }; 512 513 pwm_b_z_pins: pwm_b_z { 514 mux { 515 groups = "pwm_b_z"; 516 function = "pwm_b"; 517 bias-disable; 518 }; 519 }; 520 521 pwm_c_a_pins: pwm_c_a { 522 mux { 523 groups = "pwm_c_a"; 524 function = "pwm_c"; 525 bias-disable; 526 }; 527 }; 528 529 pwm_c_x10_pins: pwm_c_x10 { 530 mux { 531 groups = "pwm_c_x10"; 532 function = "pwm_c"; 533 bias-disable; 534 }; 535 }; 536 537 pwm_c_x17_pins: pwm_c_x17 { 538 mux { 539 groups = "pwm_c_x17"; 540 function = "pwm_c"; 541 bias-disable; 542 }; 543 }; 544 545 pwm_d_x11_pins: pwm_d_x11 { 546 mux { 547 groups = "pwm_d_x11"; 548 function = "pwm_d"; 549 bias-disable; 550 }; 551 }; 552 553 pwm_d_x16_pins: pwm_d_x16 { 554 mux { 555 groups = "pwm_d_x16"; 556 function = "pwm_d"; 557 bias-disable; 558 }; 559 }; 560 561 sdio_pins: sdio { 562 mux { 563 groups = "sdio_d0", 564 "sdio_d1", 565 "sdio_d2", 566 "sdio_d3", 567 "sdio_cmd", 568 "sdio_clk"; 569 function = "sdio"; 570 bias-disable; 571 }; 572 }; 573 574 sdio_clk_gate_pins: sdio_clk_gate { 575 mux { 576 groups = "GPIOX_4"; 577 function = "gpio_periphs"; 578 bias-pull-down; 579 }; 580 }; 581 582 spdif_in_z_pins: spdif_in_z { 583 mux { 584 groups = "spdif_in_z"; 585 function = "spdif_in"; 586 bias-disable; 587 }; 588 }; 589 590 spdif_in_a1_pins: spdif_in_a1 { 591 mux { 592 groups = "spdif_in_a1"; 593 function = "spdif_in"; 594 bias-disable; 595 }; 596 }; 597 598 spdif_in_a7_pins: spdif_in_a7 { 599 mux { 600 groups = "spdif_in_a7"; 601 function = "spdif_in"; 602 bias-disable; 603 }; 604 }; 605 606 spdif_in_a19_pins: spdif_in_a19 { 607 mux { 608 groups = "spdif_in_a19"; 609 function = "spdif_in"; 610 bias-disable; 611 }; 612 }; 613 614 spdif_in_a20_pins: spdif_in_a20 { 615 mux { 616 groups = "spdif_in_a20"; 617 function = "spdif_in"; 618 bias-disable; 619 }; 620 }; 621 622 spdif_out_a1_pins: spdif_out_a1 { 623 mux { 624 groups = "spdif_out_a1"; 625 function = "spdif_out"; 626 bias-disable; 627 }; 628 }; 629 630 spdif_out_a11_pins: spdif_out_a11 { 631 mux { 632 groups = "spdif_out_a11"; 633 function = "spdif_out"; 634 bias-disable; 635 }; 636 }; 637 638 spdif_out_a19_pins: spdif_out_a19 { 639 mux { 640 groups = "spdif_out_a19"; 641 function = "spdif_out"; 642 bias-disable; 643 }; 644 }; 645 646 spdif_out_a20_pins: spdif_out_a20 { 647 mux { 648 groups = "spdif_out_a20"; 649 function = "spdif_out"; 650 bias-disable; 651 }; 652 }; 653 654 spdif_out_z_pins: spdif_out_z { 655 mux { 656 groups = "spdif_out_z"; 657 function = "spdif_out"; 658 bias-disable; 659 }; 660 }; 661 662 spi0_pins: spi0 { 663 mux { 664 groups = "spi0_miso", 665 "spi0_mosi", 666 "spi0_clk"; 667 function = "spi0"; 668 bias-disable; 669 }; 670 }; 671 672 spi0_ss0_pins: spi0_ss0 { 673 mux { 674 groups = "spi0_ss0"; 675 function = "spi0"; 676 bias-disable; 677 }; 678 }; 679 680 spi0_ss1_pins: spi0_ss1 { 681 mux { 682 groups = "spi0_ss1"; 683 function = "spi0"; 684 bias-disable; 685 }; 686 }; 687 688 spi0_ss2_pins: spi0_ss2 { 689 mux { 690 groups = "spi0_ss2"; 691 function = "spi0"; 692 bias-disable; 693 }; 694 }; 695 696 spi1_a_pins: spi1_a { 697 mux { 698 groups = "spi1_miso_a", 699 "spi1_mosi_a", 700 "spi1_clk_a"; 701 function = "spi1"; 702 bias-disable; 703 }; 704 }; 705 706 spi1_ss0_a_pins: spi1_ss0_a { 707 mux { 708 groups = "spi1_ss0_a"; 709 function = "spi1"; 710 bias-disable; 711 }; 712 }; 713 714 spi1_ss1_pins: spi1_ss1 { 715 mux { 716 groups = "spi1_ss1"; 717 function = "spi1"; 718 bias-disable; 719 }; 720 }; 721 722 spi1_x_pins: spi1_x { 723 mux { 724 groups = "spi1_miso_x", 725 "spi1_mosi_x", 726 "spi1_clk_x"; 727 function = "spi1"; 728 bias-disable; 729 }; 730 }; 731 732 spi1_ss0_x_pins: spi1_ss0_x { 733 mux { 734 groups = "spi1_ss0_x"; 735 function = "spi1"; 736 bias-disable; 737 }; 738 }; 739 740 tdma_din0_pins: tdma_din0 { 741 mux { 742 groups = "tdma_din0"; 743 function = "tdma"; 744 bias-disable; 745 }; 746 }; 747 748 tdma_dout0_x14_pins: tdma_dout0_x14 { 749 mux { 750 groups = "tdma_dout0_x14"; 751 function = "tdma"; 752 bias-disable; 753 }; 754 }; 755 756 tdma_dout0_x15_pins: tdma_dout0_x15 { 757 mux { 758 groups = "tdma_dout0_x15"; 759 function = "tdma"; 760 bias-disable; 761 }; 762 }; 763 764 tdma_dout1_pins: tdma_dout1 { 765 mux { 766 groups = "tdma_dout1"; 767 function = "tdma"; 768 bias-disable; 769 }; 770 }; 771 772 tdma_din1_pins: tdma_din1 { 773 mux { 774 groups = "tdma_din1"; 775 function = "tdma"; 776 bias-disable; 777 }; 778 }; 779 780 tdma_fs_pins: tdma_fs { 781 mux { 782 groups = "tdma_fs"; 783 function = "tdma"; 784 bias-disable; 785 }; 786 }; 787 788 tdma_fs_slv_pins: tdma_fs_slv { 789 mux { 790 groups = "tdma_fs_slv"; 791 function = "tdma"; 792 bias-disable; 793 }; 794 }; 795 796 tdma_sclk_pins: tdma_sclk { 797 mux { 798 groups = "tdma_sclk"; 799 function = "tdma"; 800 bias-disable; 801 }; 802 }; 803 804 tdma_sclk_slv_pins: tdma_sclk_slv { 805 mux { 806 groups = "tdma_sclk_slv"; 807 function = "tdma"; 808 bias-disable; 809 }; 810 }; 811 812 tdmb_din0_pins: tdmb_din0 { 813 mux { 814 groups = "tdmb_din0"; 815 function = "tdmb"; 816 bias-disable; 817 }; 818 }; 819 820 tdmb_din1_pins: tdmb_din1 { 821 mux { 822 groups = "tdmb_din1"; 823 function = "tdmb"; 824 bias-disable; 825 }; 826 }; 827 828 tdmb_din2_pins: tdmb_din2 { 829 mux { 830 groups = "tdmb_din2"; 831 function = "tdmb"; 832 bias-disable; 833 }; 834 }; 835 836 tdmb_din3_pins: tdmb_din3 { 837 mux { 838 groups = "tdmb_din3"; 839 function = "tdmb"; 840 bias-disable; 841 }; 842 }; 843 844 tdmb_dout0_pins: tdmb_dout0 { 845 mux { 846 groups = "tdmb_dout0"; 847 function = "tdmb"; 848 bias-disable; 849 }; 850 }; 851 852 tdmb_dout1_pins: tdmb_dout1 { 853 mux { 854 groups = "tdmb_dout1"; 855 function = "tdmb"; 856 bias-disable; 857 }; 858 }; 859 860 tdmb_dout2_pins: tdmb_dout2 { 861 mux { 862 groups = "tdmb_dout2"; 863 function = "tdmb"; 864 bias-disable; 865 }; 866 }; 867 868 tdmb_dout3_pins: tdmb_dout3 { 869 mux { 870 groups = "tdmb_dout3"; 871 function = "tdmb"; 872 bias-disable; 873 }; 874 }; 875 876 tdmb_fs_pins: tdmb_fs { 877 mux { 878 groups = "tdmb_fs"; 879 function = "tdmb"; 880 bias-disable; 881 }; 882 }; 883 884 tdmb_fs_slv_pins: tdmb_fs_slv { 885 mux { 886 groups = "tdmb_fs_slv"; 887 function = "tdmb"; 888 bias-disable; 889 }; 890 }; 891 892 tdmb_sclk_pins: tdmb_sclk { 893 mux { 894 groups = "tdmb_sclk"; 895 function = "tdmb"; 896 bias-disable; 897 }; 898 }; 899 900 tdmb_sclk_slv_pins: tdmb_sclk_slv { 901 mux { 902 groups = "tdmb_sclk_slv"; 903 function = "tdmb"; 904 bias-disable; 905 }; 906 }; 907 908 tdmc_fs_pins: tdmc_fs { 909 mux { 910 groups = "tdmc_fs"; 911 function = "tdmc"; 912 bias-disable; 913 }; 914 }; 915 916 tdmc_fs_slv_pins: tdmc_fs_slv { 917 mux { 918 groups = "tdmc_fs_slv"; 919 function = "tdmc"; 920 bias-disable; 921 }; 922 }; 923 924 tdmc_sclk_pins: tdmc_sclk { 925 mux { 926 groups = "tdmc_sclk"; 927 function = "tdmc"; 928 bias-disable; 929 }; 930 }; 931 932 tdmc_sclk_slv_pins: tdmc_sclk_slv { 933 mux { 934 groups = "tdmc_sclk_slv"; 935 function = "tdmc"; 936 bias-disable; 937 }; 938 }; 939 940 tdmc_din0_pins: tdmc_din0 { 941 mux { 942 groups = "tdmc_din0"; 943 function = "tdmc"; 944 bias-disable; 945 }; 946 }; 947 948 tdmc_din1_pins: tdmc_din1 { 949 mux { 950 groups = "tdmc_din1"; 951 function = "tdmc"; 952 bias-disable; 953 }; 954 }; 955 956 tdmc_din2_pins: tdmc_din2 { 957 mux { 958 groups = "tdmc_din2"; 959 function = "tdmc"; 960 bias-disable; 961 }; 962 }; 963 964 tdmc_din3_pins: tdmc_din3 { 965 mux { 966 groups = "tdmc_din3"; 967 function = "tdmc"; 968 bias-disable; 969 }; 970 }; 971 972 tdmc_dout0_pins: tdmc_dout0 { 973 mux { 974 groups = "tdmc_dout0"; 975 function = "tdmc"; 976 bias-disable; 977 }; 978 }; 979 980 tdmc_dout1_pins: tdmc_dout1 { 981 mux { 982 groups = "tdmc_dout1"; 983 function = "tdmc"; 984 bias-disable; 985 }; 986 }; 987 988 tdmc_dout2_pins: tdmc_dout2 { 989 mux { 990 groups = "tdmc_dout2"; 991 function = "tdmc"; 992 bias-disable; 993 }; 994 }; 995 996 tdmc_dout3_pins: tdmc_dout3 { 997 mux { 998 groups = "tdmc_dout3"; 999 function = "tdmc"; 1000 bias-disable; 1001 }; 1002 }; 1003 1004 uart_a_pins: uart_a { 1005 mux { 1006 groups = "uart_tx_a", 1007 "uart_rx_a"; 1008 function = "uart_a"; 1009 bias-disable; 1010 }; 1011 }; 1012 1013 uart_a_cts_rts_pins: uart_a_cts_rts { 1014 mux { 1015 groups = "uart_cts_a", 1016 "uart_rts_a"; 1017 function = "uart_a"; 1018 bias-disable; 1019 }; 1020 }; 1021 1022 uart_b_x_pins: uart_b_x { 1023 mux { 1024 groups = "uart_tx_b_x", 1025 "uart_rx_b_x"; 1026 function = "uart_b"; 1027 bias-disable; 1028 }; 1029 }; 1030 1031 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1032 mux { 1033 groups = "uart_cts_b_x", 1034 "uart_rts_b_x"; 1035 function = "uart_b"; 1036 bias-disable; 1037 }; 1038 }; 1039 1040 uart_b_z_pins: uart_b_z { 1041 mux { 1042 groups = "uart_tx_b_z", 1043 "uart_rx_b_z"; 1044 function = "uart_b"; 1045 bias-disable; 1046 }; 1047 }; 1048 1049 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1050 mux { 1051 groups = "uart_cts_b_z", 1052 "uart_rts_b_z"; 1053 function = "uart_b"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 uart_ao_b_z_pins: uart_ao_b_z { 1059 mux { 1060 groups = "uart_ao_tx_b_z", 1061 "uart_ao_rx_b_z"; 1062 function = "uart_ao_b_z"; 1063 bias-disable; 1064 }; 1065 }; 1066 1067 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1068 mux { 1069 groups = "uart_ao_cts_b_z", 1070 "uart_ao_rts_b_z"; 1071 function = "uart_ao_b_z"; 1072 bias-disable; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 hiubus: bus@ff63c000 { 1079 compatible = "simple-bus"; 1080 reg = <0x0 0xff63c000 0x0 0x1c00>; 1081 #address-cells = <2>; 1082 #size-cells = <2>; 1083 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1084 1085 sysctrl: system-controller@0 { 1086 compatible = "amlogic,meson-axg-hhi-sysctrl", 1087 "simple-mfd", "syscon"; 1088 reg = <0 0 0 0x400>; 1089 1090 clkc: clock-controller { 1091 compatible = "amlogic,axg-clkc"; 1092 #clock-cells = <1>; 1093 clocks = <&xtal>; 1094 clock-names = "xtal"; 1095 }; 1096 }; 1097 }; 1098 1099 mailbox: mailbox@ff63c404 { 1100 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1101 reg = <0 0xff63c404 0 0x4c>; 1102 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1103 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1104 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1105 #mbox-cells = <1>; 1106 }; 1107 1108 audio: bus@ff642000 { 1109 compatible = "simple-bus"; 1110 reg = <0x0 0xff642000 0x0 0x2000>; 1111 #address-cells = <2>; 1112 #size-cells = <2>; 1113 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1114 1115 clkc_audio: clock-controller@0 { 1116 compatible = "amlogic,axg-audio-clkc"; 1117 reg = <0x0 0x0 0x0 0xb4>; 1118 #clock-cells = <1>; 1119 1120 clocks = <&clkc CLKID_AUDIO>, 1121 <&clkc CLKID_MPLL0>, 1122 <&clkc CLKID_MPLL1>, 1123 <&clkc CLKID_MPLL2>, 1124 <&clkc CLKID_MPLL3>, 1125 <&clkc CLKID_HIFI_PLL>, 1126 <&clkc CLKID_FCLK_DIV3>, 1127 <&clkc CLKID_FCLK_DIV4>, 1128 <&clkc CLKID_GP0_PLL>; 1129 clock-names = "pclk", 1130 "mst_in0", 1131 "mst_in1", 1132 "mst_in2", 1133 "mst_in3", 1134 "mst_in4", 1135 "mst_in5", 1136 "mst_in6", 1137 "mst_in7"; 1138 1139 resets = <&reset RESET_AUDIO>; 1140 }; 1141 1142 toddr_a: audio-controller@100 { 1143 compatible = "amlogic,axg-toddr"; 1144 reg = <0x0 0x100 0x0 0x1c>; 1145 #sound-dai-cells = <0>; 1146 sound-name-prefix = "TODDR_A"; 1147 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1148 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1149 resets = <&arb AXG_ARB_TODDR_A>; 1150 status = "disabled"; 1151 }; 1152 1153 toddr_b: audio-controller@140 { 1154 compatible = "amlogic,axg-toddr"; 1155 reg = <0x0 0x140 0x0 0x1c>; 1156 #sound-dai-cells = <0>; 1157 sound-name-prefix = "TODDR_B"; 1158 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1159 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1160 resets = <&arb AXG_ARB_TODDR_B>; 1161 status = "disabled"; 1162 }; 1163 1164 toddr_c: audio-controller@180 { 1165 compatible = "amlogic,axg-toddr"; 1166 reg = <0x0 0x180 0x0 0x1c>; 1167 #sound-dai-cells = <0>; 1168 sound-name-prefix = "TODDR_C"; 1169 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1170 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1171 resets = <&arb AXG_ARB_TODDR_C>; 1172 status = "disabled"; 1173 }; 1174 1175 frddr_a: audio-controller@1c0 { 1176 compatible = "amlogic,axg-frddr"; 1177 reg = <0x0 0x1c0 0x0 0x1c>; 1178 #sound-dai-cells = <0>; 1179 sound-name-prefix = "FRDDR_A"; 1180 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1181 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1182 resets = <&arb AXG_ARB_FRDDR_A>; 1183 status = "disabled"; 1184 }; 1185 1186 frddr_b: audio-controller@200 { 1187 compatible = "amlogic,axg-frddr"; 1188 reg = <0x0 0x200 0x0 0x1c>; 1189 #sound-dai-cells = <0>; 1190 sound-name-prefix = "FRDDR_B"; 1191 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1192 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1193 resets = <&arb AXG_ARB_FRDDR_B>; 1194 status = "disabled"; 1195 }; 1196 1197 frddr_c: audio-controller@240 { 1198 compatible = "amlogic,axg-frddr"; 1199 reg = <0x0 0x240 0x0 0x1c>; 1200 #sound-dai-cells = <0>; 1201 sound-name-prefix = "FRDDR_C"; 1202 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1203 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1204 resets = <&arb AXG_ARB_FRDDR_C>; 1205 status = "disabled"; 1206 }; 1207 1208 arb: reset-controller@280 { 1209 compatible = "amlogic,meson-axg-audio-arb"; 1210 reg = <0x0 0x280 0x0 0x4>; 1211 #reset-cells = <1>; 1212 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1213 }; 1214 1215 tdmin_a: audio-controller@300 { 1216 compatible = "amlogic,axg-tdmin"; 1217 reg = <0x0 0x300 0x0 0x40>; 1218 sound-name-prefix = "TDMIN_A"; 1219 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1220 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1221 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1222 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1223 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1224 clock-names = "pclk", "sclk", "sclk_sel", 1225 "lrclk", "lrclk_sel"; 1226 status = "disabled"; 1227 }; 1228 1229 tdmin_b: audio-controller@340 { 1230 compatible = "amlogic,axg-tdmin"; 1231 reg = <0x0 0x340 0x0 0x40>; 1232 sound-name-prefix = "TDMIN_B"; 1233 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1234 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1235 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1236 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1237 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1238 clock-names = "pclk", "sclk", "sclk_sel", 1239 "lrclk", "lrclk_sel"; 1240 status = "disabled"; 1241 }; 1242 1243 tdmin_c: audio-controller@380 { 1244 compatible = "amlogic,axg-tdmin"; 1245 reg = <0x0 0x380 0x0 0x40>; 1246 sound-name-prefix = "TDMIN_C"; 1247 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1248 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1249 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1250 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1251 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1252 clock-names = "pclk", "sclk", "sclk_sel", 1253 "lrclk", "lrclk_sel"; 1254 status = "disabled"; 1255 }; 1256 1257 tdmin_lb: audio-controller@3c0 { 1258 compatible = "amlogic,axg-tdmin"; 1259 reg = <0x0 0x3c0 0x0 0x40>; 1260 sound-name-prefix = "TDMIN_LB"; 1261 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1262 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1263 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1264 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1265 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1266 clock-names = "pclk", "sclk", "sclk_sel", 1267 "lrclk", "lrclk_sel"; 1268 status = "disabled"; 1269 }; 1270 1271 spdifin: audio-controller@400 { 1272 compatible = "amlogic,axg-spdifin"; 1273 reg = <0x0 0x400 0x0 0x30>; 1274 #sound-dai-cells = <0>; 1275 sound-name-prefix = "SPDIFIN"; 1276 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1277 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1278 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1279 clock-names = "pclk", "refclk"; 1280 status = "disabled"; 1281 }; 1282 1283 spdifout: audio-controller@480 { 1284 compatible = "amlogic,axg-spdifout"; 1285 reg = <0x0 0x480 0x0 0x50>; 1286 #sound-dai-cells = <0>; 1287 sound-name-prefix = "SPDIFOUT"; 1288 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1289 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1290 clock-names = "pclk", "mclk"; 1291 status = "disabled"; 1292 }; 1293 1294 tdmout_a: audio-controller@500 { 1295 compatible = "amlogic,axg-tdmout"; 1296 reg = <0x0 0x500 0x0 0x40>; 1297 sound-name-prefix = "TDMOUT_A"; 1298 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1299 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1300 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1301 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1302 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1303 clock-names = "pclk", "sclk", "sclk_sel", 1304 "lrclk", "lrclk_sel"; 1305 status = "disabled"; 1306 }; 1307 1308 tdmout_b: audio-controller@540 { 1309 compatible = "amlogic,axg-tdmout"; 1310 reg = <0x0 0x540 0x0 0x40>; 1311 sound-name-prefix = "TDMOUT_B"; 1312 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1313 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1314 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1315 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1316 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1317 clock-names = "pclk", "sclk", "sclk_sel", 1318 "lrclk", "lrclk_sel"; 1319 status = "disabled"; 1320 }; 1321 1322 tdmout_c: audio-controller@580 { 1323 compatible = "amlogic,axg-tdmout"; 1324 reg = <0x0 0x580 0x0 0x40>; 1325 sound-name-prefix = "TDMOUT_C"; 1326 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1327 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1328 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1329 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1330 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1331 clock-names = "pclk", "sclk", "sclk_sel", 1332 "lrclk", "lrclk_sel"; 1333 status = "disabled"; 1334 }; 1335 }; 1336 1337 aobus: bus@ff800000 { 1338 compatible = "simple-bus"; 1339 reg = <0x0 0xff800000 0x0 0x100000>; 1340 #address-cells = <2>; 1341 #size-cells = <2>; 1342 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1343 1344 sysctrl_AO: sys-ctrl@0 { 1345 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1346 reg = <0x0 0x0 0x0 0x100>; 1347 1348 clkc_AO: clock-controller { 1349 compatible = "amlogic,meson-axg-aoclkc"; 1350 #clock-cells = <1>; 1351 #reset-cells = <1>; 1352 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1353 clock-names = "xtal", "mpeg-clk"; 1354 }; 1355 }; 1356 1357 pinctrl_aobus: pinctrl@14 { 1358 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 ranges; 1362 1363 gpio_ao: bank@14 { 1364 reg = <0x0 0x00014 0x0 0x8>, 1365 <0x0 0x0002c 0x0 0x4>, 1366 <0x0 0x00024 0x0 0x8>; 1367 reg-names = "mux", "pull", "gpio"; 1368 gpio-controller; 1369 #gpio-cells = <2>; 1370 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1371 }; 1372 1373 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1374 mux { 1375 groups = "i2c_ao_sck_4"; 1376 function = "i2c_ao"; 1377 bias-disable; 1378 }; 1379 }; 1380 1381 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1382 mux { 1383 groups = "i2c_ao_sck_8"; 1384 function = "i2c_ao"; 1385 bias-disable; 1386 }; 1387 }; 1388 1389 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1390 mux { 1391 groups = "i2c_ao_sck_10"; 1392 function = "i2c_ao"; 1393 bias-disable; 1394 }; 1395 }; 1396 1397 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1398 mux { 1399 groups = "i2c_ao_sda_5"; 1400 function = "i2c_ao"; 1401 bias-disable; 1402 }; 1403 }; 1404 1405 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1406 mux { 1407 groups = "i2c_ao_sda_9"; 1408 function = "i2c_ao"; 1409 bias-disable; 1410 }; 1411 }; 1412 1413 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1414 mux { 1415 groups = "i2c_ao_sda_11"; 1416 function = "i2c_ao"; 1417 bias-disable; 1418 }; 1419 }; 1420 1421 remote_input_ao_pins: remote_input_ao { 1422 mux { 1423 groups = "remote_input_ao"; 1424 function = "remote_input_ao"; 1425 bias-disable; 1426 }; 1427 }; 1428 1429 uart_ao_a_pins: uart_ao_a { 1430 mux { 1431 groups = "uart_ao_tx_a", 1432 "uart_ao_rx_a"; 1433 function = "uart_ao_a"; 1434 bias-disable; 1435 }; 1436 }; 1437 1438 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1439 mux { 1440 groups = "uart_ao_cts_a", 1441 "uart_ao_rts_a"; 1442 function = "uart_ao_a"; 1443 bias-disable; 1444 }; 1445 }; 1446 1447 uart_ao_b_pins: uart_ao_b { 1448 mux { 1449 groups = "uart_ao_tx_b", 1450 "uart_ao_rx_b"; 1451 function = "uart_ao_b"; 1452 bias-disable; 1453 }; 1454 }; 1455 1456 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1457 mux { 1458 groups = "uart_ao_cts_b", 1459 "uart_ao_rts_b"; 1460 function = "uart_ao_b"; 1461 bias-disable; 1462 }; 1463 }; 1464 }; 1465 1466 sec_AO: ao-secure@140 { 1467 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1468 reg = <0x0 0x140 0x0 0x140>; 1469 amlogic,has-chip-id; 1470 }; 1471 1472 pwm_AO_cd: pwm@2000 { 1473 compatible = "amlogic,meson-axg-ao-pwm"; 1474 reg = <0x0 0x02000 0x0 0x20>; 1475 #pwm-cells = <3>; 1476 status = "disabled"; 1477 }; 1478 1479 uart_AO: serial@3000 { 1480 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1481 reg = <0x0 0x3000 0x0 0x18>; 1482 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1483 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1484 clock-names = "xtal", "pclk", "baud"; 1485 status = "disabled"; 1486 }; 1487 1488 uart_AO_B: serial@4000 { 1489 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1490 reg = <0x0 0x4000 0x0 0x18>; 1491 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1492 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1493 clock-names = "xtal", "pclk", "baud"; 1494 status = "disabled"; 1495 }; 1496 1497 i2c_AO: i2c@5000 { 1498 compatible = "amlogic,meson-axg-i2c"; 1499 reg = <0x0 0x05000 0x0 0x20>; 1500 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1501 clocks = <&clkc CLKID_AO_I2C>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 1507 pwm_AO_ab: pwm@7000 { 1508 compatible = "amlogic,meson-axg-ao-pwm"; 1509 reg = <0x0 0x07000 0x0 0x20>; 1510 #pwm-cells = <3>; 1511 status = "disabled"; 1512 }; 1513 1514 ir: ir@8000 { 1515 compatible = "amlogic,meson-gxbb-ir"; 1516 reg = <0x0 0x8000 0x0 0x20>; 1517 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1518 status = "disabled"; 1519 }; 1520 1521 saradc: adc@9000 { 1522 compatible = "amlogic,meson-axg-saradc", 1523 "amlogic,meson-saradc"; 1524 reg = <0x0 0x9000 0x0 0x38>; 1525 #io-channel-cells = <1>; 1526 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1527 clocks = <&xtal>, 1528 <&clkc_AO CLKID_AO_SAR_ADC>, 1529 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1530 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1531 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1532 status = "disabled"; 1533 }; 1534 }; 1535 1536 gic: interrupt-controller@ffc01000 { 1537 compatible = "arm,gic-400"; 1538 reg = <0x0 0xffc01000 0 0x1000>, 1539 <0x0 0xffc02000 0 0x2000>, 1540 <0x0 0xffc04000 0 0x2000>, 1541 <0x0 0xffc06000 0 0x2000>; 1542 interrupt-controller; 1543 interrupts = <GIC_PPI 9 1544 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1545 #interrupt-cells = <3>; 1546 #address-cells = <0>; 1547 }; 1548 1549 cbus: bus@ffd00000 { 1550 compatible = "simple-bus"; 1551 reg = <0x0 0xffd00000 0x0 0x25000>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1555 1556 reset: reset-controller@1004 { 1557 compatible = "amlogic,meson-axg-reset"; 1558 reg = <0x0 0x01004 0x0 0x9c>; 1559 #reset-cells = <1>; 1560 }; 1561 1562 gpio_intc: interrupt-controller@f080 { 1563 compatible = "amlogic,meson-axg-gpio-intc", 1564 "amlogic,meson-gpio-intc"; 1565 reg = <0x0 0xf080 0x0 0x10>; 1566 interrupt-controller; 1567 #interrupt-cells = <2>; 1568 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1569 }; 1570 1571 watchdog@f0d0 { 1572 compatible = "amlogic,meson-gxbb-wdt"; 1573 reg = <0x0 0xf0d0 0x0 0x10>; 1574 clocks = <&xtal>; 1575 }; 1576 1577 pwm_ab: pwm@1b000 { 1578 compatible = "amlogic,meson-axg-ee-pwm"; 1579 reg = <0x0 0x1b000 0x0 0x20>; 1580 #pwm-cells = <3>; 1581 status = "disabled"; 1582 }; 1583 1584 pwm_cd: pwm@1a000 { 1585 compatible = "amlogic,meson-axg-ee-pwm"; 1586 reg = <0x0 0x1a000 0x0 0x20>; 1587 #pwm-cells = <3>; 1588 status = "disabled"; 1589 }; 1590 1591 spicc0: spi@13000 { 1592 compatible = "amlogic,meson-axg-spicc"; 1593 reg = <0x0 0x13000 0x0 0x3c>; 1594 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&clkc CLKID_SPICC0>; 1596 clock-names = "core"; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 status = "disabled"; 1600 }; 1601 1602 spicc1: spi@15000 { 1603 compatible = "amlogic,meson-axg-spicc"; 1604 reg = <0x0 0x15000 0x0 0x3c>; 1605 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&clkc CLKID_SPICC1>; 1607 clock-names = "core"; 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 status = "disabled"; 1611 }; 1612 1613 clk_msr: clock-measure@18000 { 1614 compatible = "amlogic,meson-axg-clk-measure"; 1615 reg = <0x0 0x18000 0x0 0x10>; 1616 }; 1617 1618 i2c3: i2c@1c000 { 1619 compatible = "amlogic,meson-axg-i2c"; 1620 reg = <0x0 0x1c000 0x0 0x20>; 1621 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1622 clocks = <&clkc CLKID_I2C>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 i2c2: i2c@1d000 { 1629 compatible = "amlogic,meson-axg-i2c"; 1630 reg = <0x0 0x1d000 0x0 0x20>; 1631 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1632 clocks = <&clkc CLKID_I2C>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 status = "disabled"; 1636 }; 1637 1638 i2c1: i2c@1e000 { 1639 compatible = "amlogic,meson-axg-i2c"; 1640 reg = <0x0 0x1e000 0x0 0x20>; 1641 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1642 clocks = <&clkc CLKID_I2C>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c0: i2c@1f000 { 1649 compatible = "amlogic,meson-axg-i2c"; 1650 reg = <0x0 0x1f000 0x0 0x20>; 1651 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1652 clocks = <&clkc CLKID_I2C>; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 }; 1657 1658 uart_B: serial@23000 { 1659 compatible = "amlogic,meson-gx-uart"; 1660 reg = <0x0 0x23000 0x0 0x18>; 1661 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1662 status = "disabled"; 1663 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1664 clock-names = "xtal", "pclk", "baud"; 1665 }; 1666 1667 uart_A: serial@24000 { 1668 compatible = "amlogic,meson-gx-uart"; 1669 reg = <0x0 0x24000 0x0 0x18>; 1670 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1671 status = "disabled"; 1672 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1673 clock-names = "xtal", "pclk", "baud"; 1674 }; 1675 }; 1676 1677 apb: bus@ffe00000 { 1678 compatible = "simple-bus"; 1679 reg = <0x0 0xffe00000 0x0 0x200000>; 1680 #address-cells = <2>; 1681 #size-cells = <2>; 1682 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1683 1684 sd_emmc_b: sd@5000 { 1685 compatible = "amlogic,meson-axg-mmc"; 1686 reg = <0x0 0x5000 0x0 0x800>; 1687 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1688 status = "disabled"; 1689 clocks = <&clkc CLKID_SD_EMMC_B>, 1690 <&clkc CLKID_SD_EMMC_B_CLK0>, 1691 <&clkc CLKID_FCLK_DIV2>; 1692 clock-names = "core", "clkin0", "clkin1"; 1693 resets = <&reset RESET_SD_EMMC_B>; 1694 }; 1695 1696 sd_emmc_c: mmc@7000 { 1697 compatible = "amlogic,meson-axg-mmc"; 1698 reg = <0x0 0x7000 0x0 0x800>; 1699 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1700 status = "disabled"; 1701 clocks = <&clkc CLKID_SD_EMMC_C>, 1702 <&clkc CLKID_SD_EMMC_C_CLK0>, 1703 <&clkc CLKID_FCLK_DIV2>; 1704 clock-names = "core", "clkin0", "clkin1"; 1705 resets = <&reset RESET_SD_EMMC_C>; 1706 }; 1707 }; 1708 1709 sram: sram@fffc0000 { 1710 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1711 reg = <0x0 0xfffc0000 0x0 0x20000>; 1712 #address-cells = <1>; 1713 #size-cells = <1>; 1714 ranges = <0 0x0 0xfffc0000 0x20000>; 1715 1716 cpu_scp_lpri: scp-shmem@13000 { 1717 compatible = "amlogic,meson-axg-scp-shmem"; 1718 reg = <0x13000 0x400>; 1719 }; 1720 1721 cpu_scp_hpri: scp-shmem@13400 { 1722 compatible = "amlogic,meson-axg-scp-shmem"; 1723 reg = <0x13400 0x400>; 1724 }; 1725 }; 1726 }; 1727 1728 timer { 1729 compatible = "arm,armv8-timer"; 1730 interrupts = <GIC_PPI 13 1731 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1732 <GIC_PPI 14 1733 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1734 <GIC_PPI 11 1735 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1736 <GIC_PPI 10 1737 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1738 }; 1739 1740 xtal: xtal-clk { 1741 compatible = "fixed-clock"; 1742 clock-frequency = <24000000>; 1743 clock-output-names = "xtal"; 1744 #clock-cells = <0>; 1745 }; 1746}; 1747