1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		cbus: bus@ffd00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffd00000 0x0 0x25000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
123
124			pwm_ab: pwm@1b000 {
125				compatible = "amlogic,meson-axg-ee-pwm";
126				reg = <0x0 0x1b000 0x0 0x20>;
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			pwm_cd: pwm@1a000 {
132				compatible = "amlogic,meson-axg-ee-pwm";
133				reg = <0x0 0x1a000 0x0 0x20>;
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			reset: reset-controller@1004 {
139				compatible = "amlogic,meson-axg-reset";
140				reg = <0x0 0x01004 0x0 0x9c>;
141				#reset-cells = <1>;
142			};
143
144			spicc0: spi@13000 {
145				compatible = "amlogic,meson-axg-spicc";
146				reg = <0x0 0x13000 0x0 0x3c>;
147				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clkc CLKID_SPICC0>;
149				clock-names = "core";
150				#address-cells = <1>;
151				#size-cells = <0>;
152				status = "disabled";
153			};
154
155			spicc1: spi@15000 {
156				compatible = "amlogic,meson-axg-spicc";
157				reg = <0x0 0x15000 0x0 0x3c>;
158				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159				clocks = <&clkc CLKID_SPICC1>;
160				clock-names = "core";
161				#address-cells = <1>;
162				#size-cells = <0>;
163				status = "disabled";
164			};
165
166			i2c0: i2c@1f000 {
167				compatible = "amlogic,meson-axg-i2c";
168				status = "disabled";
169				reg = <0x0 0x1f000 0x0 0x20>;
170				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
171					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
172				#address-cells = <1>;
173				#size-cells = <0>;
174				clocks = <&clkc CLKID_I2C>;
175				clock-names = "clk_i2c";
176			};
177
178			i2c1: i2c@1e000 {
179				compatible = "amlogic,meson-axg-i2c";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				reg = <0x0 0x1e000 0x0 0x20>;
183				status = "disabled";
184				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
185					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
186				clocks = <&clkc CLKID_I2C>;
187				clock-names = "clk_i2c";
188			};
189
190			i2c2: i2c@1d000 {
191				compatible = "amlogic,meson-axg-i2c";
192				status = "disabled";
193				reg = <0x0 0x1d000 0x0 0x20>;
194				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
195					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
196				#address-cells = <1>;
197				#size-cells = <0>;
198				clocks = <&clkc CLKID_I2C>;
199				clock-names = "clk_i2c";
200			};
201
202			i2c3: i2c@1c000 {
203				compatible = "amlogic,meson-axg-i2c";
204				status = "disabled";
205				reg = <0x0 0x1c000 0x0 0x20>;
206				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
207					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
208				#address-cells = <1>;
209				#size-cells = <0>;
210				clocks = <&clkc CLKID_I2C>;
211				clock-names = "clk_i2c";
212			};
213
214			uart_A: serial@24000 {
215				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
216				reg = <0x0 0x24000 0x0 0x18>;
217				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
218				status = "disabled";
219			};
220
221			uart_B: serial@23000 {
222				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
223				reg = <0x0 0x23000 0x0 0x18>;
224				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
225				status = "disabled";
226			};
227		};
228
229		ethmac: ethernet@ff3f0000 {
230			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
231			reg = <0x0 0xff3f0000 0x0 0x10000
232				0x0 0xff634540 0x0 0x8>;
233			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
234			interrupt-names = "macirq";
235			clocks = <&clkc CLKID_ETH>,
236				 <&clkc CLKID_FCLK_DIV2>,
237				 <&clkc CLKID_MPLL2>;
238			clock-names = "stmmaceth", "clkin0", "clkin1";
239			status = "disabled";
240		};
241
242		gic: interrupt-controller@ffc01000 {
243			compatible = "arm,gic-400";
244			reg = <0x0 0xffc01000 0 0x1000>,
245			      <0x0 0xffc02000 0 0x2000>,
246			      <0x0 0xffc04000 0 0x2000>,
247			      <0x0 0xffc06000 0 0x2000>;
248			interrupt-controller;
249			interrupts = <GIC_PPI 9
250				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
251			#interrupt-cells = <3>;
252			#address-cells = <0>;
253		};
254
255		hiubus: bus@ff63c000 {
256			compatible = "simple-bus";
257			reg = <0x0 0xff63c000 0x0 0x1c00>;
258			#address-cells = <2>;
259			#size-cells = <2>;
260			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
261
262			clkc: clock-controller@0 {
263				compatible = "amlogic,axg-clkc";
264				#clock-cells = <1>;
265				reg = <0x0 0x0 0x0 0x320>;
266			};
267		};
268
269		mailbox: mailbox@ff63dc00 {
270			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
271			reg = <0 0xff63dc00 0 0x400>;
272			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
273				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
274				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
275			#mbox-cells = <1>;
276		};
277
278		periphs: periphs@ff634000 {
279			compatible = "simple-bus";
280			reg = <0x0 0xff634000 0x0 0x2000>;
281			#address-cells = <2>;
282			#size-cells = <2>;
283			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
284
285			hwrng: rng {
286				compatible = "amlogic,meson-rng";
287				reg = <0x0 0x18 0x0 0x4>;
288				clocks = <&clkc CLKID_RNG0>;
289				clock-names = "core";
290			};
291
292			pinctrl_periphs: pinctrl@480 {
293				compatible = "amlogic,meson-axg-periphs-pinctrl";
294				#address-cells = <2>;
295				#size-cells = <2>;
296				ranges;
297
298				gpio: bank@480 {
299					reg = <0x0 0x00480 0x0 0x40>,
300						<0x0 0x004e8 0x0 0x14>,
301						<0x0 0x00520 0x0 0x14>,
302						<0x0 0x00430 0x0 0x3c>;
303					reg-names = "mux", "pull", "pull-enable", "gpio";
304					gpio-controller;
305					#gpio-cells = <2>;
306					gpio-ranges = <&pinctrl_periphs 0 0 86>;
307				};
308
309				eth_rgmii_x_pins: eth-x-rgmii {
310					mux {
311						groups = "eth_mdio_x",
312						       "eth_mdc_x",
313						       "eth_rgmii_rx_clk_x",
314						       "eth_rx_dv_x",
315						       "eth_rxd0_x",
316						       "eth_rxd1_x",
317						       "eth_rxd2_rgmii",
318						       "eth_rxd3_rgmii",
319						       "eth_rgmii_tx_clk",
320						       "eth_txen_x",
321						       "eth_txd0_x",
322						       "eth_txd1_x",
323						       "eth_txd2_rgmii",
324						       "eth_txd3_rgmii";
325						function = "eth";
326					};
327				};
328
329				eth_rgmii_y_pins: eth-y-rgmii {
330					mux {
331						groups = "eth_mdio_y",
332						       "eth_mdc_y",
333						       "eth_rgmii_rx_clk_y",
334						       "eth_rx_dv_y",
335						       "eth_rxd0_y",
336						       "eth_rxd1_y",
337						       "eth_rxd2_rgmii",
338						       "eth_rxd3_rgmii",
339						       "eth_rgmii_tx_clk",
340						       "eth_txen_y",
341						       "eth_txd0_y",
342						       "eth_txd1_y",
343						       "eth_txd2_rgmii",
344						       "eth_txd3_rgmii";
345						function = "eth";
346					};
347				};
348
349				pwm_a_a_pins: pwm_a_a {
350					mux {
351						groups = "pwm_a_a";
352						function = "pwm_a";
353					};
354				};
355
356				pwm_a_x18_pins: pwm_a_x18 {
357					mux {
358						groups = "pwm_a_x18";
359						function = "pwm_a";
360					};
361				};
362
363				pwm_a_x20_pins: pwm_a_x20 {
364					mux {
365						groups = "pwm_a_x20";
366						function = "pwm_a";
367					};
368				};
369
370				pwm_a_z_pins: pwm_a_z {
371					mux {
372						groups = "pwm_a_z";
373						function = "pwm_a";
374					};
375				};
376
377				pwm_b_a_pins: pwm_b_a {
378					mux {
379						groups = "pwm_b_a";
380						function = "pwm_b";
381					};
382				};
383
384				pwm_b_x_pins: pwm_b_x {
385					mux {
386						groups = "pwm_b_x";
387						function = "pwm_b";
388					};
389				};
390
391				pwm_b_z_pins: pwm_b_z {
392					mux {
393						groups = "pwm_b_z";
394						function = "pwm_b";
395					};
396				};
397
398				pwm_c_a_pins: pwm_c_a {
399					mux {
400						groups = "pwm_c_a";
401						function = "pwm_c";
402					};
403				};
404
405				pwm_c_x10_pins: pwm_c_x10 {
406					mux {
407						groups = "pwm_c_x10";
408						function = "pwm_c";
409					};
410				};
411
412				pwm_c_x17_pins: pwm_c_x17 {
413					mux {
414						groups = "pwm_c_x17";
415						function = "pwm_c";
416					};
417				};
418
419				pwm_d_x11_pins: pwm_d_x11 {
420					mux {
421						groups = "pwm_d_x11";
422						function = "pwm_d";
423					};
424				};
425
426				pwm_d_x16_pins: pwm_d_x16 {
427					mux {
428						groups = "pwm_d_x16";
429						function = "pwm_d";
430					};
431				};
432
433				spi0_pins: spi0 {
434					mux {
435						groups = "spi0_miso",
436							"spi0_mosi",
437							"spi0_clk";
438						function = "spi0";
439					};
440				};
441
442				spi0_ss0_pins: spi0_ss0 {
443					mux {
444						groups = "spi0_ss0";
445						function = "spi0";
446					};
447				};
448
449				spi0_ss1_pins: spi0_ss1 {
450					mux {
451						groups = "spi0_ss1";
452						function = "spi0";
453					};
454				};
455
456				spi0_ss2_pins: spi0_ss2 {
457					mux {
458						groups = "spi0_ss2";
459						function = "spi0";
460					};
461				};
462
463
464				spi1_a_pins: spi1_a {
465					mux {
466						groups = "spi1_miso_a",
467							"spi1_mosi_a",
468							"spi1_clk_a";
469						function = "spi1";
470					};
471				};
472
473				spi1_ss0_a_pins: spi1_ss0_a {
474					mux {
475						groups = "spi1_ss0_a";
476						function = "spi1";
477					};
478				};
479
480				spi1_ss1_pins: spi1_ss1 {
481					mux {
482						groups = "spi1_ss1";
483						function = "spi1";
484					};
485				};
486
487				spi1_x_pins: spi1_x {
488					mux {
489						groups = "spi1_miso_x",
490							"spi1_mosi_x",
491							"spi1_clk_x";
492						function = "spi1";
493					};
494				};
495
496				spi1_ss0_x_pins: spi1_ss0_x {
497					mux {
498						groups = "spi1_ss0_x";
499						function = "spi1";
500					};
501				};
502			};
503		};
504
505		sram: sram@fffc0000 {
506			compatible = "amlogic,meson-axg-sram", "mmio-sram";
507			reg = <0x0 0xfffc0000 0x0 0x20000>;
508			#address-cells = <1>;
509			#size-cells = <1>;
510			ranges = <0 0x0 0xfffc0000 0x20000>;
511
512			cpu_scp_lpri: scp-shmem@0 {
513				compatible = "amlogic,meson-axg-scp-shmem";
514				reg = <0x13000 0x400>;
515			};
516
517			cpu_scp_hpri: scp-shmem@200 {
518				compatible = "amlogic,meson-axg-scp-shmem";
519				reg = <0x13400 0x400>;
520			};
521		};
522
523		aobus: bus@ff800000 {
524			compatible = "simple-bus";
525			reg = <0x0 0xff800000 0x0 0x100000>;
526			#address-cells = <2>;
527			#size-cells = <2>;
528			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
529
530			pinctrl_aobus: pinctrl@14 {
531				compatible = "amlogic,meson-axg-aobus-pinctrl";
532				#address-cells = <2>;
533				#size-cells = <2>;
534				ranges;
535
536				gpio_ao: bank@14 {
537					reg = <0x0 0x00014 0x0 0x8>,
538						<0x0 0x0002c 0x0 0x4>,
539						<0x0 0x00024 0x0 0x8>;
540					reg-names = "mux", "pull", "gpio";
541					gpio-controller;
542					#gpio-cells = <2>;
543					gpio-ranges = <&pinctrl_aobus 0 0 15>;
544				};
545
546				remote_input_ao_pins: remote_input_ao {
547					mux {
548						groups = "remote_input_ao";
549						function = "remote_input_ao";
550					};
551				};
552			};
553
554			pwm_AO_ab: pwm@7000 {
555				compatible = "amlogic,meson-axg-ao-pwm";
556				reg = <0x0 0x07000 0x0 0x20>;
557				#pwm-cells = <3>;
558				status = "disabled";
559			};
560
561			pwm_AO_cd: pwm@2000 {
562				compatible = "amlogic,axg-ao-pwm";
563				reg = <0x0 0x02000  0x0 0x20>;
564				#pwm-cells = <3>;
565				status = "disabled";
566			};
567
568			i2c_AO: i2c@5000 {
569				compatible = "amlogic,meson-axg-i2c";
570				status = "disabled";
571				reg = <0x0 0x05000 0x0 0x20>;
572				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
573				#address-cells = <1>;
574				#size-cells = <0>;
575				clocks = <&clkc CLKID_I2C>;
576				clock-names = "clk_i2c";
577			};
578
579			uart_AO: serial@3000 {
580				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
581				reg = <0x0 0x3000 0x0 0x18>;
582				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
583				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
584				clock-names = "xtal", "pclk", "baud";
585				status = "disabled";
586			};
587
588			uart_AO_B: serial@4000 {
589				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
590				reg = <0x0 0x4000 0x0 0x18>;
591				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
592				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
593				clock-names = "xtal", "pclk", "baud";
594				status = "disabled";
595			};
596
597			ir: ir@8000 {
598				compatible = "amlogic,meson-gxbb-ir";
599				reg = <0x0 0x8000 0x0 0x20>;
600				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
601				status = "disabled";
602			};
603		};
604	};
605};
606