1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10
11/ {
12	compatible = "amlogic,meson-axg";
13
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	reserved-memory {
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22
23		/* 16 MiB reserved for Hardware ROM Firmware */
24		hwrom_reserved: hwrom@0 {
25			reg = <0x0 0x0 0x0 0x1000000>;
26			no-map;
27		};
28
29		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
30		secmon_reserved: secmon@5000000 {
31			reg = <0x0 0x05000000 0x0 0x300000>;
32			no-map;
33		};
34	};
35
36	cpus {
37		#address-cells = <0x2>;
38		#size-cells = <0x0>;
39
40		cpu0: cpu@0 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53", "arm,armv8";
43			reg = <0x0 0x0>;
44			enable-method = "psci";
45			next-level-cache = <&l2>;
46		};
47
48		cpu1: cpu@1 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53", "arm,armv8";
51			reg = <0x0 0x1>;
52			enable-method = "psci";
53			next-level-cache = <&l2>;
54		};
55
56		cpu2: cpu@2 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a53", "arm,armv8";
59			reg = <0x0 0x2>;
60			enable-method = "psci";
61			next-level-cache = <&l2>;
62		};
63
64		cpu3: cpu@3 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53", "arm,armv8";
67			reg = <0x0 0x3>;
68			enable-method = "psci";
69			next-level-cache = <&l2>;
70		};
71
72		l2: l2-cache0 {
73			compatible = "cache";
74		};
75	};
76
77	arm-pmu {
78		compatible = "arm,cortex-a53-pmu";
79		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
80			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
84	};
85
86	psci {
87		compatible = "arm,psci-1.0";
88		method = "smc";
89	};
90
91	timer {
92		compatible = "arm,armv8-timer";
93		interrupts = <GIC_PPI 13
94			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
95			     <GIC_PPI 14
96			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 11
98			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
99			     <GIC_PPI 10
100			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
101	};
102
103	xtal: xtal-clk {
104		compatible = "fixed-clock";
105		clock-frequency = <24000000>;
106		clock-output-names = "xtal";
107		#clock-cells = <0>;
108	};
109
110	soc {
111		compatible = "simple-bus";
112		#address-cells = <2>;
113		#size-cells = <2>;
114		ranges;
115
116		cbus: bus@ffd00000 {
117			compatible = "simple-bus";
118			reg = <0x0 0xffd00000 0x0 0x25000>;
119			#address-cells = <2>;
120			#size-cells = <2>;
121			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
122
123			pwm_ab: pwm@1b000 {
124				compatible = "amlogic,meson-axg-ee-pwm";
125				reg = <0x0 0x1b000 0x0 0x20>;
126				#pwm-cells = <3>;
127				status = "disabled";
128			};
129
130			pwm_cd: pwm@1a000 {
131				compatible = "amlogic,meson-axg-ee-pwm";
132				reg = <0x0 0x1a000 0x0 0x20>;
133				#pwm-cells = <3>;
134				status = "disabled";
135			};
136
137			reset: reset-controller@1004 {
138				compatible = "amlogic,meson-axg-reset";
139				reg = <0x0 0x01004 0x0 0x9c>;
140				#reset-cells = <1>;
141			};
142
143			spicc0: spi@13000 {
144				compatible = "amlogic,meson-axg-spicc";
145				reg = <0x0 0x13000 0x0 0x3c>;
146				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
147				clocks = <&clkc CLKID_SPICC0>;
148				clock-names = "core";
149				#address-cells = <1>;
150				#size-cells = <0>;
151				status = "disabled";
152			};
153
154			spicc1: spi@15000 {
155				compatible = "amlogic,meson-axg-spicc";
156				reg = <0x0 0x15000 0x0 0x3c>;
157				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
158				clocks = <&clkc CLKID_SPICC1>;
159				clock-names = "core";
160				#address-cells = <1>;
161				#size-cells = <0>;
162				status = "disabled";
163			};
164
165			i2c0: i2c@1f000 {
166				compatible = "amlogic,meson-axg-i2c";
167				status = "disabled";
168				reg = <0x0 0x1f000 0x0 0x20>;
169				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
170					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
171				#address-cells = <1>;
172				#size-cells = <0>;
173				clocks = <&clkc CLKID_I2C>;
174				clock-names = "clk_i2c";
175			};
176
177			i2c1: i2c@1e000 {
178				compatible = "amlogic,meson-axg-i2c";
179				#address-cells = <1>;
180				#size-cells = <0>;
181				reg = <0x0 0x1e000 0x0 0x20>;
182				status = "disabled";
183				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
184					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
185				clocks = <&clkc CLKID_I2C>;
186				clock-names = "clk_i2c";
187			};
188
189			i2c2: i2c@1d000 {
190				compatible = "amlogic,meson-axg-i2c";
191				status = "disabled";
192				reg = <0x0 0x1d000 0x0 0x20>;
193				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
194					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
195				#address-cells = <1>;
196				#size-cells = <0>;
197				clocks = <&clkc CLKID_I2C>;
198				clock-names = "clk_i2c";
199			};
200
201			i2c3: i2c@1c000 {
202				compatible = "amlogic,meson-axg-i2c";
203				status = "disabled";
204				reg = <0x0 0x1c000 0x0 0x20>;
205				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
206					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
207				#address-cells = <1>;
208				#size-cells = <0>;
209				clocks = <&clkc CLKID_I2C>;
210				clock-names = "clk_i2c";
211			};
212
213			uart_A: serial@24000 {
214				compatible = "amlogic,meson-gx-uart";
215				reg = <0x0 0x24000 0x0 0x18>;
216				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
217				status = "disabled";
218				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
219				clock-names = "xtal", "pclk", "baud";
220			};
221
222			uart_B: serial@23000 {
223				compatible = "amlogic,meson-gx-uart";
224				reg = <0x0 0x23000 0x0 0x18>;
225				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
226				status = "disabled";
227				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
228				clock-names = "xtal", "pclk", "baud";
229			};
230		};
231
232		ethmac: ethernet@ff3f0000 {
233			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
234			reg = <0x0 0xff3f0000 0x0 0x10000
235				0x0 0xff634540 0x0 0x8>;
236			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
237			interrupt-names = "macirq";
238			clocks = <&clkc CLKID_ETH>,
239				 <&clkc CLKID_FCLK_DIV2>,
240				 <&clkc CLKID_MPLL2>;
241			clock-names = "stmmaceth", "clkin0", "clkin1";
242			status = "disabled";
243		};
244
245		gic: interrupt-controller@ffc01000 {
246			compatible = "arm,gic-400";
247			reg = <0x0 0xffc01000 0 0x1000>,
248			      <0x0 0xffc02000 0 0x2000>,
249			      <0x0 0xffc04000 0 0x2000>,
250			      <0x0 0xffc06000 0 0x2000>;
251			interrupt-controller;
252			interrupts = <GIC_PPI 9
253				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
254			#interrupt-cells = <3>;
255			#address-cells = <0>;
256		};
257
258		hiubus: bus@ff63c000 {
259			compatible = "simple-bus";
260			reg = <0x0 0xff63c000 0x0 0x1c00>;
261			#address-cells = <2>;
262			#size-cells = <2>;
263			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
264
265			sysctrl: system-controller@0 {
266				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
267				reg = <0 0 0 0x400>;
268
269				clkc: clock-controller {
270					compatible = "amlogic,axg-clkc";
271					#clock-cells = <1>;
272				};
273			};
274		};
275
276		mailbox: mailbox@ff63dc00 {
277			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
278			reg = <0 0xff63dc00 0 0x400>;
279			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
280				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
281				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
282			#mbox-cells = <1>;
283		};
284
285		periphs: periphs@ff634000 {
286			compatible = "simple-bus";
287			reg = <0x0 0xff634000 0x0 0x2000>;
288			#address-cells = <2>;
289			#size-cells = <2>;
290			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
291
292			hwrng: rng {
293				compatible = "amlogic,meson-rng";
294				reg = <0x0 0x18 0x0 0x4>;
295				clocks = <&clkc CLKID_RNG0>;
296				clock-names = "core";
297			};
298
299			pinctrl_periphs: pinctrl@480 {
300				compatible = "amlogic,meson-axg-periphs-pinctrl";
301				#address-cells = <2>;
302				#size-cells = <2>;
303				ranges;
304
305				gpio: bank@480 {
306					reg = <0x0 0x00480 0x0 0x40>,
307						<0x0 0x004e8 0x0 0x14>,
308						<0x0 0x00520 0x0 0x14>,
309						<0x0 0x00430 0x0 0x3c>;
310					reg-names = "mux", "pull", "pull-enable", "gpio";
311					gpio-controller;
312					#gpio-cells = <2>;
313					gpio-ranges = <&pinctrl_periphs 0 0 86>;
314				};
315
316				eth_rmii_x_pins: eth-x-rmii {
317					mux {
318						groups = "eth_mdio_x",
319						       "eth_mdc_x",
320						       "eth_rgmii_rx_clk_x",
321						       "eth_rx_dv_x",
322						       "eth_rxd0_x",
323						       "eth_rxd1_x",
324						       "eth_txen_x",
325						       "eth_txd0_x",
326						       "eth_txd1_x";
327						function = "eth";
328					};
329				};
330
331				eth_rmii_y_pins: eth-y-rmii {
332					mux {
333						groups = "eth_mdio_y",
334						       "eth_mdc_y",
335						       "eth_rgmii_rx_clk_y",
336						       "eth_rx_dv_y",
337						       "eth_rxd0_y",
338						       "eth_rxd1_y",
339						       "eth_txen_y",
340						       "eth_txd0_y",
341						       "eth_txd1_y";
342						function = "eth";
343					};
344				};
345
346				eth_rgmii_x_pins: eth-x-rgmii {
347					mux {
348						groups = "eth_mdio_x",
349						       "eth_mdc_x",
350						       "eth_rgmii_rx_clk_x",
351						       "eth_rx_dv_x",
352						       "eth_rxd0_x",
353						       "eth_rxd1_x",
354						       "eth_rxd2_rgmii",
355						       "eth_rxd3_rgmii",
356						       "eth_rgmii_tx_clk",
357						       "eth_txen_x",
358						       "eth_txd0_x",
359						       "eth_txd1_x",
360						       "eth_txd2_rgmii",
361						       "eth_txd3_rgmii";
362						function = "eth";
363					};
364				};
365
366				eth_rgmii_y_pins: eth-y-rgmii {
367					mux {
368						groups = "eth_mdio_y",
369						       "eth_mdc_y",
370						       "eth_rgmii_rx_clk_y",
371						       "eth_rx_dv_y",
372						       "eth_rxd0_y",
373						       "eth_rxd1_y",
374						       "eth_rxd2_rgmii",
375						       "eth_rxd3_rgmii",
376						       "eth_rgmii_tx_clk",
377						       "eth_txen_y",
378						       "eth_txd0_y",
379						       "eth_txd1_y",
380						       "eth_txd2_rgmii",
381						       "eth_txd3_rgmii";
382						function = "eth";
383					};
384				};
385
386				pwm_a_a_pins: pwm_a_a {
387					mux {
388						groups = "pwm_a_a";
389						function = "pwm_a";
390					};
391				};
392
393				pwm_a_x18_pins: pwm_a_x18 {
394					mux {
395						groups = "pwm_a_x18";
396						function = "pwm_a";
397					};
398				};
399
400				pwm_a_x20_pins: pwm_a_x20 {
401					mux {
402						groups = "pwm_a_x20";
403						function = "pwm_a";
404					};
405				};
406
407				pwm_a_z_pins: pwm_a_z {
408					mux {
409						groups = "pwm_a_z";
410						function = "pwm_a";
411					};
412				};
413
414				pwm_b_a_pins: pwm_b_a {
415					mux {
416						groups = "pwm_b_a";
417						function = "pwm_b";
418					};
419				};
420
421				pwm_b_x_pins: pwm_b_x {
422					mux {
423						groups = "pwm_b_x";
424						function = "pwm_b";
425					};
426				};
427
428				pwm_b_z_pins: pwm_b_z {
429					mux {
430						groups = "pwm_b_z";
431						function = "pwm_b";
432					};
433				};
434
435				pwm_c_a_pins: pwm_c_a {
436					mux {
437						groups = "pwm_c_a";
438						function = "pwm_c";
439					};
440				};
441
442				pwm_c_x10_pins: pwm_c_x10 {
443					mux {
444						groups = "pwm_c_x10";
445						function = "pwm_c";
446					};
447				};
448
449				pwm_c_x17_pins: pwm_c_x17 {
450					mux {
451						groups = "pwm_c_x17";
452						function = "pwm_c";
453					};
454				};
455
456				pwm_d_x11_pins: pwm_d_x11 {
457					mux {
458						groups = "pwm_d_x11";
459						function = "pwm_d";
460					};
461				};
462
463				pwm_d_x16_pins: pwm_d_x16 {
464					mux {
465						groups = "pwm_d_x16";
466						function = "pwm_d";
467					};
468				};
469
470				spi0_pins: spi0 {
471					mux {
472						groups = "spi0_miso",
473							"spi0_mosi",
474							"spi0_clk";
475						function = "spi0";
476					};
477				};
478
479				spi0_ss0_pins: spi0_ss0 {
480					mux {
481						groups = "spi0_ss0";
482						function = "spi0";
483					};
484				};
485
486				spi0_ss1_pins: spi0_ss1 {
487					mux {
488						groups = "spi0_ss1";
489						function = "spi0";
490					};
491				};
492
493				spi0_ss2_pins: spi0_ss2 {
494					mux {
495						groups = "spi0_ss2";
496						function = "spi0";
497					};
498				};
499
500
501				spi1_a_pins: spi1_a {
502					mux {
503						groups = "spi1_miso_a",
504							"spi1_mosi_a",
505							"spi1_clk_a";
506						function = "spi1";
507					};
508				};
509
510				spi1_ss0_a_pins: spi1_ss0_a {
511					mux {
512						groups = "spi1_ss0_a";
513						function = "spi1";
514					};
515				};
516
517				spi1_ss1_pins: spi1_ss1 {
518					mux {
519						groups = "spi1_ss1";
520						function = "spi1";
521					};
522				};
523
524				spi1_x_pins: spi1_x {
525					mux {
526						groups = "spi1_miso_x",
527							"spi1_mosi_x",
528							"spi1_clk_x";
529						function = "spi1";
530					};
531				};
532
533				spi1_ss0_x_pins: spi1_ss0_x {
534					mux {
535						groups = "spi1_ss0_x";
536						function = "spi1";
537					};
538				};
539
540				i2c0_pins: i2c0 {
541					mux {
542						groups = "i2c0_sck",
543							"i2c0_sda";
544						function = "i2c0";
545					};
546				};
547
548				i2c1_z_pins: i2c1_z {
549					mux {
550						groups = "i2c1_sck_z",
551							"i2c1_sda_z";
552						function = "i2c1";
553					};
554				};
555
556				i2c1_x_pins: i2c1_x {
557					mux {
558						groups = "i2c1_sck_x",
559							"i2c1_sda_x";
560						function = "i2c1";
561					};
562				};
563
564				i2c2_x_pins: i2c2_x {
565					mux {
566						groups = "i2c2_sck_x",
567							"i2c2_sda_x";
568						function = "i2c2";
569					};
570				};
571
572				i2c2_a_pins: i2c2_a {
573					mux {
574						groups = "i2c2_sck_a",
575							"i2c2_sda_a";
576						function = "i2c2";
577					};
578				};
579
580				i2c3_a6_pins: i2c3_a6 {
581					mux {
582						groups = "i2c3_sda_a6",
583							"i2c3_sck_a7";
584						function = "i2c3";
585					};
586				};
587
588				i2c3_a12_pins: i2c3_a12 {
589					mux {
590						groups = "i2c3_sda_a12",
591							"i2c3_sck_a13";
592						function = "i2c3";
593					};
594				};
595
596				i2c3_a19_pins: i2c3_a19 {
597					mux {
598						groups = "i2c3_sda_a19",
599							"i2c3_sck_a20";
600						function = "i2c3";
601					};
602				};
603
604				uart_a_pins: uart_a {
605					mux {
606						groups = "uart_tx_a",
607							"uart_rx_a";
608						function = "uart_a";
609					};
610				};
611
612				uart_a_cts_rts_pins: uart_a_cts_rts {
613					mux {
614						groups = "uart_cts_a",
615							"uart_rts_a";
616						function = "uart_a";
617					};
618				};
619
620				uart_b_x_pins: uart_b_x {
621					mux {
622						groups = "uart_tx_b_x",
623							"uart_rx_b_x";
624						function = "uart_b";
625					};
626				};
627
628				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
629					mux {
630						groups = "uart_cts_b_x",
631							"uart_rts_b_x";
632						function = "uart_b";
633					};
634				};
635
636				uart_b_z_pins: uart_b_z {
637					mux {
638						groups = "uart_tx_b_z",
639							"uart_rx_b_z";
640						function = "uart_b";
641					};
642				};
643
644				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
645					mux {
646						groups = "uart_cts_b_z",
647							"uart_rts_b_z";
648						function = "uart_b";
649					};
650				};
651
652				uart_ao_b_z_pins: uart_ao_b_z {
653					mux {
654						groups = "uart_ao_tx_b_z",
655							"uart_ao_rx_b_z";
656						function = "uart_ao_b_z";
657					};
658				};
659
660				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
661					mux {
662						groups = "uart_ao_cts_b_z",
663							"uart_ao_rts_b_z";
664						function = "uart_ao_b_z";
665					};
666				};
667			};
668		};
669
670		sram: sram@fffc0000 {
671			compatible = "amlogic,meson-axg-sram", "mmio-sram";
672			reg = <0x0 0xfffc0000 0x0 0x20000>;
673			#address-cells = <1>;
674			#size-cells = <1>;
675			ranges = <0 0x0 0xfffc0000 0x20000>;
676
677			cpu_scp_lpri: scp-shmem@0 {
678				compatible = "amlogic,meson-axg-scp-shmem";
679				reg = <0x13000 0x400>;
680			};
681
682			cpu_scp_hpri: scp-shmem@200 {
683				compatible = "amlogic,meson-axg-scp-shmem";
684				reg = <0x13400 0x400>;
685			};
686		};
687
688		aobus: bus@ff800000 {
689			compatible = "simple-bus";
690			reg = <0x0 0xff800000 0x0 0x100000>;
691			#address-cells = <2>;
692			#size-cells = <2>;
693			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
694
695			pinctrl_aobus: pinctrl@14 {
696				compatible = "amlogic,meson-axg-aobus-pinctrl";
697				#address-cells = <2>;
698				#size-cells = <2>;
699				ranges;
700
701				gpio_ao: bank@14 {
702					reg = <0x0 0x00014 0x0 0x8>,
703						<0x0 0x0002c 0x0 0x4>,
704						<0x0 0x00024 0x0 0x8>;
705					reg-names = "mux", "pull", "gpio";
706					gpio-controller;
707					#gpio-cells = <2>;
708					gpio-ranges = <&pinctrl_aobus 0 0 15>;
709				};
710
711				remote_input_ao_pins: remote_input_ao {
712					mux {
713						groups = "remote_input_ao";
714						function = "remote_input_ao";
715					};
716				};
717
718				uart_ao_a_pins: uart_ao_a {
719					mux {
720						groups = "uart_ao_tx_a",
721							"uart_ao_rx_a";
722						function = "uart_ao_a";
723					};
724				};
725
726				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
727					mux {
728						groups = "uart_ao_cts_a",
729							"uart_ao_rts_a";
730						function = "uart_ao_a";
731					};
732				};
733
734				uart_ao_b_pins: uart_ao_b {
735					mux {
736						groups = "uart_ao_tx_b",
737							"uart_ao_rx_b";
738						function = "uart_ao_b";
739					};
740				};
741
742				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
743					mux {
744						groups = "uart_ao_cts_b",
745							"uart_ao_rts_b";
746						function = "uart_ao_b";
747					};
748				};
749			};
750
751			sec_AO: ao-secure@140 {
752				compatible = "amlogic,meson-gx-ao-secure", "syscon";
753				reg = <0x0 0x140 0x0 0x140>;
754				amlogic,has-chip-id;
755			};
756
757			pwm_AO_ab: pwm@7000 {
758				compatible = "amlogic,meson-axg-ao-pwm";
759				reg = <0x0 0x07000 0x0 0x20>;
760				#pwm-cells = <3>;
761				status = "disabled";
762			};
763
764			pwm_AO_cd: pwm@2000 {
765				compatible = "amlogic,meson-axg-ao-pwm";
766				reg = <0x0 0x02000  0x0 0x20>;
767				#pwm-cells = <3>;
768				status = "disabled";
769			};
770
771			i2c_AO: i2c@5000 {
772				compatible = "amlogic,meson-axg-i2c";
773				status = "disabled";
774				reg = <0x0 0x05000 0x0 0x20>;
775				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
776				#address-cells = <1>;
777				#size-cells = <0>;
778				clocks = <&clkc CLKID_I2C>;
779				clock-names = "clk_i2c";
780			};
781
782			uart_AO: serial@3000 {
783				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
784				reg = <0x0 0x3000 0x0 0x18>;
785				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
786				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
787				clock-names = "xtal", "pclk", "baud";
788				status = "disabled";
789			};
790
791			uart_AO_B: serial@4000 {
792				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
793				reg = <0x0 0x4000 0x0 0x18>;
794				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
795				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
796				clock-names = "xtal", "pclk", "baud";
797				status = "disabled";
798			};
799
800			ir: ir@8000 {
801				compatible = "amlogic,meson-gxbb-ir";
802				reg = <0x0 0x8000 0x0 0x20>;
803				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
804				status = "disabled";
805			};
806		};
807	};
808};
809