1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10#include <dt-bindings/clock/axg-aoclkc.h>
11#include <dt-bindings/gpio/meson-axg-gpio.h>
12#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
13
14/ {
15	compatible = "amlogic,meson-axg";
16
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	reserved-memory {
22		#address-cells = <2>;
23		#size-cells = <2>;
24		ranges;
25
26		/* 16 MiB reserved for Hardware ROM Firmware */
27		hwrom_reserved: hwrom@0 {
28			reg = <0x0 0x0 0x0 0x1000000>;
29			no-map;
30		};
31
32		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
33		secmon_reserved: secmon@5000000 {
34			reg = <0x0 0x05000000 0x0 0x300000>;
35			no-map;
36		};
37	};
38
39	cpus {
40		#address-cells = <0x2>;
41		#size-cells = <0x0>;
42
43		cpu0: cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53", "arm,armv8";
46			reg = <0x0 0x0>;
47			enable-method = "psci";
48			next-level-cache = <&l2>;
49		};
50
51		cpu1: cpu@1 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53", "arm,armv8";
54			reg = <0x0 0x1>;
55			enable-method = "psci";
56			next-level-cache = <&l2>;
57		};
58
59		cpu2: cpu@2 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53", "arm,armv8";
62			reg = <0x0 0x2>;
63			enable-method = "psci";
64			next-level-cache = <&l2>;
65		};
66
67		cpu3: cpu@3 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53", "arm,armv8";
70			reg = <0x0 0x3>;
71			enable-method = "psci";
72			next-level-cache = <&l2>;
73		};
74
75		l2: l2-cache0 {
76			compatible = "cache";
77		};
78	};
79
80	arm-pmu {
81		compatible = "arm,cortex-a53-pmu";
82		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
87	};
88
89	psci {
90		compatible = "arm,psci-1.0";
91		method = "smc";
92	};
93
94	timer {
95		compatible = "arm,armv8-timer";
96		interrupts = <GIC_PPI 13
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 14
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 11
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
102			     <GIC_PPI 10
103			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
104	};
105
106	xtal: xtal-clk {
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "xtal";
110		#clock-cells = <0>;
111	};
112
113	ao_alt_xtal: ao_alt_xtal-clk {
114		compatible = "fixed-clock";
115		clock-frequency = <32000000>;
116		clock-output-names = "ao_alt_xtal";
117		#clock-cells = <0>;
118	};
119
120	soc {
121		compatible = "simple-bus";
122		#address-cells = <2>;
123		#size-cells = <2>;
124		ranges;
125
126		apb: apb@ffe00000 {
127			compatible = "simple-bus";
128			reg = <0x0 0xffe00000 0x0 0x200000>;
129			#address-cells = <2>;
130			#size-cells = <2>;
131			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
132
133			sd_emmc_b: sd@5000 {
134				compatible = "amlogic,meson-axg-mmc";
135				reg = <0x0 0x5000 0x0 0x2000>;
136				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
137				status = "disabled";
138				clocks = <&clkc CLKID_SD_EMMC_B>,
139					<&clkc CLKID_SD_EMMC_B_CLK0>,
140					<&clkc CLKID_FCLK_DIV2>;
141				clock-names = "core", "clkin0", "clkin1";
142				resets = <&reset RESET_SD_EMMC_B>;
143			};
144
145			sd_emmc_c: mmc@7000 {
146				compatible = "amlogic,meson-axg-mmc";
147				reg = <0x0 0x7000 0x0 0x2000>;
148				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
149				status = "disabled";
150				clocks = <&clkc CLKID_SD_EMMC_C>,
151					<&clkc CLKID_SD_EMMC_C_CLK0>,
152					<&clkc CLKID_FCLK_DIV2>;
153				clock-names = "core", "clkin0", "clkin1";
154				resets = <&reset RESET_SD_EMMC_C>;
155			};
156		};
157
158		cbus: bus@ffd00000 {
159			compatible = "simple-bus";
160			reg = <0x0 0xffd00000 0x0 0x25000>;
161			#address-cells = <2>;
162			#size-cells = <2>;
163			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
164
165			gpio_intc: interrupt-controller@f080 {
166				compatible = "amlogic,meson-gpio-intc";
167				reg = <0x0 0xf080 0x0 0x10>;
168				interrupt-controller;
169				#interrupt-cells = <2>;
170				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
171				status = "disabled";
172			};
173
174			pwm_ab: pwm@1b000 {
175				compatible = "amlogic,meson-axg-ee-pwm";
176				reg = <0x0 0x1b000 0x0 0x20>;
177				#pwm-cells = <3>;
178				status = "disabled";
179			};
180
181			pwm_cd: pwm@1a000 {
182				compatible = "amlogic,meson-axg-ee-pwm";
183				reg = <0x0 0x1a000 0x0 0x20>;
184				#pwm-cells = <3>;
185				status = "disabled";
186			};
187
188			reset: reset-controller@1004 {
189				compatible = "amlogic,meson-axg-reset";
190				reg = <0x0 0x01004 0x0 0x9c>;
191				#reset-cells = <1>;
192			};
193
194			spicc0: spi@13000 {
195				compatible = "amlogic,meson-axg-spicc";
196				reg = <0x0 0x13000 0x0 0x3c>;
197				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
198				clocks = <&clkc CLKID_SPICC0>;
199				clock-names = "core";
200				#address-cells = <1>;
201				#size-cells = <0>;
202				status = "disabled";
203			};
204
205			spicc1: spi@15000 {
206				compatible = "amlogic,meson-axg-spicc";
207				reg = <0x0 0x15000 0x0 0x3c>;
208				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
209				clocks = <&clkc CLKID_SPICC1>;
210				clock-names = "core";
211				#address-cells = <1>;
212				#size-cells = <0>;
213				status = "disabled";
214			};
215
216			i2c0: i2c@1f000 {
217				compatible = "amlogic,meson-axg-i2c";
218				reg = <0x0 0x1f000 0x0 0x20>;
219				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
220				clocks = <&clkc CLKID_I2C>;
221				#address-cells = <1>;
222				#size-cells = <0>;
223				status = "disabled";
224			};
225
226			i2c1: i2c@1e000 {
227				compatible = "amlogic,meson-axg-i2c";
228				reg = <0x0 0x1e000 0x0 0x20>;
229				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
230				clocks = <&clkc CLKID_I2C>;
231				#address-cells = <1>;
232				#size-cells = <0>;
233				status = "disabled";
234			};
235
236			i2c2: i2c@1d000 {
237				compatible = "amlogic,meson-axg-i2c";
238				reg = <0x0 0x1d000 0x0 0x20>;
239				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
240				clocks = <&clkc CLKID_I2C>;
241				#address-cells = <1>;
242				#size-cells = <0>;
243				status = "disabled";
244			};
245
246			i2c3: i2c@1c000 {
247				compatible = "amlogic,meson-axg-i2c";
248				reg = <0x0 0x1c000 0x0 0x20>;
249				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
250				clocks = <&clkc CLKID_I2C>;
251				#address-cells = <1>;
252				#size-cells = <0>;
253				status = "disabled";
254			};
255
256			uart_A: serial@24000 {
257				compatible = "amlogic,meson-gx-uart";
258				reg = <0x0 0x24000 0x0 0x18>;
259				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
260				status = "disabled";
261				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
262				clock-names = "xtal", "pclk", "baud";
263			};
264
265			uart_B: serial@23000 {
266				compatible = "amlogic,meson-gx-uart";
267				reg = <0x0 0x23000 0x0 0x18>;
268				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
269				status = "disabled";
270				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
271				clock-names = "xtal", "pclk", "baud";
272			};
273		};
274
275		ethmac: ethernet@ff3f0000 {
276			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
277			reg = <0x0 0xff3f0000 0x0 0x10000
278				0x0 0xff634540 0x0 0x8>;
279			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
280			interrupt-names = "macirq";
281			clocks = <&clkc CLKID_ETH>,
282				 <&clkc CLKID_FCLK_DIV2>,
283				 <&clkc CLKID_MPLL2>;
284			clock-names = "stmmaceth", "clkin0", "clkin1";
285			status = "disabled";
286		};
287
288		gic: interrupt-controller@ffc01000 {
289			compatible = "arm,gic-400";
290			reg = <0x0 0xffc01000 0 0x1000>,
291			      <0x0 0xffc02000 0 0x2000>,
292			      <0x0 0xffc04000 0 0x2000>,
293			      <0x0 0xffc06000 0 0x2000>;
294			interrupt-controller;
295			interrupts = <GIC_PPI 9
296				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
297			#interrupt-cells = <3>;
298			#address-cells = <0>;
299		};
300
301		hiubus: bus@ff63c000 {
302			compatible = "simple-bus";
303			reg = <0x0 0xff63c000 0x0 0x1c00>;
304			#address-cells = <2>;
305			#size-cells = <2>;
306			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
307
308			sysctrl: system-controller@0 {
309				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
310				reg = <0 0 0 0x400>;
311
312				clkc: clock-controller {
313					compatible = "amlogic,axg-clkc";
314					#clock-cells = <1>;
315				};
316			};
317		};
318
319		mailbox: mailbox@ff63dc00 {
320			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
321			reg = <0 0xff63dc00 0 0x400>;
322			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
323				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
324				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
325			#mbox-cells = <1>;
326		};
327
328		periphs: periphs@ff634000 {
329			compatible = "simple-bus";
330			reg = <0x0 0xff634000 0x0 0x2000>;
331			#address-cells = <2>;
332			#size-cells = <2>;
333			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
334
335			hwrng: rng {
336				compatible = "amlogic,meson-rng";
337				reg = <0x0 0x18 0x0 0x4>;
338				clocks = <&clkc CLKID_RNG0>;
339				clock-names = "core";
340			};
341
342			pinctrl_periphs: pinctrl@480 {
343				compatible = "amlogic,meson-axg-periphs-pinctrl";
344				#address-cells = <2>;
345				#size-cells = <2>;
346				ranges;
347
348				gpio: bank@480 {
349					reg = <0x0 0x00480 0x0 0x40>,
350						<0x0 0x004e8 0x0 0x14>,
351						<0x0 0x00520 0x0 0x14>,
352						<0x0 0x00430 0x0 0x3c>;
353					reg-names = "mux", "pull", "pull-enable", "gpio";
354					gpio-controller;
355					#gpio-cells = <2>;
356					gpio-ranges = <&pinctrl_periphs 0 0 86>;
357				};
358
359				emmc_pins: emmc {
360					mux {
361						groups = "emmc_nand_d0",
362							"emmc_nand_d1",
363							"emmc_nand_d2",
364							"emmc_nand_d3",
365							"emmc_nand_d4",
366							"emmc_nand_d5",
367							"emmc_nand_d6",
368							"emmc_nand_d7",
369							"emmc_clk",
370							"emmc_cmd",
371							"emmc_ds";
372						function = "emmc";
373					};
374				};
375
376				emmc_clk_gate_pins: emmc_clk_gate {
377					mux {
378						groups = "BOOT_8";
379						function = "gpio_periphs";
380					};
381					cfg-pull-down {
382						pins = "BOOT_8";
383						bias-pull-down;
384					};
385				};
386
387				sdio_pins: sdio {
388					mux {
389						groups = "sdio_d0",
390							"sdio_d1",
391							"sdio_d2",
392							"sdio_d3",
393							"sdio_cmd",
394							"sdio_clk";
395						function = "sdio";
396					};
397				};
398
399				sdio_clk_gate_pins: sdio_clk_gate {
400					mux {
401						groups = "GPIOX_4";
402						function = "gpio_periphs";
403					};
404					cfg-pull-down {
405						pins = "GPIOX_4";
406						bias-pull-down;
407					};
408				};
409
410				eth_rmii_x_pins: eth-x-rmii {
411					mux {
412						groups = "eth_mdio_x",
413						       "eth_mdc_x",
414						       "eth_rgmii_rx_clk_x",
415						       "eth_rx_dv_x",
416						       "eth_rxd0_x",
417						       "eth_rxd1_x",
418						       "eth_txen_x",
419						       "eth_txd0_x",
420						       "eth_txd1_x";
421						function = "eth";
422					};
423				};
424
425				eth_rmii_y_pins: eth-y-rmii {
426					mux {
427						groups = "eth_mdio_y",
428						       "eth_mdc_y",
429						       "eth_rgmii_rx_clk_y",
430						       "eth_rx_dv_y",
431						       "eth_rxd0_y",
432						       "eth_rxd1_y",
433						       "eth_txen_y",
434						       "eth_txd0_y",
435						       "eth_txd1_y";
436						function = "eth";
437					};
438				};
439
440				eth_rgmii_x_pins: eth-x-rgmii {
441					mux {
442						groups = "eth_mdio_x",
443						       "eth_mdc_x",
444						       "eth_rgmii_rx_clk_x",
445						       "eth_rx_dv_x",
446						       "eth_rxd0_x",
447						       "eth_rxd1_x",
448						       "eth_rxd2_rgmii",
449						       "eth_rxd3_rgmii",
450						       "eth_rgmii_tx_clk",
451						       "eth_txen_x",
452						       "eth_txd0_x",
453						       "eth_txd1_x",
454						       "eth_txd2_rgmii",
455						       "eth_txd3_rgmii";
456						function = "eth";
457					};
458				};
459
460				eth_rgmii_y_pins: eth-y-rgmii {
461					mux {
462						groups = "eth_mdio_y",
463						       "eth_mdc_y",
464						       "eth_rgmii_rx_clk_y",
465						       "eth_rx_dv_y",
466						       "eth_rxd0_y",
467						       "eth_rxd1_y",
468						       "eth_rxd2_rgmii",
469						       "eth_rxd3_rgmii",
470						       "eth_rgmii_tx_clk",
471						       "eth_txen_y",
472						       "eth_txd0_y",
473						       "eth_txd1_y",
474						       "eth_txd2_rgmii",
475						       "eth_txd3_rgmii";
476						function = "eth";
477					};
478				};
479
480				pwm_a_a_pins: pwm_a_a {
481					mux {
482						groups = "pwm_a_a";
483						function = "pwm_a";
484					};
485				};
486
487				pwm_a_x18_pins: pwm_a_x18 {
488					mux {
489						groups = "pwm_a_x18";
490						function = "pwm_a";
491					};
492				};
493
494				pwm_a_x20_pins: pwm_a_x20 {
495					mux {
496						groups = "pwm_a_x20";
497						function = "pwm_a";
498					};
499				};
500
501				pwm_a_z_pins: pwm_a_z {
502					mux {
503						groups = "pwm_a_z";
504						function = "pwm_a";
505					};
506				};
507
508				pwm_b_a_pins: pwm_b_a {
509					mux {
510						groups = "pwm_b_a";
511						function = "pwm_b";
512					};
513				};
514
515				pwm_b_x_pins: pwm_b_x {
516					mux {
517						groups = "pwm_b_x";
518						function = "pwm_b";
519					};
520				};
521
522				pwm_b_z_pins: pwm_b_z {
523					mux {
524						groups = "pwm_b_z";
525						function = "pwm_b";
526					};
527				};
528
529				pwm_c_a_pins: pwm_c_a {
530					mux {
531						groups = "pwm_c_a";
532						function = "pwm_c";
533					};
534				};
535
536				pwm_c_x10_pins: pwm_c_x10 {
537					mux {
538						groups = "pwm_c_x10";
539						function = "pwm_c";
540					};
541				};
542
543				pwm_c_x17_pins: pwm_c_x17 {
544					mux {
545						groups = "pwm_c_x17";
546						function = "pwm_c";
547					};
548				};
549
550				pwm_d_x11_pins: pwm_d_x11 {
551					mux {
552						groups = "pwm_d_x11";
553						function = "pwm_d";
554					};
555				};
556
557				pwm_d_x16_pins: pwm_d_x16 {
558					mux {
559						groups = "pwm_d_x16";
560						function = "pwm_d";
561					};
562				};
563
564				spdif_in_z_pins: spdif_in_z {
565					mux {
566						groups = "spdif_in_z";
567						function = "spdif_in";
568					};
569				};
570
571				spdif_in_a1_pins: spdif_in_a1 {
572					mux {
573						groups = "spdif_in_a1";
574						function = "spdif_in";
575					};
576				};
577
578				spdif_in_a7_pins: spdif_in_a7 {
579					mux {
580						groups = "spdif_in_a7";
581						function = "spdif_in";
582					};
583				};
584
585				spdif_in_a19_pins: spdif_in_a19 {
586					mux {
587						groups = "spdif_in_a19";
588						function = "spdif_in";
589					};
590				};
591
592				spdif_in_a20_pins: spdif_in_a20 {
593					mux {
594						groups = "spdif_in_a20";
595						function = "spdif_in";
596					};
597				};
598
599				spdif_out_z_pins: spdif_out_z {
600					mux {
601						groups = "spdif_out_z";
602						function = "spdif_out";
603					};
604				};
605
606				spdif_out_a1_pins: spdif_out_a1 {
607					mux {
608						groups = "spdif_out_a1";
609						function = "spdif_out";
610					};
611				};
612
613				spdif_out_a11_pins: spdif_out_a11 {
614					mux {
615						groups = "spdif_out_a11";
616						function = "spdif_out";
617					};
618				};
619
620				spdif_out_a19_pins: spdif_out_a19 {
621					mux {
622						groups = "spdif_out_a19";
623						function = "spdif_out";
624					};
625				};
626
627				spdif_out_a20_pins: spdif_out_a20 {
628					mux {
629						groups = "spdif_out_a20";
630						function = "spdif_out";
631					};
632				};
633
634				spi0_pins: spi0 {
635					mux {
636						groups = "spi0_miso",
637							"spi0_mosi",
638							"spi0_clk";
639						function = "spi0";
640					};
641				};
642
643				spi0_ss0_pins: spi0_ss0 {
644					mux {
645						groups = "spi0_ss0";
646						function = "spi0";
647					};
648				};
649
650				spi0_ss1_pins: spi0_ss1 {
651					mux {
652						groups = "spi0_ss1";
653						function = "spi0";
654					};
655				};
656
657				spi0_ss2_pins: spi0_ss2 {
658					mux {
659						groups = "spi0_ss2";
660						function = "spi0";
661					};
662				};
663
664
665				spi1_a_pins: spi1_a {
666					mux {
667						groups = "spi1_miso_a",
668							"spi1_mosi_a",
669							"spi1_clk_a";
670						function = "spi1";
671					};
672				};
673
674				spi1_ss0_a_pins: spi1_ss0_a {
675					mux {
676						groups = "spi1_ss0_a";
677						function = "spi1";
678					};
679				};
680
681				spi1_ss1_pins: spi1_ss1 {
682					mux {
683						groups = "spi1_ss1";
684						function = "spi1";
685					};
686				};
687
688				spi1_x_pins: spi1_x {
689					mux {
690						groups = "spi1_miso_x",
691							"spi1_mosi_x",
692							"spi1_clk_x";
693						function = "spi1";
694					};
695				};
696
697				spi1_ss0_x_pins: spi1_ss0_x {
698					mux {
699						groups = "spi1_ss0_x";
700						function = "spi1";
701					};
702				};
703
704				i2c0_pins: i2c0 {
705					mux {
706						groups = "i2c0_sck",
707							"i2c0_sda";
708						function = "i2c0";
709					};
710				};
711
712				i2c1_z_pins: i2c1_z {
713					mux {
714						groups = "i2c1_sck_z",
715							"i2c1_sda_z";
716						function = "i2c1";
717					};
718				};
719
720				i2c1_x_pins: i2c1_x {
721					mux {
722						groups = "i2c1_sck_x",
723							"i2c1_sda_x";
724						function = "i2c1";
725					};
726				};
727
728				i2c2_x_pins: i2c2_x {
729					mux {
730						groups = "i2c2_sck_x",
731							"i2c2_sda_x";
732						function = "i2c2";
733					};
734				};
735
736				i2c2_a_pins: i2c2_a {
737					mux {
738						groups = "i2c2_sck_a",
739							"i2c2_sda_a";
740						function = "i2c2";
741					};
742				};
743
744				i2c3_a6_pins: i2c3_a6 {
745					mux {
746						groups = "i2c3_sda_a6",
747							"i2c3_sck_a7";
748						function = "i2c3";
749					};
750				};
751
752				i2c3_a12_pins: i2c3_a12 {
753					mux {
754						groups = "i2c3_sda_a12",
755							"i2c3_sck_a13";
756						function = "i2c3";
757					};
758				};
759
760				i2c3_a19_pins: i2c3_a19 {
761					mux {
762						groups = "i2c3_sda_a19",
763							"i2c3_sck_a20";
764						function = "i2c3";
765					};
766				};
767
768				uart_a_pins: uart_a {
769					mux {
770						groups = "uart_tx_a",
771							"uart_rx_a";
772						function = "uart_a";
773					};
774				};
775
776				uart_a_cts_rts_pins: uart_a_cts_rts {
777					mux {
778						groups = "uart_cts_a",
779							"uart_rts_a";
780						function = "uart_a";
781					};
782				};
783
784				uart_b_x_pins: uart_b_x {
785					mux {
786						groups = "uart_tx_b_x",
787							"uart_rx_b_x";
788						function = "uart_b";
789					};
790				};
791
792				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
793					mux {
794						groups = "uart_cts_b_x",
795							"uart_rts_b_x";
796						function = "uart_b";
797					};
798				};
799
800				uart_b_z_pins: uart_b_z {
801					mux {
802						groups = "uart_tx_b_z",
803							"uart_rx_b_z";
804						function = "uart_b";
805					};
806				};
807
808				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
809					mux {
810						groups = "uart_cts_b_z",
811							"uart_rts_b_z";
812						function = "uart_b";
813					};
814				};
815
816				uart_ao_b_z_pins: uart_ao_b_z {
817					mux {
818						groups = "uart_ao_tx_b_z",
819							"uart_ao_rx_b_z";
820						function = "uart_ao_b_z";
821					};
822				};
823
824				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
825					mux {
826						groups = "uart_ao_cts_b_z",
827							"uart_ao_rts_b_z";
828						function = "uart_ao_b_z";
829					};
830				};
831
832				mclk_b_pins: mclk_b {
833					mux {
834						groups = "mclk_b";
835						function = "mclk_b";
836					};
837				};
838
839				mclk_c_pins: mclk_c {
840					mux {
841						groups = "mclk_c";
842						function = "mclk_c";
843					};
844				};
845
846				tdma_sclk_pins: tdma_sclk {
847					mux {
848						groups = "tdma_sclk";
849						function = "tdma";
850					};
851				};
852
853				tdma_sclk_slv_pins: tdma_sclk_slv {
854					mux {
855						groups = "tdma_sclk_slv";
856						function = "tdma";
857					};
858				};
859
860				tdma_fs_pins: tdma_fs {
861					mux {
862						groups = "tdma_fs";
863						function = "tdma";
864					};
865				};
866
867				tdma_fs_slv_pins: tdma_fs_slv {
868					mux {
869						groups = "tdma_fs_slv";
870						function = "tdma";
871					};
872				};
873
874				tdma_din0_pins: tdma_din0 {
875					mux {
876						groups = "tdma_din0";
877						function = "tdma";
878					};
879				};
880
881				tdma_dout0_x14_pins: tdma_dout0_x14 {
882					mux {
883						groups = "tdma_dout0_x14";
884						function = "tdma";
885					};
886				};
887
888				tdma_dout0_x15_pins: tdma_dout0_x15 {
889					mux {
890						groups = "tdma_dout0_x15";
891						function = "tdma";
892					};
893				};
894
895				tdma_dout1_pins: tdma_dout1 {
896					mux {
897						groups = "tdma_dout1";
898						function = "tdma";
899					};
900				};
901
902				tdma_din1_pins: tdma_din1 {
903					mux {
904						groups = "tdma_din1";
905						function = "tdma";
906					};
907				};
908
909				tdmb_sclk_pins: tdmb_sclk {
910					mux {
911						groups = "tdmb_sclk";
912						function = "tdmb";
913					};
914				};
915
916				tdmb_sclk_slv_pins: tdmb_sclk_slv {
917					mux {
918						groups = "tdmb_sclk_slv";
919						function = "tdmb";
920					};
921				};
922
923				tdmb_fs_pins: tdmb_fs {
924					mux {
925						groups = "tdmb_fs";
926						function = "tdmb";
927					};
928				};
929
930				tdmb_fs_slv_pins: tdmb_fs_slv {
931					mux {
932						groups = "tdmb_fs_slv";
933						function = "tdmb";
934					};
935				};
936
937				tdmb_din0_pins: tdmb_din0 {
938					mux {
939						groups = "tdmb_din0";
940						function = "tdmb";
941					};
942				};
943
944				tdmb_dout0_pins: tdmb_dout0 {
945					mux {
946						groups = "tdmb_dout0";
947						function = "tdmb";
948					};
949				};
950
951				tdmb_din1_pins: tdmb_din1 {
952					mux {
953						groups = "tdmb_din1";
954						function = "tdmb";
955					};
956				};
957
958				tdmb_dout1_pins: tdmb_dout1 {
959					mux {
960						groups = "tdmb_dout1";
961						function = "tdmb";
962					};
963				};
964
965				tdmb_din2_pins: tdmb_din2 {
966					mux {
967						groups = "tdmb_din2";
968						function = "tdmb";
969					};
970				};
971
972				tdmb_dout2_pins: tdmb_dout2 {
973					mux {
974						groups = "tdmb_dout2";
975						function = "tdmb";
976					};
977				};
978
979				tdmb_din3_pins: tdmb_din3 {
980					mux {
981						groups = "tdmb_din3";
982						function = "tdmb";
983					};
984				};
985
986				tdmb_dout3_pins: tdmb_dout3 {
987					mux {
988						groups = "tdmb_dout3";
989						function = "tdmb";
990					};
991				};
992
993				tdmc_sclk_pins: tdmc_sclk {
994					mux {
995						groups = "tdmc_sclk";
996						function = "tdmc";
997					};
998				};
999
1000				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1001					mux {
1002						groups = "tdmc_sclk_slv";
1003						function = "tdmc";
1004					};
1005				};
1006
1007				tdmc_fs_pins: tdmc_fs {
1008					mux {
1009						groups = "tdmc_fs";
1010						function = "tdmc";
1011					};
1012				};
1013
1014				tdmc_fs_slv_pins: tdmc_fs_slv {
1015					mux {
1016						groups = "tdmc_fs_slv";
1017						function = "tdmc";
1018					};
1019				};
1020
1021				tdmc_din0_pins: tdmc_din0 {
1022					mux {
1023						groups = "tdmc_din0";
1024						function = "tdmc";
1025					};
1026				};
1027
1028				tdmc_dout0_pins: tdmc_dout0 {
1029					mux {
1030						groups = "tdmc_dout0";
1031						function = "tdmc";
1032					};
1033				};
1034
1035				tdmc_din1_pins: tdmc_din1 {
1036					mux {
1037						groups = "tdmc_din1";
1038						function = "tdmc";
1039					};
1040				};
1041
1042				tdmc_dout1_pins: tdmc_dout1 {
1043					mux {
1044						groups = "tdmc_dout1";
1045						function = "tdmc";
1046					};
1047				};
1048
1049				tdmc_din2_pins: tdmc_din2 {
1050					mux {
1051						groups = "tdmc_din2";
1052						function = "tdmc";
1053					};
1054				};
1055
1056				tdmc_dout2_pins: tdmc_dout2 {
1057					mux {
1058						groups = "tdmc_dout2";
1059						function = "tdmc";
1060					};
1061				};
1062
1063				tdmc_din3_pins: tdmc_din3 {
1064					mux {
1065						groups = "tdmc_din3";
1066						function = "tdmc";
1067					};
1068				};
1069
1070				tdmc_dout3_pins: tdmc_dout3 {
1071					mux {
1072						groups = "tdmc_dout3";
1073						function = "tdmc";
1074					};
1075				};
1076			};
1077		};
1078
1079		sram: sram@fffc0000 {
1080			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1081			reg = <0x0 0xfffc0000 0x0 0x20000>;
1082			#address-cells = <1>;
1083			#size-cells = <1>;
1084			ranges = <0 0x0 0xfffc0000 0x20000>;
1085
1086			cpu_scp_lpri: scp-shmem@0 {
1087				compatible = "amlogic,meson-axg-scp-shmem";
1088				reg = <0x13000 0x400>;
1089			};
1090
1091			cpu_scp_hpri: scp-shmem@200 {
1092				compatible = "amlogic,meson-axg-scp-shmem";
1093				reg = <0x13400 0x400>;
1094			};
1095		};
1096
1097		aobus: bus@ff800000 {
1098			compatible = "simple-bus";
1099			reg = <0x0 0xff800000 0x0 0x100000>;
1100			#address-cells = <2>;
1101			#size-cells = <2>;
1102			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1103
1104			sysctrl_AO: sys-ctrl@0 {
1105				compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1106				reg =  <0x0 0x0 0x0 0x100>;
1107
1108				clkc_AO: clock-controller {
1109					compatible = "amlogic,meson-axg-aoclkc";
1110					#clock-cells = <1>;
1111					#reset-cells = <1>;
1112				};
1113			};
1114
1115			pinctrl_aobus: pinctrl@14 {
1116				compatible = "amlogic,meson-axg-aobus-pinctrl";
1117				#address-cells = <2>;
1118				#size-cells = <2>;
1119				ranges;
1120
1121				gpio_ao: bank@14 {
1122					reg = <0x0 0x00014 0x0 0x8>,
1123						<0x0 0x0002c 0x0 0x4>,
1124						<0x0 0x00024 0x0 0x8>;
1125					reg-names = "mux", "pull", "gpio";
1126					gpio-controller;
1127					#gpio-cells = <2>;
1128					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1129				};
1130
1131				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1132					mux {
1133						groups = "i2c_ao_sck_4";
1134						function = "i2c_ao";
1135					};
1136				};
1137
1138				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1139					mux {
1140						groups = "i2c_ao_sck_8";
1141						function = "i2c_ao";
1142					};
1143				};
1144
1145				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1146					mux {
1147						groups = "i2c_ao_sck_10";
1148						function = "i2c_ao";
1149					};
1150				};
1151
1152				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1153					mux {
1154						groups = "i2c_ao_sda_5";
1155						function = "i2c_ao";
1156					};
1157				};
1158
1159				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1160					mux {
1161						groups = "i2c_ao_sda_9";
1162						function = "i2c_ao";
1163					};
1164				};
1165
1166				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1167					mux {
1168						groups = "i2c_ao_sda_11";
1169						function = "i2c_ao";
1170					};
1171				};
1172
1173				remote_input_ao_pins: remote_input_ao {
1174					mux {
1175						groups = "remote_input_ao";
1176						function = "remote_input_ao";
1177					};
1178				};
1179
1180				uart_ao_a_pins: uart_ao_a {
1181					mux {
1182						groups = "uart_ao_tx_a",
1183							"uart_ao_rx_a";
1184						function = "uart_ao_a";
1185					};
1186				};
1187
1188				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1189					mux {
1190						groups = "uart_ao_cts_a",
1191							"uart_ao_rts_a";
1192						function = "uart_ao_a";
1193					};
1194				};
1195
1196				uart_ao_b_pins: uart_ao_b {
1197					mux {
1198						groups = "uart_ao_tx_b",
1199							"uart_ao_rx_b";
1200						function = "uart_ao_b";
1201					};
1202				};
1203
1204				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1205					mux {
1206						groups = "uart_ao_cts_b",
1207							"uart_ao_rts_b";
1208						function = "uart_ao_b";
1209					};
1210				};
1211			};
1212
1213			sec_AO: ao-secure@140 {
1214				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1215				reg = <0x0 0x140 0x0 0x140>;
1216				amlogic,has-chip-id;
1217			};
1218
1219			pwm_AO_ab: pwm@7000 {
1220				compatible = "amlogic,meson-axg-ao-pwm";
1221				reg = <0x0 0x07000 0x0 0x20>;
1222				#pwm-cells = <3>;
1223				status = "disabled";
1224			};
1225
1226			pwm_AO_cd: pwm@2000 {
1227				compatible = "amlogic,meson-axg-ao-pwm";
1228				reg = <0x0 0x02000  0x0 0x20>;
1229				#pwm-cells = <3>;
1230				status = "disabled";
1231			};
1232
1233			i2c_AO: i2c@5000 {
1234				compatible = "amlogic,meson-axg-i2c";
1235				reg = <0x0 0x05000 0x0 0x20>;
1236				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1237				clocks = <&clkc CLKID_AO_I2C>;
1238				#address-cells = <1>;
1239				#size-cells = <0>;
1240				status = "disabled";
1241			};
1242
1243			uart_AO: serial@3000 {
1244				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1245				reg = <0x0 0x3000 0x0 0x18>;
1246				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1247				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1248				clock-names = "xtal", "pclk", "baud";
1249				status = "disabled";
1250			};
1251
1252			uart_AO_B: serial@4000 {
1253				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1254				reg = <0x0 0x4000 0x0 0x18>;
1255				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1256				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1257				clock-names = "xtal", "pclk", "baud";
1258				status = "disabled";
1259			};
1260
1261			ir: ir@8000 {
1262				compatible = "amlogic,meson-gxbb-ir";
1263				reg = <0x0 0x8000 0x0 0x20>;
1264				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1265				status = "disabled";
1266			};
1267
1268			saradc: adc@9000 {
1269				compatible = "amlogic,meson-axg-saradc",
1270					"amlogic,meson-saradc";
1271				reg = <0x0 0x9000 0x0 0x38>;
1272				#io-channel-cells = <1>;
1273				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1274				clocks = <&xtal>,
1275					<&clkc_AO CLKID_AO_SAR_ADC>,
1276					<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1277					<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1278				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1279				status = "disabled";
1280			};
1281		};
1282	};
1283};
1284