1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
12
13/ {
14	compatible = "amlogic,meson-axg";
15
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	reserved-memory {
21		#address-cells = <2>;
22		#size-cells = <2>;
23		ranges;
24
25		/* 16 MiB reserved for Hardware ROM Firmware */
26		hwrom_reserved: hwrom@0 {
27			reg = <0x0 0x0 0x0 0x1000000>;
28			no-map;
29		};
30
31		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
32		secmon_reserved: secmon@5000000 {
33			reg = <0x0 0x05000000 0x0 0x300000>;
34			no-map;
35		};
36	};
37
38	cpus {
39		#address-cells = <0x2>;
40		#size-cells = <0x0>;
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53", "arm,armv8";
45			reg = <0x0 0x0>;
46			enable-method = "psci";
47			next-level-cache = <&l2>;
48		};
49
50		cpu1: cpu@1 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53", "arm,armv8";
53			reg = <0x0 0x1>;
54			enable-method = "psci";
55			next-level-cache = <&l2>;
56		};
57
58		cpu2: cpu@2 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a53", "arm,armv8";
61			reg = <0x0 0x2>;
62			enable-method = "psci";
63			next-level-cache = <&l2>;
64		};
65
66		cpu3: cpu@3 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a53", "arm,armv8";
69			reg = <0x0 0x3>;
70			enable-method = "psci";
71			next-level-cache = <&l2>;
72		};
73
74		l2: l2-cache0 {
75			compatible = "cache";
76		};
77	};
78
79	arm-pmu {
80		compatible = "arm,cortex-a53-pmu";
81		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
85		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
86	};
87
88	psci {
89		compatible = "arm,psci-1.0";
90		method = "smc";
91	};
92
93	timer {
94		compatible = "arm,armv8-timer";
95		interrupts = <GIC_PPI 13
96			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 14
98			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
99			     <GIC_PPI 11
100			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
101			     <GIC_PPI 10
102			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
103	};
104
105	xtal: xtal-clk {
106		compatible = "fixed-clock";
107		clock-frequency = <24000000>;
108		clock-output-names = "xtal";
109		#clock-cells = <0>;
110	};
111
112	ao_alt_xtal: ao_alt_xtal-clk {
113		compatible = "fixed-clock";
114		clock-frequency = <32000000>;
115		clock-output-names = "ao_alt_xtal";
116		#clock-cells = <0>;
117	};
118
119	soc {
120		compatible = "simple-bus";
121		#address-cells = <2>;
122		#size-cells = <2>;
123		ranges;
124
125		apb: apb@ffe00000 {
126			compatible = "simple-bus";
127			reg = <0x0 0xffe00000 0x0 0x200000>;
128			#address-cells = <2>;
129			#size-cells = <2>;
130			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
131
132			sd_emmc_b: sd@5000 {
133				compatible = "amlogic,meson-axg-mmc";
134				reg = <0x0 0x5000 0x0 0x2000>;
135				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
136				status = "disabled";
137				clocks = <&clkc CLKID_SD_EMMC_B>,
138					<&clkc CLKID_SD_EMMC_B_CLK0>,
139					<&clkc CLKID_FCLK_DIV2>;
140				clock-names = "core", "clkin0", "clkin1";
141				resets = <&reset RESET_SD_EMMC_B>;
142			};
143
144			sd_emmc_c: mmc@7000 {
145				compatible = "amlogic,meson-axg-mmc";
146				reg = <0x0 0x7000 0x0 0x2000>;
147				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
148				status = "disabled";
149				clocks = <&clkc CLKID_SD_EMMC_C>,
150					<&clkc CLKID_SD_EMMC_C_CLK0>,
151					<&clkc CLKID_FCLK_DIV2>;
152				clock-names = "core", "clkin0", "clkin1";
153				resets = <&reset RESET_SD_EMMC_C>;
154			};
155		};
156
157		cbus: bus@ffd00000 {
158			compatible = "simple-bus";
159			reg = <0x0 0xffd00000 0x0 0x25000>;
160			#address-cells = <2>;
161			#size-cells = <2>;
162			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
163
164			gpio_intc: interrupt-controller@f080 {
165				compatible = "amlogic,meson-gpio-intc";
166				reg = <0x0 0xf080 0x0 0x10>;
167				interrupt-controller;
168				#interrupt-cells = <2>;
169				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
170				status = "disabled";
171			};
172
173			pwm_ab: pwm@1b000 {
174				compatible = "amlogic,meson-axg-ee-pwm";
175				reg = <0x0 0x1b000 0x0 0x20>;
176				#pwm-cells = <3>;
177				status = "disabled";
178			};
179
180			pwm_cd: pwm@1a000 {
181				compatible = "amlogic,meson-axg-ee-pwm";
182				reg = <0x0 0x1a000 0x0 0x20>;
183				#pwm-cells = <3>;
184				status = "disabled";
185			};
186
187			reset: reset-controller@1004 {
188				compatible = "amlogic,meson-axg-reset";
189				reg = <0x0 0x01004 0x0 0x9c>;
190				#reset-cells = <1>;
191			};
192
193			spicc0: spi@13000 {
194				compatible = "amlogic,meson-axg-spicc";
195				reg = <0x0 0x13000 0x0 0x3c>;
196				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
197				clocks = <&clkc CLKID_SPICC0>;
198				clock-names = "core";
199				#address-cells = <1>;
200				#size-cells = <0>;
201				status = "disabled";
202			};
203
204			spicc1: spi@15000 {
205				compatible = "amlogic,meson-axg-spicc";
206				reg = <0x0 0x15000 0x0 0x3c>;
207				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
208				clocks = <&clkc CLKID_SPICC1>;
209				clock-names = "core";
210				#address-cells = <1>;
211				#size-cells = <0>;
212				status = "disabled";
213			};
214
215			i2c0: i2c@1f000 {
216				compatible = "amlogic,meson-axg-i2c";
217				reg = <0x0 0x1f000 0x0 0x20>;
218				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
219				clocks = <&clkc CLKID_I2C>;
220				#address-cells = <1>;
221				#size-cells = <0>;
222				status = "disabled";
223			};
224
225			i2c1: i2c@1e000 {
226				compatible = "amlogic,meson-axg-i2c";
227				reg = <0x0 0x1e000 0x0 0x20>;
228				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
229				clocks = <&clkc CLKID_I2C>;
230				#address-cells = <1>;
231				#size-cells = <0>;
232				status = "disabled";
233			};
234
235			i2c2: i2c@1d000 {
236				compatible = "amlogic,meson-axg-i2c";
237				reg = <0x0 0x1d000 0x0 0x20>;
238				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
239				clocks = <&clkc CLKID_I2C>;
240				#address-cells = <1>;
241				#size-cells = <0>;
242				status = "disabled";
243			};
244
245			i2c3: i2c@1c000 {
246				compatible = "amlogic,meson-axg-i2c";
247				reg = <0x0 0x1c000 0x0 0x20>;
248				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
249				clocks = <&clkc CLKID_I2C>;
250				#address-cells = <1>;
251				#size-cells = <0>;
252				status = "disabled";
253			};
254
255			uart_A: serial@24000 {
256				compatible = "amlogic,meson-gx-uart";
257				reg = <0x0 0x24000 0x0 0x18>;
258				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
259				status = "disabled";
260				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
261				clock-names = "xtal", "pclk", "baud";
262			};
263
264			uart_B: serial@23000 {
265				compatible = "amlogic,meson-gx-uart";
266				reg = <0x0 0x23000 0x0 0x18>;
267				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
268				status = "disabled";
269				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
270				clock-names = "xtal", "pclk", "baud";
271			};
272		};
273
274		ethmac: ethernet@ff3f0000 {
275			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
276			reg = <0x0 0xff3f0000 0x0 0x10000
277				0x0 0xff634540 0x0 0x8>;
278			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
279			interrupt-names = "macirq";
280			clocks = <&clkc CLKID_ETH>,
281				 <&clkc CLKID_FCLK_DIV2>,
282				 <&clkc CLKID_MPLL2>;
283			clock-names = "stmmaceth", "clkin0", "clkin1";
284			status = "disabled";
285		};
286
287		gic: interrupt-controller@ffc01000 {
288			compatible = "arm,gic-400";
289			reg = <0x0 0xffc01000 0 0x1000>,
290			      <0x0 0xffc02000 0 0x2000>,
291			      <0x0 0xffc04000 0 0x2000>,
292			      <0x0 0xffc06000 0 0x2000>;
293			interrupt-controller;
294			interrupts = <GIC_PPI 9
295				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
296			#interrupt-cells = <3>;
297			#address-cells = <0>;
298		};
299
300		hiubus: bus@ff63c000 {
301			compatible = "simple-bus";
302			reg = <0x0 0xff63c000 0x0 0x1c00>;
303			#address-cells = <2>;
304			#size-cells = <2>;
305			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
306
307			sysctrl: system-controller@0 {
308				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
309				reg = <0 0 0 0x400>;
310
311				clkc: clock-controller {
312					compatible = "amlogic,axg-clkc";
313					#clock-cells = <1>;
314				};
315			};
316		};
317
318		mailbox: mailbox@ff63dc00 {
319			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
320			reg = <0 0xff63dc00 0 0x400>;
321			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
322				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
323				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
324			#mbox-cells = <1>;
325		};
326
327		periphs: periphs@ff634000 {
328			compatible = "simple-bus";
329			reg = <0x0 0xff634000 0x0 0x2000>;
330			#address-cells = <2>;
331			#size-cells = <2>;
332			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
333
334			hwrng: rng {
335				compatible = "amlogic,meson-rng";
336				reg = <0x0 0x18 0x0 0x4>;
337				clocks = <&clkc CLKID_RNG0>;
338				clock-names = "core";
339			};
340
341			pinctrl_periphs: pinctrl@480 {
342				compatible = "amlogic,meson-axg-periphs-pinctrl";
343				#address-cells = <2>;
344				#size-cells = <2>;
345				ranges;
346
347				gpio: bank@480 {
348					reg = <0x0 0x00480 0x0 0x40>,
349						<0x0 0x004e8 0x0 0x14>,
350						<0x0 0x00520 0x0 0x14>,
351						<0x0 0x00430 0x0 0x3c>;
352					reg-names = "mux", "pull", "pull-enable", "gpio";
353					gpio-controller;
354					#gpio-cells = <2>;
355					gpio-ranges = <&pinctrl_periphs 0 0 86>;
356				};
357
358				emmc_pins: emmc {
359					mux {
360						groups = "emmc_nand_d0",
361							"emmc_nand_d1",
362							"emmc_nand_d2",
363							"emmc_nand_d3",
364							"emmc_nand_d4",
365							"emmc_nand_d5",
366							"emmc_nand_d6",
367							"emmc_nand_d7",
368							"emmc_clk",
369							"emmc_cmd",
370							"emmc_ds";
371						function = "emmc";
372					};
373				};
374
375				emmc_clk_gate_pins: emmc_clk_gate {
376					mux {
377						groups = "BOOT_8";
378						function = "gpio_periphs";
379					};
380					cfg-pull-down {
381						pins = "BOOT_8";
382						bias-pull-down;
383					};
384				};
385
386				sdio_pins: sdio {
387					mux {
388						groups = "sdio_d0",
389							"sdio_d1",
390							"sdio_d2",
391							"sdio_d3",
392							"sdio_cmd",
393							"sdio_clk";
394						function = "sdio";
395					};
396				};
397
398				sdio_clk_gate_pins: sdio_clk_gate {
399					mux {
400						groups = "GPIOX_4";
401						function = "gpio_periphs";
402					};
403					cfg-pull-down {
404						pins = "GPIOX_4";
405						bias-pull-down;
406					};
407				};
408
409				eth_rmii_x_pins: eth-x-rmii {
410					mux {
411						groups = "eth_mdio_x",
412						       "eth_mdc_x",
413						       "eth_rgmii_rx_clk_x",
414						       "eth_rx_dv_x",
415						       "eth_rxd0_x",
416						       "eth_rxd1_x",
417						       "eth_txen_x",
418						       "eth_txd0_x",
419						       "eth_txd1_x";
420						function = "eth";
421					};
422				};
423
424				eth_rmii_y_pins: eth-y-rmii {
425					mux {
426						groups = "eth_mdio_y",
427						       "eth_mdc_y",
428						       "eth_rgmii_rx_clk_y",
429						       "eth_rx_dv_y",
430						       "eth_rxd0_y",
431						       "eth_rxd1_y",
432						       "eth_txen_y",
433						       "eth_txd0_y",
434						       "eth_txd1_y";
435						function = "eth";
436					};
437				};
438
439				eth_rgmii_x_pins: eth-x-rgmii {
440					mux {
441						groups = "eth_mdio_x",
442						       "eth_mdc_x",
443						       "eth_rgmii_rx_clk_x",
444						       "eth_rx_dv_x",
445						       "eth_rxd0_x",
446						       "eth_rxd1_x",
447						       "eth_rxd2_rgmii",
448						       "eth_rxd3_rgmii",
449						       "eth_rgmii_tx_clk",
450						       "eth_txen_x",
451						       "eth_txd0_x",
452						       "eth_txd1_x",
453						       "eth_txd2_rgmii",
454						       "eth_txd3_rgmii";
455						function = "eth";
456					};
457				};
458
459				eth_rgmii_y_pins: eth-y-rgmii {
460					mux {
461						groups = "eth_mdio_y",
462						       "eth_mdc_y",
463						       "eth_rgmii_rx_clk_y",
464						       "eth_rx_dv_y",
465						       "eth_rxd0_y",
466						       "eth_rxd1_y",
467						       "eth_rxd2_rgmii",
468						       "eth_rxd3_rgmii",
469						       "eth_rgmii_tx_clk",
470						       "eth_txen_y",
471						       "eth_txd0_y",
472						       "eth_txd1_y",
473						       "eth_txd2_rgmii",
474						       "eth_txd3_rgmii";
475						function = "eth";
476					};
477				};
478
479				pwm_a_a_pins: pwm_a_a {
480					mux {
481						groups = "pwm_a_a";
482						function = "pwm_a";
483					};
484				};
485
486				pwm_a_x18_pins: pwm_a_x18 {
487					mux {
488						groups = "pwm_a_x18";
489						function = "pwm_a";
490					};
491				};
492
493				pwm_a_x20_pins: pwm_a_x20 {
494					mux {
495						groups = "pwm_a_x20";
496						function = "pwm_a";
497					};
498				};
499
500				pwm_a_z_pins: pwm_a_z {
501					mux {
502						groups = "pwm_a_z";
503						function = "pwm_a";
504					};
505				};
506
507				pwm_b_a_pins: pwm_b_a {
508					mux {
509						groups = "pwm_b_a";
510						function = "pwm_b";
511					};
512				};
513
514				pwm_b_x_pins: pwm_b_x {
515					mux {
516						groups = "pwm_b_x";
517						function = "pwm_b";
518					};
519				};
520
521				pwm_b_z_pins: pwm_b_z {
522					mux {
523						groups = "pwm_b_z";
524						function = "pwm_b";
525					};
526				};
527
528				pwm_c_a_pins: pwm_c_a {
529					mux {
530						groups = "pwm_c_a";
531						function = "pwm_c";
532					};
533				};
534
535				pwm_c_x10_pins: pwm_c_x10 {
536					mux {
537						groups = "pwm_c_x10";
538						function = "pwm_c";
539					};
540				};
541
542				pwm_c_x17_pins: pwm_c_x17 {
543					mux {
544						groups = "pwm_c_x17";
545						function = "pwm_c";
546					};
547				};
548
549				pwm_d_x11_pins: pwm_d_x11 {
550					mux {
551						groups = "pwm_d_x11";
552						function = "pwm_d";
553					};
554				};
555
556				pwm_d_x16_pins: pwm_d_x16 {
557					mux {
558						groups = "pwm_d_x16";
559						function = "pwm_d";
560					};
561				};
562
563				spi0_pins: spi0 {
564					mux {
565						groups = "spi0_miso",
566							"spi0_mosi",
567							"spi0_clk";
568						function = "spi0";
569					};
570				};
571
572				spi0_ss0_pins: spi0_ss0 {
573					mux {
574						groups = "spi0_ss0";
575						function = "spi0";
576					};
577				};
578
579				spi0_ss1_pins: spi0_ss1 {
580					mux {
581						groups = "spi0_ss1";
582						function = "spi0";
583					};
584				};
585
586				spi0_ss2_pins: spi0_ss2 {
587					mux {
588						groups = "spi0_ss2";
589						function = "spi0";
590					};
591				};
592
593
594				spi1_a_pins: spi1_a {
595					mux {
596						groups = "spi1_miso_a",
597							"spi1_mosi_a",
598							"spi1_clk_a";
599						function = "spi1";
600					};
601				};
602
603				spi1_ss0_a_pins: spi1_ss0_a {
604					mux {
605						groups = "spi1_ss0_a";
606						function = "spi1";
607					};
608				};
609
610				spi1_ss1_pins: spi1_ss1 {
611					mux {
612						groups = "spi1_ss1";
613						function = "spi1";
614					};
615				};
616
617				spi1_x_pins: spi1_x {
618					mux {
619						groups = "spi1_miso_x",
620							"spi1_mosi_x",
621							"spi1_clk_x";
622						function = "spi1";
623					};
624				};
625
626				spi1_ss0_x_pins: spi1_ss0_x {
627					mux {
628						groups = "spi1_ss0_x";
629						function = "spi1";
630					};
631				};
632
633				i2c0_pins: i2c0 {
634					mux {
635						groups = "i2c0_sck",
636							"i2c0_sda";
637						function = "i2c0";
638					};
639				};
640
641				i2c1_z_pins: i2c1_z {
642					mux {
643						groups = "i2c1_sck_z",
644							"i2c1_sda_z";
645						function = "i2c1";
646					};
647				};
648
649				i2c1_x_pins: i2c1_x {
650					mux {
651						groups = "i2c1_sck_x",
652							"i2c1_sda_x";
653						function = "i2c1";
654					};
655				};
656
657				i2c2_x_pins: i2c2_x {
658					mux {
659						groups = "i2c2_sck_x",
660							"i2c2_sda_x";
661						function = "i2c2";
662					};
663				};
664
665				i2c2_a_pins: i2c2_a {
666					mux {
667						groups = "i2c2_sck_a",
668							"i2c2_sda_a";
669						function = "i2c2";
670					};
671				};
672
673				i2c3_a6_pins: i2c3_a6 {
674					mux {
675						groups = "i2c3_sda_a6",
676							"i2c3_sck_a7";
677						function = "i2c3";
678					};
679				};
680
681				i2c3_a12_pins: i2c3_a12 {
682					mux {
683						groups = "i2c3_sda_a12",
684							"i2c3_sck_a13";
685						function = "i2c3";
686					};
687				};
688
689				i2c3_a19_pins: i2c3_a19 {
690					mux {
691						groups = "i2c3_sda_a19",
692							"i2c3_sck_a20";
693						function = "i2c3";
694					};
695				};
696
697				uart_a_pins: uart_a {
698					mux {
699						groups = "uart_tx_a",
700							"uart_rx_a";
701						function = "uart_a";
702					};
703				};
704
705				uart_a_cts_rts_pins: uart_a_cts_rts {
706					mux {
707						groups = "uart_cts_a",
708							"uart_rts_a";
709						function = "uart_a";
710					};
711				};
712
713				uart_b_x_pins: uart_b_x {
714					mux {
715						groups = "uart_tx_b_x",
716							"uart_rx_b_x";
717						function = "uart_b";
718					};
719				};
720
721				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
722					mux {
723						groups = "uart_cts_b_x",
724							"uart_rts_b_x";
725						function = "uart_b";
726					};
727				};
728
729				uart_b_z_pins: uart_b_z {
730					mux {
731						groups = "uart_tx_b_z",
732							"uart_rx_b_z";
733						function = "uart_b";
734					};
735				};
736
737				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
738					mux {
739						groups = "uart_cts_b_z",
740							"uart_rts_b_z";
741						function = "uart_b";
742					};
743				};
744
745				uart_ao_b_z_pins: uart_ao_b_z {
746					mux {
747						groups = "uart_ao_tx_b_z",
748							"uart_ao_rx_b_z";
749						function = "uart_ao_b_z";
750					};
751				};
752
753				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
754					mux {
755						groups = "uart_ao_cts_b_z",
756							"uart_ao_rts_b_z";
757						function = "uart_ao_b_z";
758					};
759				};
760
761				mclk_b_pins: mclk_b {
762					mux {
763						groups = "mclk_b";
764						function = "mclk_b";
765					};
766				};
767
768				mclk_c_pins: mclk_c {
769					mux {
770						groups = "mclk_c";
771						function = "mclk_c";
772					};
773				};
774
775				tdma_sclk_pins: tdma_sclk {
776					mux {
777						groups = "tdma_sclk";
778						function = "tdma";
779					};
780				};
781
782				tdma_sclk_slv_pins: tdma_sclk_slv {
783					mux {
784						groups = "tdma_sclk_slv";
785						function = "tdma";
786					};
787				};
788
789				tdma_fs_pins: tdma_fs {
790					mux {
791						groups = "tdma_fs";
792						function = "tdma";
793					};
794				};
795
796				tdma_fs_slv_pins: tdma_fs_slv {
797					mux {
798						groups = "tdma_fs_slv";
799						function = "tdma";
800					};
801				};
802
803				tdma_din0_pins: tdma_din0 {
804					mux {
805						groups = "tdma_din0";
806						function = "tdma";
807					};
808				};
809
810				tdma_dout0_x14_pins: tdma_dout0_x14 {
811					mux {
812						groups = "tdma_dout0_x14";
813						function = "tdma";
814					};
815				};
816
817				tdma_dout0_x15_pins: tdma_dout0_x15 {
818					mux {
819						groups = "tdma_dout0_x15";
820						function = "tdma";
821					};
822				};
823
824				tdma_dout1_pins: tdma_dout1 {
825					mux {
826						groups = "tdma_dout1";
827						function = "tdma";
828					};
829				};
830
831				tdma_din1_pins: tdma_din1 {
832					mux {
833						groups = "tdma_din1";
834						function = "tdma";
835					};
836				};
837
838				tdmb_sclk_pins: tdmb_sclk {
839					mux {
840						groups = "tdmb_sclk";
841						function = "tdmb";
842					};
843				};
844
845				tdmb_sclk_slv_pins: tdmb_sclk_slv {
846					mux {
847						groups = "tdmb_sclk_slv";
848						function = "tdmb";
849					};
850				};
851
852				tdmb_fs_pins: tdmb_fs {
853					mux {
854						groups = "tdmb_fs";
855						function = "tdmb";
856					};
857				};
858
859				tdmb_fs_slv_pins: tdmb_fs_slv {
860					mux {
861						groups = "tdmb_fs_slv";
862						function = "tdmb";
863					};
864				};
865
866				tdmb_din0_pins: tdmb_din0 {
867					mux {
868						groups = "tdmb_din0";
869						function = "tdmb";
870					};
871				};
872
873				tdmb_dout0_pins: tdmb_dout0 {
874					mux {
875						groups = "tdmb_dout0";
876						function = "tdmb";
877					};
878				};
879
880				tdmb_din1_pins: tdmb_din1 {
881					mux {
882						groups = "tdmb_din1";
883						function = "tdmb";
884					};
885				};
886
887				tdmb_dout1_pins: tdmb_dout1 {
888					mux {
889						groups = "tdmb_dout1";
890						function = "tdmb";
891					};
892				};
893
894				tdmb_din2_pins: tdmb_din2 {
895					mux {
896						groups = "tdmb_din2";
897						function = "tdmb";
898					};
899				};
900
901				tdmb_dout2_pins: tdmb_dout2 {
902					mux {
903						groups = "tdmb_dout2";
904						function = "tdmb";
905					};
906				};
907
908				tdmb_din3_pins: tdmb_din3 {
909					mux {
910						groups = "tdmb_din3";
911						function = "tdmb";
912					};
913				};
914
915				tdmb_dout3_pins: tdmb_dout3 {
916					mux {
917						groups = "tdmb_dout3";
918						function = "tdmb";
919					};
920				};
921
922				tdmc_sclk_pins: tdmc_sclk {
923					mux {
924						groups = "tdmc_sclk";
925						function = "tdmc";
926					};
927				};
928
929				tdmc_sclk_slv_pins: tdmc_sclk_slv {
930					mux {
931						groups = "tdmc_sclk_slv";
932						function = "tdmc";
933					};
934				};
935
936				tdmc_fs_pins: tdmc_fs {
937					mux {
938						groups = "tdmc_fs";
939						function = "tdmc";
940					};
941				};
942
943				tdmc_fs_slv_pins: tdmc_fs_slv {
944					mux {
945						groups = "tdmc_fs_slv";
946						function = "tdmc";
947					};
948				};
949
950				tdmc_din0_pins: tdmc_din0 {
951					mux {
952						groups = "tdmc_din0";
953						function = "tdmc";
954					};
955				};
956
957				tdmc_dout0_pins: tdmc_dout0 {
958					mux {
959						groups = "tdmc_dout0";
960						function = "tdmc";
961					};
962				};
963
964				tdmc_din1_pins: tdmc_din1 {
965					mux {
966						groups = "tdmc_din1";
967						function = "tdmc";
968					};
969				};
970
971				tdmc_dout1_pins: tdmc_dout1 {
972					mux {
973						groups = "tdmc_dout1";
974						function = "tdmc";
975					};
976				};
977
978				tdmc_din2_pins: tdmc_din2 {
979					mux {
980						groups = "tdmc_din2";
981						function = "tdmc";
982					};
983				};
984
985				tdmc_dout2_pins: tdmc_dout2 {
986					mux {
987						groups = "tdmc_dout2";
988						function = "tdmc";
989					};
990				};
991
992				tdmc_din3_pins: tdmc_din3 {
993					mux {
994						groups = "tdmc_din3";
995						function = "tdmc";
996					};
997				};
998
999				tdmc_dout3_pins: tdmc_dout3 {
1000					mux {
1001						groups = "tdmc_dout3";
1002						function = "tdmc";
1003					};
1004				};
1005			};
1006		};
1007
1008		sram: sram@fffc0000 {
1009			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1010			reg = <0x0 0xfffc0000 0x0 0x20000>;
1011			#address-cells = <1>;
1012			#size-cells = <1>;
1013			ranges = <0 0x0 0xfffc0000 0x20000>;
1014
1015			cpu_scp_lpri: scp-shmem@0 {
1016				compatible = "amlogic,meson-axg-scp-shmem";
1017				reg = <0x13000 0x400>;
1018			};
1019
1020			cpu_scp_hpri: scp-shmem@200 {
1021				compatible = "amlogic,meson-axg-scp-shmem";
1022				reg = <0x13400 0x400>;
1023			};
1024		};
1025
1026		aobus: bus@ff800000 {
1027			compatible = "simple-bus";
1028			reg = <0x0 0xff800000 0x0 0x100000>;
1029			#address-cells = <2>;
1030			#size-cells = <2>;
1031			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1032
1033			pinctrl_aobus: pinctrl@14 {
1034				compatible = "amlogic,meson-axg-aobus-pinctrl";
1035				#address-cells = <2>;
1036				#size-cells = <2>;
1037				ranges;
1038
1039				gpio_ao: bank@14 {
1040					reg = <0x0 0x00014 0x0 0x8>,
1041						<0x0 0x0002c 0x0 0x4>,
1042						<0x0 0x00024 0x0 0x8>;
1043					reg-names = "mux", "pull", "gpio";
1044					gpio-controller;
1045					#gpio-cells = <2>;
1046					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1047				};
1048
1049				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1050					mux {
1051						groups = "i2c_ao_sck_4";
1052						function = "i2c_ao";
1053					};
1054				};
1055
1056				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1057					mux {
1058						groups = "i2c_ao_sck_8";
1059						function = "i2c_ao";
1060					};
1061				};
1062
1063				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1064					mux {
1065						groups = "i2c_ao_sck_10";
1066						function = "i2c_ao";
1067					};
1068				};
1069
1070				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1071					mux {
1072						groups = "i2c_ao_sda_5";
1073						function = "i2c_ao";
1074					};
1075				};
1076
1077				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1078					mux {
1079						groups = "i2c_ao_sda_9";
1080						function = "i2c_ao";
1081					};
1082				};
1083
1084				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1085					mux {
1086						groups = "i2c_ao_sda_11";
1087						function = "i2c_ao";
1088					};
1089				};
1090
1091				remote_input_ao_pins: remote_input_ao {
1092					mux {
1093						groups = "remote_input_ao";
1094						function = "remote_input_ao";
1095					};
1096				};
1097
1098				uart_ao_a_pins: uart_ao_a {
1099					mux {
1100						groups = "uart_ao_tx_a",
1101							"uart_ao_rx_a";
1102						function = "uart_ao_a";
1103					};
1104				};
1105
1106				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1107					mux {
1108						groups = "uart_ao_cts_a",
1109							"uart_ao_rts_a";
1110						function = "uart_ao_a";
1111					};
1112				};
1113
1114				uart_ao_b_pins: uart_ao_b {
1115					mux {
1116						groups = "uart_ao_tx_b",
1117							"uart_ao_rx_b";
1118						function = "uart_ao_b";
1119					};
1120				};
1121
1122				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1123					mux {
1124						groups = "uart_ao_cts_b",
1125							"uart_ao_rts_b";
1126						function = "uart_ao_b";
1127					};
1128				};
1129			};
1130
1131			sec_AO: ao-secure@140 {
1132				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1133				reg = <0x0 0x140 0x0 0x140>;
1134				amlogic,has-chip-id;
1135			};
1136
1137			pwm_AO_ab: pwm@7000 {
1138				compatible = "amlogic,meson-axg-ao-pwm";
1139				reg = <0x0 0x07000 0x0 0x20>;
1140				#pwm-cells = <3>;
1141				status = "disabled";
1142			};
1143
1144			pwm_AO_cd: pwm@2000 {
1145				compatible = "amlogic,meson-axg-ao-pwm";
1146				reg = <0x0 0x02000  0x0 0x20>;
1147				#pwm-cells = <3>;
1148				status = "disabled";
1149			};
1150
1151			i2c_AO: i2c@5000 {
1152				compatible = "amlogic,meson-axg-i2c";
1153				reg = <0x0 0x05000 0x0 0x20>;
1154				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1155				clocks = <&clkc CLKID_AO_I2C>;
1156				#address-cells = <1>;
1157				#size-cells = <0>;
1158				status = "disabled";
1159			};
1160
1161			uart_AO: serial@3000 {
1162				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1163				reg = <0x0 0x3000 0x0 0x18>;
1164				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1165				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1166				clock-names = "xtal", "pclk", "baud";
1167				status = "disabled";
1168			};
1169
1170			uart_AO_B: serial@4000 {
1171				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1172				reg = <0x0 0x4000 0x0 0x18>;
1173				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1174				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1175				clock-names = "xtal", "pclk", "baud";
1176				status = "disabled";
1177			};
1178
1179			ir: ir@8000 {
1180				compatible = "amlogic,meson-gxbb-ir";
1181				reg = <0x0 0x8000 0x0 0x20>;
1182				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1183				status = "disabled";
1184			};
1185		};
1186	};
1187};
1188