1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-audio-clkc.h> 10#include <dt-bindings/clock/axg-clkc.h> 11#include <dt-bindings/clock/axg-aoclkc.h> 12#include <dt-bindings/gpio/meson-axg-gpio.h> 13#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 14 15/ { 16 compatible = "amlogic,meson-axg"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 reserved-memory { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 /* 16 MiB reserved for Hardware ROM Firmware */ 28 hwrom_reserved: hwrom@0 { 29 reg = <0x0 0x0 0x0 0x1000000>; 30 no-map; 31 }; 32 33 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 34 secmon_reserved: secmon@5000000 { 35 reg = <0x0 0x05000000 0x0 0x300000>; 36 no-map; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <0x2>; 42 #size-cells = <0x0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 }; 51 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <0x0 0x1>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0x0 0x2>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 reg = <0x0 0x3>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 l2: l2-cache0 { 77 compatible = "cache"; 78 }; 79 }; 80 81 arm-pmu { 82 compatible = "arm,cortex-a53-pmu"; 83 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 102 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 105 }; 106 107 xtal: xtal-clk { 108 compatible = "fixed-clock"; 109 clock-frequency = <24000000>; 110 clock-output-names = "xtal"; 111 #clock-cells = <0>; 112 }; 113 114 ao_alt_xtal: ao_alt_xtal-clk { 115 compatible = "fixed-clock"; 116 clock-frequency = <32000000>; 117 clock-output-names = "ao_alt_xtal"; 118 #clock-cells = <0>; 119 }; 120 121 soc { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 apb: apb@ffe00000 { 128 compatible = "simple-bus"; 129 reg = <0x0 0xffe00000 0x0 0x200000>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 133 134 sd_emmc_b: sd@5000 { 135 compatible = "amlogic,meson-axg-mmc"; 136 reg = <0x0 0x5000 0x0 0x2000>; 137 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 138 status = "disabled"; 139 clocks = <&clkc CLKID_SD_EMMC_B>, 140 <&clkc CLKID_SD_EMMC_B_CLK0>, 141 <&clkc CLKID_FCLK_DIV2>; 142 clock-names = "core", "clkin0", "clkin1"; 143 resets = <&reset RESET_SD_EMMC_B>; 144 }; 145 146 sd_emmc_c: mmc@7000 { 147 compatible = "amlogic,meson-axg-mmc"; 148 reg = <0x0 0x7000 0x0 0x2000>; 149 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 150 status = "disabled"; 151 clocks = <&clkc CLKID_SD_EMMC_C>, 152 <&clkc CLKID_SD_EMMC_C_CLK0>, 153 <&clkc CLKID_FCLK_DIV2>; 154 clock-names = "core", "clkin0", "clkin1"; 155 resets = <&reset RESET_SD_EMMC_C>; 156 }; 157 }; 158 159 audio: bus@ff642000 { 160 compatible = "simple-bus"; 161 reg = <0x0 0xff642000 0x0 0x2000>; 162 #address-cells = <2>; 163 #size-cells = <2>; 164 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 165 166 clkc_audio: clock-controller@0 { 167 compatible = "amlogic,axg-audio-clkc"; 168 reg = <0x0 0x0 0x0 0xb4>; 169 #clock-cells = <1>; 170 171 clocks = <&clkc CLKID_AUDIO>, 172 <&clkc CLKID_MPLL0>, 173 <&clkc CLKID_MPLL1>, 174 <&clkc CLKID_MPLL2>, 175 <&clkc CLKID_MPLL3>, 176 <&clkc CLKID_HIFI_PLL>, 177 <&clkc CLKID_FCLK_DIV3>, 178 <&clkc CLKID_FCLK_DIV4>, 179 <&clkc CLKID_GP0_PLL>; 180 clock-names = "pclk", 181 "mst_in0", 182 "mst_in1", 183 "mst_in2", 184 "mst_in3", 185 "mst_in4", 186 "mst_in5", 187 "mst_in6", 188 "mst_in7"; 189 190 resets = <&reset RESET_AUDIO>; 191 }; 192 193 arb: reset-controller@280 { 194 compatible = "amlogic,meson-axg-audio-arb"; 195 reg = <0x0 0x280 0x0 0x4>; 196 #reset-cells = <1>; 197 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 198 }; 199 200 tdmin_a: audio-controller@300 { 201 compatible = "amlogic,axg-tdmin"; 202 reg = <0x0 0x300 0x0 0x40>; 203 sound-name-prefix = "TDMIN_A"; 204 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 205 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 206 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 207 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 208 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 209 clock-names = "pclk", "sclk", "sclk_sel", 210 "lrclk", "lrclk_sel"; 211 status = "disabled"; 212 }; 213 214 tdmin_b: audio-controller@340 { 215 compatible = "amlogic,axg-tdmin"; 216 reg = <0x0 0x340 0x0 0x40>; 217 sound-name-prefix = "TDMIN_B"; 218 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 219 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 220 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 221 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 222 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 223 clock-names = "pclk", "sclk", "sclk_sel", 224 "lrclk", "lrclk_sel"; 225 status = "disabled"; 226 }; 227 228 tdmin_c: audio-controller@380 { 229 compatible = "amlogic,axg-tdmin"; 230 reg = <0x0 0x380 0x0 0x40>; 231 sound-name-prefix = "TDMIN_C"; 232 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 233 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 234 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 235 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 236 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 237 clock-names = "pclk", "sclk", "sclk_sel", 238 "lrclk", "lrclk_sel"; 239 status = "disabled"; 240 }; 241 242 tdmin_lb: audio-controller@3c0 { 243 compatible = "amlogic,axg-tdmin"; 244 reg = <0x0 0x3c0 0x0 0x40>; 245 sound-name-prefix = "TDMIN_LB"; 246 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 247 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 248 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 249 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 250 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 251 clock-names = "pclk", "sclk", "sclk_sel", 252 "lrclk", "lrclk_sel"; 253 status = "disabled"; 254 }; 255 256 spdifout: audio-controller@480 { 257 compatible = "amlogic,axg-spdifout"; 258 reg = <0x0 0x480 0x0 0x50>; 259 #sound-dai-cells = <0>; 260 sound-name-prefix = "SPDIFOUT"; 261 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 262 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 263 clock-names = "pclk", "mclk"; 264 status = "disabled"; 265 }; 266 }; 267 268 cbus: bus@ffd00000 { 269 compatible = "simple-bus"; 270 reg = <0x0 0xffd00000 0x0 0x25000>; 271 #address-cells = <2>; 272 #size-cells = <2>; 273 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 274 275 gpio_intc: interrupt-controller@f080 { 276 compatible = "amlogic,meson-gpio-intc"; 277 reg = <0x0 0xf080 0x0 0x10>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 281 status = "disabled"; 282 }; 283 284 pwm_ab: pwm@1b000 { 285 compatible = "amlogic,meson-axg-ee-pwm"; 286 reg = <0x0 0x1b000 0x0 0x20>; 287 #pwm-cells = <3>; 288 status = "disabled"; 289 }; 290 291 pwm_cd: pwm@1a000 { 292 compatible = "amlogic,meson-axg-ee-pwm"; 293 reg = <0x0 0x1a000 0x0 0x20>; 294 #pwm-cells = <3>; 295 status = "disabled"; 296 }; 297 298 reset: reset-controller@1004 { 299 compatible = "amlogic,meson-axg-reset"; 300 reg = <0x0 0x01004 0x0 0x9c>; 301 #reset-cells = <1>; 302 }; 303 304 spicc0: spi@13000 { 305 compatible = "amlogic,meson-axg-spicc"; 306 reg = <0x0 0x13000 0x0 0x3c>; 307 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&clkc CLKID_SPICC0>; 309 clock-names = "core"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 spicc1: spi@15000 { 316 compatible = "amlogic,meson-axg-spicc"; 317 reg = <0x0 0x15000 0x0 0x3c>; 318 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clkc CLKID_SPICC1>; 320 clock-names = "core"; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 status = "disabled"; 324 }; 325 326 i2c0: i2c@1f000 { 327 compatible = "amlogic,meson-axg-i2c"; 328 reg = <0x0 0x1f000 0x0 0x20>; 329 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 330 clocks = <&clkc CLKID_I2C>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 status = "disabled"; 334 }; 335 336 i2c1: i2c@1e000 { 337 compatible = "amlogic,meson-axg-i2c"; 338 reg = <0x0 0x1e000 0x0 0x20>; 339 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 340 clocks = <&clkc CLKID_I2C>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 i2c2: i2c@1d000 { 347 compatible = "amlogic,meson-axg-i2c"; 348 reg = <0x0 0x1d000 0x0 0x20>; 349 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 350 clocks = <&clkc CLKID_I2C>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 status = "disabled"; 354 }; 355 356 i2c3: i2c@1c000 { 357 compatible = "amlogic,meson-axg-i2c"; 358 reg = <0x0 0x1c000 0x0 0x20>; 359 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 360 clocks = <&clkc CLKID_I2C>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 uart_A: serial@24000 { 367 compatible = "amlogic,meson-gx-uart"; 368 reg = <0x0 0x24000 0x0 0x18>; 369 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 370 status = "disabled"; 371 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 372 clock-names = "xtal", "pclk", "baud"; 373 }; 374 375 uart_B: serial@23000 { 376 compatible = "amlogic,meson-gx-uart"; 377 reg = <0x0 0x23000 0x0 0x18>; 378 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 379 status = "disabled"; 380 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 381 clock-names = "xtal", "pclk", "baud"; 382 }; 383 }; 384 385 ethmac: ethernet@ff3f0000 { 386 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 387 reg = <0x0 0xff3f0000 0x0 0x10000 388 0x0 0xff634540 0x0 0x8>; 389 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 390 interrupt-names = "macirq"; 391 clocks = <&clkc CLKID_ETH>, 392 <&clkc CLKID_FCLK_DIV2>, 393 <&clkc CLKID_MPLL2>; 394 clock-names = "stmmaceth", "clkin0", "clkin1"; 395 status = "disabled"; 396 }; 397 398 gic: interrupt-controller@ffc01000 { 399 compatible = "arm,gic-400"; 400 reg = <0x0 0xffc01000 0 0x1000>, 401 <0x0 0xffc02000 0 0x2000>, 402 <0x0 0xffc04000 0 0x2000>, 403 <0x0 0xffc06000 0 0x2000>; 404 interrupt-controller; 405 interrupts = <GIC_PPI 9 406 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 407 #interrupt-cells = <3>; 408 #address-cells = <0>; 409 }; 410 411 hiubus: bus@ff63c000 { 412 compatible = "simple-bus"; 413 reg = <0x0 0xff63c000 0x0 0x1c00>; 414 #address-cells = <2>; 415 #size-cells = <2>; 416 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 417 418 sysctrl: system-controller@0 { 419 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 420 reg = <0 0 0 0x400>; 421 422 clkc: clock-controller { 423 compatible = "amlogic,axg-clkc"; 424 #clock-cells = <1>; 425 }; 426 }; 427 }; 428 429 mailbox: mailbox@ff63dc00 { 430 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 431 reg = <0 0xff63dc00 0 0x400>; 432 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 433 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 435 #mbox-cells = <1>; 436 }; 437 438 periphs: periphs@ff634000 { 439 compatible = "simple-bus"; 440 reg = <0x0 0xff634000 0x0 0x2000>; 441 #address-cells = <2>; 442 #size-cells = <2>; 443 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 444 445 hwrng: rng { 446 compatible = "amlogic,meson-rng"; 447 reg = <0x0 0x18 0x0 0x4>; 448 clocks = <&clkc CLKID_RNG0>; 449 clock-names = "core"; 450 }; 451 452 pinctrl_periphs: pinctrl@480 { 453 compatible = "amlogic,meson-axg-periphs-pinctrl"; 454 #address-cells = <2>; 455 #size-cells = <2>; 456 ranges; 457 458 gpio: bank@480 { 459 reg = <0x0 0x00480 0x0 0x40>, 460 <0x0 0x004e8 0x0 0x14>, 461 <0x0 0x00520 0x0 0x14>, 462 <0x0 0x00430 0x0 0x3c>; 463 reg-names = "mux", "pull", "pull-enable", "gpio"; 464 gpio-controller; 465 #gpio-cells = <2>; 466 gpio-ranges = <&pinctrl_periphs 0 0 86>; 467 }; 468 469 emmc_pins: emmc { 470 mux { 471 groups = "emmc_nand_d0", 472 "emmc_nand_d1", 473 "emmc_nand_d2", 474 "emmc_nand_d3", 475 "emmc_nand_d4", 476 "emmc_nand_d5", 477 "emmc_nand_d6", 478 "emmc_nand_d7", 479 "emmc_clk", 480 "emmc_cmd", 481 "emmc_ds"; 482 function = "emmc"; 483 }; 484 }; 485 486 emmc_clk_gate_pins: emmc_clk_gate { 487 mux { 488 groups = "BOOT_8"; 489 function = "gpio_periphs"; 490 }; 491 cfg-pull-down { 492 pins = "BOOT_8"; 493 bias-pull-down; 494 }; 495 }; 496 497 sdio_pins: sdio { 498 mux { 499 groups = "sdio_d0", 500 "sdio_d1", 501 "sdio_d2", 502 "sdio_d3", 503 "sdio_cmd", 504 "sdio_clk"; 505 function = "sdio"; 506 }; 507 }; 508 509 sdio_clk_gate_pins: sdio_clk_gate { 510 mux { 511 groups = "GPIOX_4"; 512 function = "gpio_periphs"; 513 }; 514 cfg-pull-down { 515 pins = "GPIOX_4"; 516 bias-pull-down; 517 }; 518 }; 519 520 eth_rmii_x_pins: eth-x-rmii { 521 mux { 522 groups = "eth_mdio_x", 523 "eth_mdc_x", 524 "eth_rgmii_rx_clk_x", 525 "eth_rx_dv_x", 526 "eth_rxd0_x", 527 "eth_rxd1_x", 528 "eth_txen_x", 529 "eth_txd0_x", 530 "eth_txd1_x"; 531 function = "eth"; 532 }; 533 }; 534 535 eth_rmii_y_pins: eth-y-rmii { 536 mux { 537 groups = "eth_mdio_y", 538 "eth_mdc_y", 539 "eth_rgmii_rx_clk_y", 540 "eth_rx_dv_y", 541 "eth_rxd0_y", 542 "eth_rxd1_y", 543 "eth_txen_y", 544 "eth_txd0_y", 545 "eth_txd1_y"; 546 function = "eth"; 547 }; 548 }; 549 550 eth_rgmii_x_pins: eth-x-rgmii { 551 mux { 552 groups = "eth_mdio_x", 553 "eth_mdc_x", 554 "eth_rgmii_rx_clk_x", 555 "eth_rx_dv_x", 556 "eth_rxd0_x", 557 "eth_rxd1_x", 558 "eth_rxd2_rgmii", 559 "eth_rxd3_rgmii", 560 "eth_rgmii_tx_clk", 561 "eth_txen_x", 562 "eth_txd0_x", 563 "eth_txd1_x", 564 "eth_txd2_rgmii", 565 "eth_txd3_rgmii"; 566 function = "eth"; 567 }; 568 }; 569 570 eth_rgmii_y_pins: eth-y-rgmii { 571 mux { 572 groups = "eth_mdio_y", 573 "eth_mdc_y", 574 "eth_rgmii_rx_clk_y", 575 "eth_rx_dv_y", 576 "eth_rxd0_y", 577 "eth_rxd1_y", 578 "eth_rxd2_rgmii", 579 "eth_rxd3_rgmii", 580 "eth_rgmii_tx_clk", 581 "eth_txen_y", 582 "eth_txd0_y", 583 "eth_txd1_y", 584 "eth_txd2_rgmii", 585 "eth_txd3_rgmii"; 586 function = "eth"; 587 }; 588 }; 589 590 pdm_dclk_a14_pins: pdm_dclk_a14 { 591 mux { 592 groups = "pdm_dclk_a14"; 593 function = "pdm"; 594 }; 595 }; 596 597 pdm_dclk_a19_pins: pdm_dclk_a19 { 598 mux { 599 groups = "pdm_dclk_a19"; 600 function = "pdm"; 601 }; 602 }; 603 604 pdm_din0_pins: pdm_din0 { 605 mux { 606 groups = "pdm_din0"; 607 function = "pdm"; 608 }; 609 }; 610 611 pdm_din1_pins: pdm_din1 { 612 mux { 613 groups = "pdm_din1"; 614 function = "pdm"; 615 }; 616 }; 617 618 pdm_din2_pins: pdm_din2 { 619 mux { 620 groups = "pdm_din2"; 621 function = "pdm"; 622 }; 623 }; 624 625 pdm_din3_pins: pdm_din3 { 626 mux { 627 groups = "pdm_din3"; 628 function = "pdm"; 629 }; 630 }; 631 632 pwm_a_a_pins: pwm_a_a { 633 mux { 634 groups = "pwm_a_a"; 635 function = "pwm_a"; 636 }; 637 }; 638 639 pwm_a_x18_pins: pwm_a_x18 { 640 mux { 641 groups = "pwm_a_x18"; 642 function = "pwm_a"; 643 }; 644 }; 645 646 pwm_a_x20_pins: pwm_a_x20 { 647 mux { 648 groups = "pwm_a_x20"; 649 function = "pwm_a"; 650 }; 651 }; 652 653 pwm_a_z_pins: pwm_a_z { 654 mux { 655 groups = "pwm_a_z"; 656 function = "pwm_a"; 657 }; 658 }; 659 660 pwm_b_a_pins: pwm_b_a { 661 mux { 662 groups = "pwm_b_a"; 663 function = "pwm_b"; 664 }; 665 }; 666 667 pwm_b_x_pins: pwm_b_x { 668 mux { 669 groups = "pwm_b_x"; 670 function = "pwm_b"; 671 }; 672 }; 673 674 pwm_b_z_pins: pwm_b_z { 675 mux { 676 groups = "pwm_b_z"; 677 function = "pwm_b"; 678 }; 679 }; 680 681 pwm_c_a_pins: pwm_c_a { 682 mux { 683 groups = "pwm_c_a"; 684 function = "pwm_c"; 685 }; 686 }; 687 688 pwm_c_x10_pins: pwm_c_x10 { 689 mux { 690 groups = "pwm_c_x10"; 691 function = "pwm_c"; 692 }; 693 }; 694 695 pwm_c_x17_pins: pwm_c_x17 { 696 mux { 697 groups = "pwm_c_x17"; 698 function = "pwm_c"; 699 }; 700 }; 701 702 pwm_d_x11_pins: pwm_d_x11 { 703 mux { 704 groups = "pwm_d_x11"; 705 function = "pwm_d"; 706 }; 707 }; 708 709 pwm_d_x16_pins: pwm_d_x16 { 710 mux { 711 groups = "pwm_d_x16"; 712 function = "pwm_d"; 713 }; 714 }; 715 716 spdif_in_z_pins: spdif_in_z { 717 mux { 718 groups = "spdif_in_z"; 719 function = "spdif_in"; 720 }; 721 }; 722 723 spdif_in_a1_pins: spdif_in_a1 { 724 mux { 725 groups = "spdif_in_a1"; 726 function = "spdif_in"; 727 }; 728 }; 729 730 spdif_in_a7_pins: spdif_in_a7 { 731 mux { 732 groups = "spdif_in_a7"; 733 function = "spdif_in"; 734 }; 735 }; 736 737 spdif_in_a19_pins: spdif_in_a19 { 738 mux { 739 groups = "spdif_in_a19"; 740 function = "spdif_in"; 741 }; 742 }; 743 744 spdif_in_a20_pins: spdif_in_a20 { 745 mux { 746 groups = "spdif_in_a20"; 747 function = "spdif_in"; 748 }; 749 }; 750 751 spdif_out_z_pins: spdif_out_z { 752 mux { 753 groups = "spdif_out_z"; 754 function = "spdif_out"; 755 }; 756 }; 757 758 spdif_out_a1_pins: spdif_out_a1 { 759 mux { 760 groups = "spdif_out_a1"; 761 function = "spdif_out"; 762 }; 763 }; 764 765 spdif_out_a11_pins: spdif_out_a11 { 766 mux { 767 groups = "spdif_out_a11"; 768 function = "spdif_out"; 769 }; 770 }; 771 772 spdif_out_a19_pins: spdif_out_a19 { 773 mux { 774 groups = "spdif_out_a19"; 775 function = "spdif_out"; 776 }; 777 }; 778 779 spdif_out_a20_pins: spdif_out_a20 { 780 mux { 781 groups = "spdif_out_a20"; 782 function = "spdif_out"; 783 }; 784 }; 785 786 spi0_pins: spi0 { 787 mux { 788 groups = "spi0_miso", 789 "spi0_mosi", 790 "spi0_clk"; 791 function = "spi0"; 792 }; 793 }; 794 795 spi0_ss0_pins: spi0_ss0 { 796 mux { 797 groups = "spi0_ss0"; 798 function = "spi0"; 799 }; 800 }; 801 802 spi0_ss1_pins: spi0_ss1 { 803 mux { 804 groups = "spi0_ss1"; 805 function = "spi0"; 806 }; 807 }; 808 809 spi0_ss2_pins: spi0_ss2 { 810 mux { 811 groups = "spi0_ss2"; 812 function = "spi0"; 813 }; 814 }; 815 816 817 spi1_a_pins: spi1_a { 818 mux { 819 groups = "spi1_miso_a", 820 "spi1_mosi_a", 821 "spi1_clk_a"; 822 function = "spi1"; 823 }; 824 }; 825 826 spi1_ss0_a_pins: spi1_ss0_a { 827 mux { 828 groups = "spi1_ss0_a"; 829 function = "spi1"; 830 }; 831 }; 832 833 spi1_ss1_pins: spi1_ss1 { 834 mux { 835 groups = "spi1_ss1"; 836 function = "spi1"; 837 }; 838 }; 839 840 spi1_x_pins: spi1_x { 841 mux { 842 groups = "spi1_miso_x", 843 "spi1_mosi_x", 844 "spi1_clk_x"; 845 function = "spi1"; 846 }; 847 }; 848 849 spi1_ss0_x_pins: spi1_ss0_x { 850 mux { 851 groups = "spi1_ss0_x"; 852 function = "spi1"; 853 }; 854 }; 855 856 i2c0_pins: i2c0 { 857 mux { 858 groups = "i2c0_sck", 859 "i2c0_sda"; 860 function = "i2c0"; 861 }; 862 }; 863 864 i2c1_z_pins: i2c1_z { 865 mux { 866 groups = "i2c1_sck_z", 867 "i2c1_sda_z"; 868 function = "i2c1"; 869 }; 870 }; 871 872 i2c1_x_pins: i2c1_x { 873 mux { 874 groups = "i2c1_sck_x", 875 "i2c1_sda_x"; 876 function = "i2c1"; 877 }; 878 }; 879 880 i2c2_x_pins: i2c2_x { 881 mux { 882 groups = "i2c2_sck_x", 883 "i2c2_sda_x"; 884 function = "i2c2"; 885 }; 886 }; 887 888 i2c2_a_pins: i2c2_a { 889 mux { 890 groups = "i2c2_sck_a", 891 "i2c2_sda_a"; 892 function = "i2c2"; 893 }; 894 }; 895 896 i2c3_a6_pins: i2c3_a6 { 897 mux { 898 groups = "i2c3_sda_a6", 899 "i2c3_sck_a7"; 900 function = "i2c3"; 901 }; 902 }; 903 904 i2c3_a12_pins: i2c3_a12 { 905 mux { 906 groups = "i2c3_sda_a12", 907 "i2c3_sck_a13"; 908 function = "i2c3"; 909 }; 910 }; 911 912 i2c3_a19_pins: i2c3_a19 { 913 mux { 914 groups = "i2c3_sda_a19", 915 "i2c3_sck_a20"; 916 function = "i2c3"; 917 }; 918 }; 919 920 uart_a_pins: uart_a { 921 mux { 922 groups = "uart_tx_a", 923 "uart_rx_a"; 924 function = "uart_a"; 925 }; 926 }; 927 928 uart_a_cts_rts_pins: uart_a_cts_rts { 929 mux { 930 groups = "uart_cts_a", 931 "uart_rts_a"; 932 function = "uart_a"; 933 }; 934 }; 935 936 uart_b_x_pins: uart_b_x { 937 mux { 938 groups = "uart_tx_b_x", 939 "uart_rx_b_x"; 940 function = "uart_b"; 941 }; 942 }; 943 944 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 945 mux { 946 groups = "uart_cts_b_x", 947 "uart_rts_b_x"; 948 function = "uart_b"; 949 }; 950 }; 951 952 uart_b_z_pins: uart_b_z { 953 mux { 954 groups = "uart_tx_b_z", 955 "uart_rx_b_z"; 956 function = "uart_b"; 957 }; 958 }; 959 960 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 961 mux { 962 groups = "uart_cts_b_z", 963 "uart_rts_b_z"; 964 function = "uart_b"; 965 }; 966 }; 967 968 uart_ao_b_z_pins: uart_ao_b_z { 969 mux { 970 groups = "uart_ao_tx_b_z", 971 "uart_ao_rx_b_z"; 972 function = "uart_ao_b_z"; 973 }; 974 }; 975 976 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 977 mux { 978 groups = "uart_ao_cts_b_z", 979 "uart_ao_rts_b_z"; 980 function = "uart_ao_b_z"; 981 }; 982 }; 983 984 mclk_b_pins: mclk_b { 985 mux { 986 groups = "mclk_b"; 987 function = "mclk_b"; 988 }; 989 }; 990 991 mclk_c_pins: mclk_c { 992 mux { 993 groups = "mclk_c"; 994 function = "mclk_c"; 995 }; 996 }; 997 998 tdma_sclk_pins: tdma_sclk { 999 mux { 1000 groups = "tdma_sclk"; 1001 function = "tdma"; 1002 }; 1003 }; 1004 1005 tdma_sclk_slv_pins: tdma_sclk_slv { 1006 mux { 1007 groups = "tdma_sclk_slv"; 1008 function = "tdma"; 1009 }; 1010 }; 1011 1012 tdma_fs_pins: tdma_fs { 1013 mux { 1014 groups = "tdma_fs"; 1015 function = "tdma"; 1016 }; 1017 }; 1018 1019 tdma_fs_slv_pins: tdma_fs_slv { 1020 mux { 1021 groups = "tdma_fs_slv"; 1022 function = "tdma"; 1023 }; 1024 }; 1025 1026 tdma_din0_pins: tdma_din0 { 1027 mux { 1028 groups = "tdma_din0"; 1029 function = "tdma"; 1030 }; 1031 }; 1032 1033 tdma_dout0_x14_pins: tdma_dout0_x14 { 1034 mux { 1035 groups = "tdma_dout0_x14"; 1036 function = "tdma"; 1037 }; 1038 }; 1039 1040 tdma_dout0_x15_pins: tdma_dout0_x15 { 1041 mux { 1042 groups = "tdma_dout0_x15"; 1043 function = "tdma"; 1044 }; 1045 }; 1046 1047 tdma_dout1_pins: tdma_dout1 { 1048 mux { 1049 groups = "tdma_dout1"; 1050 function = "tdma"; 1051 }; 1052 }; 1053 1054 tdma_din1_pins: tdma_din1 { 1055 mux { 1056 groups = "tdma_din1"; 1057 function = "tdma"; 1058 }; 1059 }; 1060 1061 tdmb_sclk_pins: tdmb_sclk { 1062 mux { 1063 groups = "tdmb_sclk"; 1064 function = "tdmb"; 1065 }; 1066 }; 1067 1068 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1069 mux { 1070 groups = "tdmb_sclk_slv"; 1071 function = "tdmb"; 1072 }; 1073 }; 1074 1075 tdmb_fs_pins: tdmb_fs { 1076 mux { 1077 groups = "tdmb_fs"; 1078 function = "tdmb"; 1079 }; 1080 }; 1081 1082 tdmb_fs_slv_pins: tdmb_fs_slv { 1083 mux { 1084 groups = "tdmb_fs_slv"; 1085 function = "tdmb"; 1086 }; 1087 }; 1088 1089 tdmb_din0_pins: tdmb_din0 { 1090 mux { 1091 groups = "tdmb_din0"; 1092 function = "tdmb"; 1093 }; 1094 }; 1095 1096 tdmb_dout0_pins: tdmb_dout0 { 1097 mux { 1098 groups = "tdmb_dout0"; 1099 function = "tdmb"; 1100 }; 1101 }; 1102 1103 tdmb_din1_pins: tdmb_din1 { 1104 mux { 1105 groups = "tdmb_din1"; 1106 function = "tdmb"; 1107 }; 1108 }; 1109 1110 tdmb_dout1_pins: tdmb_dout1 { 1111 mux { 1112 groups = "tdmb_dout1"; 1113 function = "tdmb"; 1114 }; 1115 }; 1116 1117 tdmb_din2_pins: tdmb_din2 { 1118 mux { 1119 groups = "tdmb_din2"; 1120 function = "tdmb"; 1121 }; 1122 }; 1123 1124 tdmb_dout2_pins: tdmb_dout2 { 1125 mux { 1126 groups = "tdmb_dout2"; 1127 function = "tdmb"; 1128 }; 1129 }; 1130 1131 tdmb_din3_pins: tdmb_din3 { 1132 mux { 1133 groups = "tdmb_din3"; 1134 function = "tdmb"; 1135 }; 1136 }; 1137 1138 tdmb_dout3_pins: tdmb_dout3 { 1139 mux { 1140 groups = "tdmb_dout3"; 1141 function = "tdmb"; 1142 }; 1143 }; 1144 1145 tdmc_sclk_pins: tdmc_sclk { 1146 mux { 1147 groups = "tdmc_sclk"; 1148 function = "tdmc"; 1149 }; 1150 }; 1151 1152 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1153 mux { 1154 groups = "tdmc_sclk_slv"; 1155 function = "tdmc"; 1156 }; 1157 }; 1158 1159 tdmc_fs_pins: tdmc_fs { 1160 mux { 1161 groups = "tdmc_fs"; 1162 function = "tdmc"; 1163 }; 1164 }; 1165 1166 tdmc_fs_slv_pins: tdmc_fs_slv { 1167 mux { 1168 groups = "tdmc_fs_slv"; 1169 function = "tdmc"; 1170 }; 1171 }; 1172 1173 tdmc_din0_pins: tdmc_din0 { 1174 mux { 1175 groups = "tdmc_din0"; 1176 function = "tdmc"; 1177 }; 1178 }; 1179 1180 tdmc_dout0_pins: tdmc_dout0 { 1181 mux { 1182 groups = "tdmc_dout0"; 1183 function = "tdmc"; 1184 }; 1185 }; 1186 1187 tdmc_din1_pins: tdmc_din1 { 1188 mux { 1189 groups = "tdmc_din1"; 1190 function = "tdmc"; 1191 }; 1192 }; 1193 1194 tdmc_dout1_pins: tdmc_dout1 { 1195 mux { 1196 groups = "tdmc_dout1"; 1197 function = "tdmc"; 1198 }; 1199 }; 1200 1201 tdmc_din2_pins: tdmc_din2 { 1202 mux { 1203 groups = "tdmc_din2"; 1204 function = "tdmc"; 1205 }; 1206 }; 1207 1208 tdmc_dout2_pins: tdmc_dout2 { 1209 mux { 1210 groups = "tdmc_dout2"; 1211 function = "tdmc"; 1212 }; 1213 }; 1214 1215 tdmc_din3_pins: tdmc_din3 { 1216 mux { 1217 groups = "tdmc_din3"; 1218 function = "tdmc"; 1219 }; 1220 }; 1221 1222 tdmc_dout3_pins: tdmc_dout3 { 1223 mux { 1224 groups = "tdmc_dout3"; 1225 function = "tdmc"; 1226 }; 1227 }; 1228 }; 1229 }; 1230 1231 sram: sram@fffc0000 { 1232 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1233 reg = <0x0 0xfffc0000 0x0 0x20000>; 1234 #address-cells = <1>; 1235 #size-cells = <1>; 1236 ranges = <0 0x0 0xfffc0000 0x20000>; 1237 1238 cpu_scp_lpri: scp-shmem@0 { 1239 compatible = "amlogic,meson-axg-scp-shmem"; 1240 reg = <0x13000 0x400>; 1241 }; 1242 1243 cpu_scp_hpri: scp-shmem@200 { 1244 compatible = "amlogic,meson-axg-scp-shmem"; 1245 reg = <0x13400 0x400>; 1246 }; 1247 }; 1248 1249 aobus: bus@ff800000 { 1250 compatible = "simple-bus"; 1251 reg = <0x0 0xff800000 0x0 0x100000>; 1252 #address-cells = <2>; 1253 #size-cells = <2>; 1254 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1255 1256 sysctrl_AO: sys-ctrl@0 { 1257 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd"; 1258 reg = <0x0 0x0 0x0 0x100>; 1259 1260 clkc_AO: clock-controller { 1261 compatible = "amlogic,meson-axg-aoclkc"; 1262 #clock-cells = <1>; 1263 #reset-cells = <1>; 1264 }; 1265 }; 1266 1267 pinctrl_aobus: pinctrl@14 { 1268 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1269 #address-cells = <2>; 1270 #size-cells = <2>; 1271 ranges; 1272 1273 gpio_ao: bank@14 { 1274 reg = <0x0 0x00014 0x0 0x8>, 1275 <0x0 0x0002c 0x0 0x4>, 1276 <0x0 0x00024 0x0 0x8>; 1277 reg-names = "mux", "pull", "gpio"; 1278 gpio-controller; 1279 #gpio-cells = <2>; 1280 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1281 }; 1282 1283 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1284 mux { 1285 groups = "i2c_ao_sck_4"; 1286 function = "i2c_ao"; 1287 }; 1288 }; 1289 1290 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1291 mux { 1292 groups = "i2c_ao_sck_8"; 1293 function = "i2c_ao"; 1294 }; 1295 }; 1296 1297 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1298 mux { 1299 groups = "i2c_ao_sck_10"; 1300 function = "i2c_ao"; 1301 }; 1302 }; 1303 1304 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1305 mux { 1306 groups = "i2c_ao_sda_5"; 1307 function = "i2c_ao"; 1308 }; 1309 }; 1310 1311 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1312 mux { 1313 groups = "i2c_ao_sda_9"; 1314 function = "i2c_ao"; 1315 }; 1316 }; 1317 1318 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1319 mux { 1320 groups = "i2c_ao_sda_11"; 1321 function = "i2c_ao"; 1322 }; 1323 }; 1324 1325 remote_input_ao_pins: remote_input_ao { 1326 mux { 1327 groups = "remote_input_ao"; 1328 function = "remote_input_ao"; 1329 }; 1330 }; 1331 1332 uart_ao_a_pins: uart_ao_a { 1333 mux { 1334 groups = "uart_ao_tx_a", 1335 "uart_ao_rx_a"; 1336 function = "uart_ao_a"; 1337 }; 1338 }; 1339 1340 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1341 mux { 1342 groups = "uart_ao_cts_a", 1343 "uart_ao_rts_a"; 1344 function = "uart_ao_a"; 1345 }; 1346 }; 1347 1348 uart_ao_b_pins: uart_ao_b { 1349 mux { 1350 groups = "uart_ao_tx_b", 1351 "uart_ao_rx_b"; 1352 function = "uart_ao_b"; 1353 }; 1354 }; 1355 1356 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1357 mux { 1358 groups = "uart_ao_cts_b", 1359 "uart_ao_rts_b"; 1360 function = "uart_ao_b"; 1361 }; 1362 }; 1363 }; 1364 1365 sec_AO: ao-secure@140 { 1366 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1367 reg = <0x0 0x140 0x0 0x140>; 1368 amlogic,has-chip-id; 1369 }; 1370 1371 pwm_AO_ab: pwm@7000 { 1372 compatible = "amlogic,meson-axg-ao-pwm"; 1373 reg = <0x0 0x07000 0x0 0x20>; 1374 #pwm-cells = <3>; 1375 status = "disabled"; 1376 }; 1377 1378 pwm_AO_cd: pwm@2000 { 1379 compatible = "amlogic,meson-axg-ao-pwm"; 1380 reg = <0x0 0x02000 0x0 0x20>; 1381 #pwm-cells = <3>; 1382 status = "disabled"; 1383 }; 1384 1385 i2c_AO: i2c@5000 { 1386 compatible = "amlogic,meson-axg-i2c"; 1387 reg = <0x0 0x05000 0x0 0x20>; 1388 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1389 clocks = <&clkc CLKID_AO_I2C>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 uart_AO: serial@3000 { 1396 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1397 reg = <0x0 0x3000 0x0 0x18>; 1398 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1399 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1400 clock-names = "xtal", "pclk", "baud"; 1401 status = "disabled"; 1402 }; 1403 1404 uart_AO_B: serial@4000 { 1405 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1406 reg = <0x0 0x4000 0x0 0x18>; 1407 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1408 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1409 clock-names = "xtal", "pclk", "baud"; 1410 status = "disabled"; 1411 }; 1412 1413 ir: ir@8000 { 1414 compatible = "amlogic,meson-gxbb-ir"; 1415 reg = <0x0 0x8000 0x0 0x20>; 1416 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1417 status = "disabled"; 1418 }; 1419 1420 saradc: adc@9000 { 1421 compatible = "amlogic,meson-axg-saradc", 1422 "amlogic,meson-saradc"; 1423 reg = <0x0 0x9000 0x0 0x38>; 1424 #io-channel-cells = <1>; 1425 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1426 clocks = <&xtal>, 1427 <&clkc_AO CLKID_AO_SAR_ADC>, 1428 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1429 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1430 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1431 status = "disabled"; 1432 }; 1433 }; 1434 }; 1435}; 1436