1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 reserved-memory { 128 #address-cells = <2>; 129 #size-cells = <2>; 130 ranges; 131 132 /* 16 MiB reserved for Hardware ROM Firmware */ 133 hwrom_reserved: hwrom@0 { 134 reg = <0x0 0x0 0x0 0x1000000>; 135 no-map; 136 }; 137 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 139 secmon_reserved: secmon@5000000 { 140 reg = <0x0 0x05000000 0x0 0x300000>; 141 no-map; 142 }; 143 }; 144 145 scpi { 146 compatible = "arm,scpi-pre-1.0"; 147 mboxes = <&mailbox 1 &mailbox 2>; 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 149 150 scpi_clocks: clocks { 151 compatible = "arm,scpi-clocks"; 152 153 scpi_dvfs: clock-controller { 154 compatible = "arm,scpi-dvfs-clocks"; 155 #clock-cells = <1>; 156 clock-indices = <0>; 157 clock-output-names = "vcpu"; 158 }; 159 }; 160 161 scpi_sensors: sensors { 162 compatible = "amlogic,meson-gxbb-scpi-sensors"; 163 #thermal-sensor-cells = <1>; 164 }; 165 }; 166 167 soc { 168 compatible = "simple-bus"; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 ethmac: ethernet@ff3f0000 { 174 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 175 reg = <0x0 0xff3f0000 0x0 0x10000 176 0x0 0xff634540 0x0 0x8>; 177 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "macirq"; 179 clocks = <&clkc CLKID_ETH>, 180 <&clkc CLKID_FCLK_DIV2>, 181 <&clkc CLKID_MPLL2>; 182 clock-names = "stmmaceth", "clkin0", "clkin1"; 183 status = "disabled"; 184 }; 185 186 pdm: audio-controller@ff632000 { 187 compatible = "amlogic,axg-pdm"; 188 reg = <0x0 0xff632000 0x0 0x34>; 189 #sound-dai-cells = <0>; 190 sound-name-prefix = "PDM"; 191 clocks = <&clkc_audio AUD_CLKID_PDM>, 192 <&clkc_audio AUD_CLKID_PDM_DCLK>, 193 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 194 clock-names = "pclk", "dclk", "sysclk"; 195 status = "disabled"; 196 }; 197 198 periphs: bus@ff634000 { 199 compatible = "simple-bus"; 200 reg = <0x0 0xff634000 0x0 0x2000>; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 204 205 hwrng: rng@18 { 206 compatible = "amlogic,meson-rng"; 207 reg = <0x0 0x18 0x0 0x4>; 208 clocks = <&clkc CLKID_RNG0>; 209 clock-names = "core"; 210 }; 211 212 pinctrl_periphs: pinctrl@480 { 213 compatible = "amlogic,meson-axg-periphs-pinctrl"; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 ranges; 217 218 gpio: bank@480 { 219 reg = <0x0 0x00480 0x0 0x40>, 220 <0x0 0x004e8 0x0 0x14>, 221 <0x0 0x00520 0x0 0x14>, 222 <0x0 0x00430 0x0 0x3c>; 223 reg-names = "mux", "pull", "pull-enable", "gpio"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&pinctrl_periphs 0 0 86>; 227 }; 228 229 i2c0_pins: i2c0 { 230 mux { 231 groups = "i2c0_sck", 232 "i2c0_sda"; 233 function = "i2c0"; 234 bias-disable; 235 }; 236 }; 237 238 i2c1_x_pins: i2c1_x { 239 mux { 240 groups = "i2c1_sck_x", 241 "i2c1_sda_x"; 242 function = "i2c1"; 243 bias-disable; 244 }; 245 }; 246 247 i2c1_z_pins: i2c1_z { 248 mux { 249 groups = "i2c1_sck_z", 250 "i2c1_sda_z"; 251 function = "i2c1"; 252 bias-disable; 253 }; 254 }; 255 256 i2c2_a_pins: i2c2_a { 257 mux { 258 groups = "i2c2_sck_a", 259 "i2c2_sda_a"; 260 function = "i2c2"; 261 bias-disable; 262 }; 263 }; 264 265 i2c2_x_pins: i2c2_x { 266 mux { 267 groups = "i2c2_sck_x", 268 "i2c2_sda_x"; 269 function = "i2c2"; 270 bias-disable; 271 }; 272 }; 273 274 i2c3_a6_pins: i2c3_a6 { 275 mux { 276 groups = "i2c3_sda_a6", 277 "i2c3_sck_a7"; 278 function = "i2c3"; 279 bias-disable; 280 }; 281 }; 282 283 i2c3_a12_pins: i2c3_a12 { 284 mux { 285 groups = "i2c3_sda_a12", 286 "i2c3_sck_a13"; 287 function = "i2c3"; 288 bias-disable; 289 }; 290 }; 291 292 i2c3_a19_pins: i2c3_a19 { 293 mux { 294 groups = "i2c3_sda_a19", 295 "i2c3_sck_a20"; 296 function = "i2c3"; 297 bias-disable; 298 }; 299 }; 300 301 emmc_pins: emmc { 302 mux-0 { 303 groups = "emmc_nand_d0", 304 "emmc_nand_d1", 305 "emmc_nand_d2", 306 "emmc_nand_d3", 307 "emmc_nand_d4", 308 "emmc_nand_d5", 309 "emmc_nand_d6", 310 "emmc_nand_d7", 311 "emmc_cmd"; 312 function = "emmc"; 313 bias-pull-up; 314 }; 315 316 mux-1 { 317 groups = "emmc_clk"; 318 function = "emmc"; 319 bias-disable; 320 }; 321 }; 322 323 emmc_ds_pins: emmc_ds { 324 mux { 325 groups = "emmc_ds"; 326 function = "emmc"; 327 bias-pull-down; 328 }; 329 }; 330 331 emmc_clk_gate_pins: emmc_clk_gate { 332 mux { 333 groups = "BOOT_8"; 334 function = "gpio_periphs"; 335 bias-pull-down; 336 }; 337 }; 338 339 eth_rgmii_x_pins: eth-x-rgmii { 340 mux { 341 groups = "eth_mdio_x", 342 "eth_mdc_x", 343 "eth_rgmii_rx_clk_x", 344 "eth_rx_dv_x", 345 "eth_rxd0_x", 346 "eth_rxd1_x", 347 "eth_rxd2_rgmii", 348 "eth_rxd3_rgmii", 349 "eth_rgmii_tx_clk", 350 "eth_txen_x", 351 "eth_txd0_x", 352 "eth_txd1_x", 353 "eth_txd2_rgmii", 354 "eth_txd3_rgmii"; 355 function = "eth"; 356 bias-disable; 357 }; 358 }; 359 360 eth_rgmii_y_pins: eth-y-rgmii { 361 mux { 362 groups = "eth_mdio_y", 363 "eth_mdc_y", 364 "eth_rgmii_rx_clk_y", 365 "eth_rx_dv_y", 366 "eth_rxd0_y", 367 "eth_rxd1_y", 368 "eth_rxd2_rgmii", 369 "eth_rxd3_rgmii", 370 "eth_rgmii_tx_clk", 371 "eth_txen_y", 372 "eth_txd0_y", 373 "eth_txd1_y", 374 "eth_txd2_rgmii", 375 "eth_txd3_rgmii"; 376 function = "eth"; 377 bias-disable; 378 }; 379 }; 380 381 eth_rmii_x_pins: eth-x-rmii { 382 mux { 383 groups = "eth_mdio_x", 384 "eth_mdc_x", 385 "eth_rgmii_rx_clk_x", 386 "eth_rx_dv_x", 387 "eth_rxd0_x", 388 "eth_rxd1_x", 389 "eth_txen_x", 390 "eth_txd0_x", 391 "eth_txd1_x"; 392 function = "eth"; 393 bias-disable; 394 }; 395 }; 396 397 eth_rmii_y_pins: eth-y-rmii { 398 mux { 399 groups = "eth_mdio_y", 400 "eth_mdc_y", 401 "eth_rgmii_rx_clk_y", 402 "eth_rx_dv_y", 403 "eth_rxd0_y", 404 "eth_rxd1_y", 405 "eth_txen_y", 406 "eth_txd0_y", 407 "eth_txd1_y"; 408 function = "eth"; 409 bias-disable; 410 }; 411 }; 412 413 mclk_b_pins: mclk_b { 414 mux { 415 groups = "mclk_b"; 416 function = "mclk_b"; 417 bias-disable; 418 }; 419 }; 420 421 mclk_c_pins: mclk_c { 422 mux { 423 groups = "mclk_c"; 424 function = "mclk_c"; 425 bias-disable; 426 }; 427 }; 428 429 pdm_dclk_a14_pins: pdm_dclk_a14 { 430 mux { 431 groups = "pdm_dclk_a14"; 432 function = "pdm"; 433 bias-disable; 434 }; 435 }; 436 437 pdm_dclk_a19_pins: pdm_dclk_a19 { 438 mux { 439 groups = "pdm_dclk_a19"; 440 function = "pdm"; 441 bias-disable; 442 }; 443 }; 444 445 pdm_din0_pins: pdm_din0 { 446 mux { 447 groups = "pdm_din0"; 448 function = "pdm"; 449 bias-disable; 450 }; 451 }; 452 453 pdm_din1_pins: pdm_din1 { 454 mux { 455 groups = "pdm_din1"; 456 function = "pdm"; 457 bias-disable; 458 }; 459 }; 460 461 pdm_din2_pins: pdm_din2 { 462 mux { 463 groups = "pdm_din2"; 464 function = "pdm"; 465 bias-disable; 466 }; 467 }; 468 469 pdm_din3_pins: pdm_din3 { 470 mux { 471 groups = "pdm_din3"; 472 function = "pdm"; 473 bias-disable; 474 }; 475 }; 476 477 pwm_a_a_pins: pwm_a_a { 478 mux { 479 groups = "pwm_a_a"; 480 function = "pwm_a"; 481 bias-disable; 482 }; 483 }; 484 485 pwm_a_x18_pins: pwm_a_x18 { 486 mux { 487 groups = "pwm_a_x18"; 488 function = "pwm_a"; 489 bias-disable; 490 }; 491 }; 492 493 pwm_a_x20_pins: pwm_a_x20 { 494 mux { 495 groups = "pwm_a_x20"; 496 function = "pwm_a"; 497 bias-disable; 498 }; 499 }; 500 501 pwm_a_z_pins: pwm_a_z { 502 mux { 503 groups = "pwm_a_z"; 504 function = "pwm_a"; 505 bias-disable; 506 }; 507 }; 508 509 pwm_b_a_pins: pwm_b_a { 510 mux { 511 groups = "pwm_b_a"; 512 function = "pwm_b"; 513 bias-disable; 514 }; 515 }; 516 517 pwm_b_x_pins: pwm_b_x { 518 mux { 519 groups = "pwm_b_x"; 520 function = "pwm_b"; 521 bias-disable; 522 }; 523 }; 524 525 pwm_b_z_pins: pwm_b_z { 526 mux { 527 groups = "pwm_b_z"; 528 function = "pwm_b"; 529 bias-disable; 530 }; 531 }; 532 533 pwm_c_a_pins: pwm_c_a { 534 mux { 535 groups = "pwm_c_a"; 536 function = "pwm_c"; 537 bias-disable; 538 }; 539 }; 540 541 pwm_c_x10_pins: pwm_c_x10 { 542 mux { 543 groups = "pwm_c_x10"; 544 function = "pwm_c"; 545 bias-disable; 546 }; 547 }; 548 549 pwm_c_x17_pins: pwm_c_x17 { 550 mux { 551 groups = "pwm_c_x17"; 552 function = "pwm_c"; 553 bias-disable; 554 }; 555 }; 556 557 pwm_d_x11_pins: pwm_d_x11 { 558 mux { 559 groups = "pwm_d_x11"; 560 function = "pwm_d"; 561 bias-disable; 562 }; 563 }; 564 565 pwm_d_x16_pins: pwm_d_x16 { 566 mux { 567 groups = "pwm_d_x16"; 568 function = "pwm_d"; 569 bias-disable; 570 }; 571 }; 572 573 sdio_pins: sdio { 574 mux-0 { 575 groups = "sdio_d0", 576 "sdio_d1", 577 "sdio_d2", 578 "sdio_d3", 579 "sdio_cmd"; 580 function = "sdio"; 581 bias-pull-up; 582 }; 583 584 mux-1 { 585 groups = "sdio_clk"; 586 function = "sdio"; 587 bias-disable; 588 }; 589 }; 590 591 sdio_clk_gate_pins: sdio_clk_gate { 592 mux { 593 groups = "GPIOX_4"; 594 function = "gpio_periphs"; 595 bias-pull-down; 596 }; 597 }; 598 599 spdif_in_z_pins: spdif_in_z { 600 mux { 601 groups = "spdif_in_z"; 602 function = "spdif_in"; 603 bias-disable; 604 }; 605 }; 606 607 spdif_in_a1_pins: spdif_in_a1 { 608 mux { 609 groups = "spdif_in_a1"; 610 function = "spdif_in"; 611 bias-disable; 612 }; 613 }; 614 615 spdif_in_a7_pins: spdif_in_a7 { 616 mux { 617 groups = "spdif_in_a7"; 618 function = "spdif_in"; 619 bias-disable; 620 }; 621 }; 622 623 spdif_in_a19_pins: spdif_in_a19 { 624 mux { 625 groups = "spdif_in_a19"; 626 function = "spdif_in"; 627 bias-disable; 628 }; 629 }; 630 631 spdif_in_a20_pins: spdif_in_a20 { 632 mux { 633 groups = "spdif_in_a20"; 634 function = "spdif_in"; 635 bias-disable; 636 }; 637 }; 638 639 spdif_out_a1_pins: spdif_out_a1 { 640 mux { 641 groups = "spdif_out_a1"; 642 function = "spdif_out"; 643 bias-disable; 644 }; 645 }; 646 647 spdif_out_a11_pins: spdif_out_a11 { 648 mux { 649 groups = "spdif_out_a11"; 650 function = "spdif_out"; 651 bias-disable; 652 }; 653 }; 654 655 spdif_out_a19_pins: spdif_out_a19 { 656 mux { 657 groups = "spdif_out_a19"; 658 function = "spdif_out"; 659 bias-disable; 660 }; 661 }; 662 663 spdif_out_a20_pins: spdif_out_a20 { 664 mux { 665 groups = "spdif_out_a20"; 666 function = "spdif_out"; 667 bias-disable; 668 }; 669 }; 670 671 spdif_out_z_pins: spdif_out_z { 672 mux { 673 groups = "spdif_out_z"; 674 function = "spdif_out"; 675 bias-disable; 676 }; 677 }; 678 679 spi0_pins: spi0 { 680 mux { 681 groups = "spi0_miso", 682 "spi0_mosi", 683 "spi0_clk"; 684 function = "spi0"; 685 bias-disable; 686 }; 687 }; 688 689 spi0_ss0_pins: spi0_ss0 { 690 mux { 691 groups = "spi0_ss0"; 692 function = "spi0"; 693 bias-disable; 694 }; 695 }; 696 697 spi0_ss1_pins: spi0_ss1 { 698 mux { 699 groups = "spi0_ss1"; 700 function = "spi0"; 701 bias-disable; 702 }; 703 }; 704 705 spi0_ss2_pins: spi0_ss2 { 706 mux { 707 groups = "spi0_ss2"; 708 function = "spi0"; 709 bias-disable; 710 }; 711 }; 712 713 spi1_a_pins: spi1_a { 714 mux { 715 groups = "spi1_miso_a", 716 "spi1_mosi_a", 717 "spi1_clk_a"; 718 function = "spi1"; 719 bias-disable; 720 }; 721 }; 722 723 spi1_ss0_a_pins: spi1_ss0_a { 724 mux { 725 groups = "spi1_ss0_a"; 726 function = "spi1"; 727 bias-disable; 728 }; 729 }; 730 731 spi1_ss1_pins: spi1_ss1 { 732 mux { 733 groups = "spi1_ss1"; 734 function = "spi1"; 735 bias-disable; 736 }; 737 }; 738 739 spi1_x_pins: spi1_x { 740 mux { 741 groups = "spi1_miso_x", 742 "spi1_mosi_x", 743 "spi1_clk_x"; 744 function = "spi1"; 745 bias-disable; 746 }; 747 }; 748 749 spi1_ss0_x_pins: spi1_ss0_x { 750 mux { 751 groups = "spi1_ss0_x"; 752 function = "spi1"; 753 bias-disable; 754 }; 755 }; 756 757 tdma_din0_pins: tdma_din0 { 758 mux { 759 groups = "tdma_din0"; 760 function = "tdma"; 761 bias-disable; 762 }; 763 }; 764 765 tdma_dout0_x14_pins: tdma_dout0_x14 { 766 mux { 767 groups = "tdma_dout0_x14"; 768 function = "tdma"; 769 bias-disable; 770 }; 771 }; 772 773 tdma_dout0_x15_pins: tdma_dout0_x15 { 774 mux { 775 groups = "tdma_dout0_x15"; 776 function = "tdma"; 777 bias-disable; 778 }; 779 }; 780 781 tdma_dout1_pins: tdma_dout1 { 782 mux { 783 groups = "tdma_dout1"; 784 function = "tdma"; 785 bias-disable; 786 }; 787 }; 788 789 tdma_din1_pins: tdma_din1 { 790 mux { 791 groups = "tdma_din1"; 792 function = "tdma"; 793 bias-disable; 794 }; 795 }; 796 797 tdma_fs_pins: tdma_fs { 798 mux { 799 groups = "tdma_fs"; 800 function = "tdma"; 801 bias-disable; 802 }; 803 }; 804 805 tdma_fs_slv_pins: tdma_fs_slv { 806 mux { 807 groups = "tdma_fs_slv"; 808 function = "tdma"; 809 bias-disable; 810 }; 811 }; 812 813 tdma_sclk_pins: tdma_sclk { 814 mux { 815 groups = "tdma_sclk"; 816 function = "tdma"; 817 bias-disable; 818 }; 819 }; 820 821 tdma_sclk_slv_pins: tdma_sclk_slv { 822 mux { 823 groups = "tdma_sclk_slv"; 824 function = "tdma"; 825 bias-disable; 826 }; 827 }; 828 829 tdmb_din0_pins: tdmb_din0 { 830 mux { 831 groups = "tdmb_din0"; 832 function = "tdmb"; 833 bias-disable; 834 }; 835 }; 836 837 tdmb_din1_pins: tdmb_din1 { 838 mux { 839 groups = "tdmb_din1"; 840 function = "tdmb"; 841 bias-disable; 842 }; 843 }; 844 845 tdmb_din2_pins: tdmb_din2 { 846 mux { 847 groups = "tdmb_din2"; 848 function = "tdmb"; 849 bias-disable; 850 }; 851 }; 852 853 tdmb_din3_pins: tdmb_din3 { 854 mux { 855 groups = "tdmb_din3"; 856 function = "tdmb"; 857 bias-disable; 858 }; 859 }; 860 861 tdmb_dout0_pins: tdmb_dout0 { 862 mux { 863 groups = "tdmb_dout0"; 864 function = "tdmb"; 865 bias-disable; 866 }; 867 }; 868 869 tdmb_dout1_pins: tdmb_dout1 { 870 mux { 871 groups = "tdmb_dout1"; 872 function = "tdmb"; 873 bias-disable; 874 }; 875 }; 876 877 tdmb_dout2_pins: tdmb_dout2 { 878 mux { 879 groups = "tdmb_dout2"; 880 function = "tdmb"; 881 bias-disable; 882 }; 883 }; 884 885 tdmb_dout3_pins: tdmb_dout3 { 886 mux { 887 groups = "tdmb_dout3"; 888 function = "tdmb"; 889 bias-disable; 890 }; 891 }; 892 893 tdmb_fs_pins: tdmb_fs { 894 mux { 895 groups = "tdmb_fs"; 896 function = "tdmb"; 897 bias-disable; 898 }; 899 }; 900 901 tdmb_fs_slv_pins: tdmb_fs_slv { 902 mux { 903 groups = "tdmb_fs_slv"; 904 function = "tdmb"; 905 bias-disable; 906 }; 907 }; 908 909 tdmb_sclk_pins: tdmb_sclk { 910 mux { 911 groups = "tdmb_sclk"; 912 function = "tdmb"; 913 bias-disable; 914 }; 915 }; 916 917 tdmb_sclk_slv_pins: tdmb_sclk_slv { 918 mux { 919 groups = "tdmb_sclk_slv"; 920 function = "tdmb"; 921 bias-disable; 922 }; 923 }; 924 925 tdmc_fs_pins: tdmc_fs { 926 mux { 927 groups = "tdmc_fs"; 928 function = "tdmc"; 929 bias-disable; 930 }; 931 }; 932 933 tdmc_fs_slv_pins: tdmc_fs_slv { 934 mux { 935 groups = "tdmc_fs_slv"; 936 function = "tdmc"; 937 bias-disable; 938 }; 939 }; 940 941 tdmc_sclk_pins: tdmc_sclk { 942 mux { 943 groups = "tdmc_sclk"; 944 function = "tdmc"; 945 bias-disable; 946 }; 947 }; 948 949 tdmc_sclk_slv_pins: tdmc_sclk_slv { 950 mux { 951 groups = "tdmc_sclk_slv"; 952 function = "tdmc"; 953 bias-disable; 954 }; 955 }; 956 957 tdmc_din0_pins: tdmc_din0 { 958 mux { 959 groups = "tdmc_din0"; 960 function = "tdmc"; 961 bias-disable; 962 }; 963 }; 964 965 tdmc_din1_pins: tdmc_din1 { 966 mux { 967 groups = "tdmc_din1"; 968 function = "tdmc"; 969 bias-disable; 970 }; 971 }; 972 973 tdmc_din2_pins: tdmc_din2 { 974 mux { 975 groups = "tdmc_din2"; 976 function = "tdmc"; 977 bias-disable; 978 }; 979 }; 980 981 tdmc_din3_pins: tdmc_din3 { 982 mux { 983 groups = "tdmc_din3"; 984 function = "tdmc"; 985 bias-disable; 986 }; 987 }; 988 989 tdmc_dout0_pins: tdmc_dout0 { 990 mux { 991 groups = "tdmc_dout0"; 992 function = "tdmc"; 993 bias-disable; 994 }; 995 }; 996 997 tdmc_dout1_pins: tdmc_dout1 { 998 mux { 999 groups = "tdmc_dout1"; 1000 function = "tdmc"; 1001 bias-disable; 1002 }; 1003 }; 1004 1005 tdmc_dout2_pins: tdmc_dout2 { 1006 mux { 1007 groups = "tdmc_dout2"; 1008 function = "tdmc"; 1009 bias-disable; 1010 }; 1011 }; 1012 1013 tdmc_dout3_pins: tdmc_dout3 { 1014 mux { 1015 groups = "tdmc_dout3"; 1016 function = "tdmc"; 1017 bias-disable; 1018 }; 1019 }; 1020 1021 uart_a_pins: uart_a { 1022 mux { 1023 groups = "uart_tx_a", 1024 "uart_rx_a"; 1025 function = "uart_a"; 1026 bias-disable; 1027 }; 1028 }; 1029 1030 uart_a_cts_rts_pins: uart_a_cts_rts { 1031 mux { 1032 groups = "uart_cts_a", 1033 "uart_rts_a"; 1034 function = "uart_a"; 1035 bias-disable; 1036 }; 1037 }; 1038 1039 uart_b_x_pins: uart_b_x { 1040 mux { 1041 groups = "uart_tx_b_x", 1042 "uart_rx_b_x"; 1043 function = "uart_b"; 1044 bias-disable; 1045 }; 1046 }; 1047 1048 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1049 mux { 1050 groups = "uart_cts_b_x", 1051 "uart_rts_b_x"; 1052 function = "uart_b"; 1053 bias-disable; 1054 }; 1055 }; 1056 1057 uart_b_z_pins: uart_b_z { 1058 mux { 1059 groups = "uart_tx_b_z", 1060 "uart_rx_b_z"; 1061 function = "uart_b"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1067 mux { 1068 groups = "uart_cts_b_z", 1069 "uart_rts_b_z"; 1070 function = "uart_b"; 1071 bias-disable; 1072 }; 1073 }; 1074 1075 uart_ao_b_z_pins: uart_ao_b_z { 1076 mux { 1077 groups = "uart_ao_tx_b_z", 1078 "uart_ao_rx_b_z"; 1079 function = "uart_ao_b_z"; 1080 bias-disable; 1081 }; 1082 }; 1083 1084 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1085 mux { 1086 groups = "uart_ao_cts_b_z", 1087 "uart_ao_rts_b_z"; 1088 function = "uart_ao_b_z"; 1089 bias-disable; 1090 }; 1091 }; 1092 }; 1093 }; 1094 1095 hiubus: bus@ff63c000 { 1096 compatible = "simple-bus"; 1097 reg = <0x0 0xff63c000 0x0 0x1c00>; 1098 #address-cells = <2>; 1099 #size-cells = <2>; 1100 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1101 1102 sysctrl: system-controller@0 { 1103 compatible = "amlogic,meson-axg-hhi-sysctrl", 1104 "simple-mfd", "syscon"; 1105 reg = <0 0 0 0x400>; 1106 1107 clkc: clock-controller { 1108 compatible = "amlogic,axg-clkc"; 1109 #clock-cells = <1>; 1110 clocks = <&xtal>; 1111 clock-names = "xtal"; 1112 }; 1113 }; 1114 }; 1115 1116 mailbox: mailbox@ff63c404 { 1117 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1118 reg = <0 0xff63c404 0 0x4c>; 1119 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1120 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1121 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1122 #mbox-cells = <1>; 1123 }; 1124 1125 audio: bus@ff642000 { 1126 compatible = "simple-bus"; 1127 reg = <0x0 0xff642000 0x0 0x2000>; 1128 #address-cells = <2>; 1129 #size-cells = <2>; 1130 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1131 1132 clkc_audio: clock-controller@0 { 1133 compatible = "amlogic,axg-audio-clkc"; 1134 reg = <0x0 0x0 0x0 0xb4>; 1135 #clock-cells = <1>; 1136 1137 clocks = <&clkc CLKID_AUDIO>, 1138 <&clkc CLKID_MPLL0>, 1139 <&clkc CLKID_MPLL1>, 1140 <&clkc CLKID_MPLL2>, 1141 <&clkc CLKID_MPLL3>, 1142 <&clkc CLKID_HIFI_PLL>, 1143 <&clkc CLKID_FCLK_DIV3>, 1144 <&clkc CLKID_FCLK_DIV4>, 1145 <&clkc CLKID_GP0_PLL>; 1146 clock-names = "pclk", 1147 "mst_in0", 1148 "mst_in1", 1149 "mst_in2", 1150 "mst_in3", 1151 "mst_in4", 1152 "mst_in5", 1153 "mst_in6", 1154 "mst_in7"; 1155 1156 resets = <&reset RESET_AUDIO>; 1157 }; 1158 1159 toddr_a: audio-controller@100 { 1160 compatible = "amlogic,axg-toddr"; 1161 reg = <0x0 0x100 0x0 0x1c>; 1162 #sound-dai-cells = <0>; 1163 sound-name-prefix = "TODDR_A"; 1164 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1165 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1166 resets = <&arb AXG_ARB_TODDR_A>; 1167 status = "disabled"; 1168 }; 1169 1170 toddr_b: audio-controller@140 { 1171 compatible = "amlogic,axg-toddr"; 1172 reg = <0x0 0x140 0x0 0x1c>; 1173 #sound-dai-cells = <0>; 1174 sound-name-prefix = "TODDR_B"; 1175 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1176 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1177 resets = <&arb AXG_ARB_TODDR_B>; 1178 status = "disabled"; 1179 }; 1180 1181 toddr_c: audio-controller@180 { 1182 compatible = "amlogic,axg-toddr"; 1183 reg = <0x0 0x180 0x0 0x1c>; 1184 #sound-dai-cells = <0>; 1185 sound-name-prefix = "TODDR_C"; 1186 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1187 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1188 resets = <&arb AXG_ARB_TODDR_C>; 1189 status = "disabled"; 1190 }; 1191 1192 frddr_a: audio-controller@1c0 { 1193 compatible = "amlogic,axg-frddr"; 1194 reg = <0x0 0x1c0 0x0 0x1c>; 1195 #sound-dai-cells = <0>; 1196 sound-name-prefix = "FRDDR_A"; 1197 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1198 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1199 resets = <&arb AXG_ARB_FRDDR_A>; 1200 status = "disabled"; 1201 }; 1202 1203 frddr_b: audio-controller@200 { 1204 compatible = "amlogic,axg-frddr"; 1205 reg = <0x0 0x200 0x0 0x1c>; 1206 #sound-dai-cells = <0>; 1207 sound-name-prefix = "FRDDR_B"; 1208 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1209 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1210 resets = <&arb AXG_ARB_FRDDR_B>; 1211 status = "disabled"; 1212 }; 1213 1214 frddr_c: audio-controller@240 { 1215 compatible = "amlogic,axg-frddr"; 1216 reg = <0x0 0x240 0x0 0x1c>; 1217 #sound-dai-cells = <0>; 1218 sound-name-prefix = "FRDDR_C"; 1219 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1220 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1221 resets = <&arb AXG_ARB_FRDDR_C>; 1222 status = "disabled"; 1223 }; 1224 1225 arb: reset-controller@280 { 1226 compatible = "amlogic,meson-axg-audio-arb"; 1227 reg = <0x0 0x280 0x0 0x4>; 1228 #reset-cells = <1>; 1229 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1230 }; 1231 1232 tdmin_a: audio-controller@300 { 1233 compatible = "amlogic,axg-tdmin"; 1234 reg = <0x0 0x300 0x0 0x40>; 1235 sound-name-prefix = "TDMIN_A"; 1236 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1237 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1238 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1239 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1240 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1241 clock-names = "pclk", "sclk", "sclk_sel", 1242 "lrclk", "lrclk_sel"; 1243 status = "disabled"; 1244 }; 1245 1246 tdmin_b: audio-controller@340 { 1247 compatible = "amlogic,axg-tdmin"; 1248 reg = <0x0 0x340 0x0 0x40>; 1249 sound-name-prefix = "TDMIN_B"; 1250 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1251 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1252 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1253 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1254 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1255 clock-names = "pclk", "sclk", "sclk_sel", 1256 "lrclk", "lrclk_sel"; 1257 status = "disabled"; 1258 }; 1259 1260 tdmin_c: audio-controller@380 { 1261 compatible = "amlogic,axg-tdmin"; 1262 reg = <0x0 0x380 0x0 0x40>; 1263 sound-name-prefix = "TDMIN_C"; 1264 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1265 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1266 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1267 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1268 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1269 clock-names = "pclk", "sclk", "sclk_sel", 1270 "lrclk", "lrclk_sel"; 1271 status = "disabled"; 1272 }; 1273 1274 tdmin_lb: audio-controller@3c0 { 1275 compatible = "amlogic,axg-tdmin"; 1276 reg = <0x0 0x3c0 0x0 0x40>; 1277 sound-name-prefix = "TDMIN_LB"; 1278 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1279 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1280 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1281 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1282 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1283 clock-names = "pclk", "sclk", "sclk_sel", 1284 "lrclk", "lrclk_sel"; 1285 status = "disabled"; 1286 }; 1287 1288 spdifin: audio-controller@400 { 1289 compatible = "amlogic,axg-spdifin"; 1290 reg = <0x0 0x400 0x0 0x30>; 1291 #sound-dai-cells = <0>; 1292 sound-name-prefix = "SPDIFIN"; 1293 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1294 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1295 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1296 clock-names = "pclk", "refclk"; 1297 status = "disabled"; 1298 }; 1299 1300 spdifout: audio-controller@480 { 1301 compatible = "amlogic,axg-spdifout"; 1302 reg = <0x0 0x480 0x0 0x50>; 1303 #sound-dai-cells = <0>; 1304 sound-name-prefix = "SPDIFOUT"; 1305 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1306 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1307 clock-names = "pclk", "mclk"; 1308 status = "disabled"; 1309 }; 1310 1311 tdmout_a: audio-controller@500 { 1312 compatible = "amlogic,axg-tdmout"; 1313 reg = <0x0 0x500 0x0 0x40>; 1314 sound-name-prefix = "TDMOUT_A"; 1315 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1316 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1317 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1318 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1319 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1320 clock-names = "pclk", "sclk", "sclk_sel", 1321 "lrclk", "lrclk_sel"; 1322 status = "disabled"; 1323 }; 1324 1325 tdmout_b: audio-controller@540 { 1326 compatible = "amlogic,axg-tdmout"; 1327 reg = <0x0 0x540 0x0 0x40>; 1328 sound-name-prefix = "TDMOUT_B"; 1329 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1330 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1331 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1332 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1333 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1334 clock-names = "pclk", "sclk", "sclk_sel", 1335 "lrclk", "lrclk_sel"; 1336 status = "disabled"; 1337 }; 1338 1339 tdmout_c: audio-controller@580 { 1340 compatible = "amlogic,axg-tdmout"; 1341 reg = <0x0 0x580 0x0 0x40>; 1342 sound-name-prefix = "TDMOUT_C"; 1343 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1344 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1345 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1346 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1347 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1348 clock-names = "pclk", "sclk", "sclk_sel", 1349 "lrclk", "lrclk_sel"; 1350 status = "disabled"; 1351 }; 1352 }; 1353 1354 aobus: bus@ff800000 { 1355 compatible = "simple-bus"; 1356 reg = <0x0 0xff800000 0x0 0x100000>; 1357 #address-cells = <2>; 1358 #size-cells = <2>; 1359 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1360 1361 sysctrl_AO: sys-ctrl@0 { 1362 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1363 reg = <0x0 0x0 0x0 0x100>; 1364 1365 clkc_AO: clock-controller { 1366 compatible = "amlogic,meson-axg-aoclkc"; 1367 #clock-cells = <1>; 1368 #reset-cells = <1>; 1369 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1370 clock-names = "xtal", "mpeg-clk"; 1371 }; 1372 }; 1373 1374 pinctrl_aobus: pinctrl@14 { 1375 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1376 #address-cells = <2>; 1377 #size-cells = <2>; 1378 ranges; 1379 1380 gpio_ao: bank@14 { 1381 reg = <0x0 0x00014 0x0 0x8>, 1382 <0x0 0x0002c 0x0 0x4>, 1383 <0x0 0x00024 0x0 0x8>; 1384 reg-names = "mux", "pull", "gpio"; 1385 gpio-controller; 1386 #gpio-cells = <2>; 1387 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1388 }; 1389 1390 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1391 mux { 1392 groups = "i2c_ao_sck_4"; 1393 function = "i2c_ao"; 1394 bias-disable; 1395 }; 1396 }; 1397 1398 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1399 mux { 1400 groups = "i2c_ao_sck_8"; 1401 function = "i2c_ao"; 1402 bias-disable; 1403 }; 1404 }; 1405 1406 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1407 mux { 1408 groups = "i2c_ao_sck_10"; 1409 function = "i2c_ao"; 1410 bias-disable; 1411 }; 1412 }; 1413 1414 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1415 mux { 1416 groups = "i2c_ao_sda_5"; 1417 function = "i2c_ao"; 1418 bias-disable; 1419 }; 1420 }; 1421 1422 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1423 mux { 1424 groups = "i2c_ao_sda_9"; 1425 function = "i2c_ao"; 1426 bias-disable; 1427 }; 1428 }; 1429 1430 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1431 mux { 1432 groups = "i2c_ao_sda_11"; 1433 function = "i2c_ao"; 1434 bias-disable; 1435 }; 1436 }; 1437 1438 remote_input_ao_pins: remote_input_ao { 1439 mux { 1440 groups = "remote_input_ao"; 1441 function = "remote_input_ao"; 1442 bias-disable; 1443 }; 1444 }; 1445 1446 uart_ao_a_pins: uart_ao_a { 1447 mux { 1448 groups = "uart_ao_tx_a", 1449 "uart_ao_rx_a"; 1450 function = "uart_ao_a"; 1451 bias-disable; 1452 }; 1453 }; 1454 1455 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1456 mux { 1457 groups = "uart_ao_cts_a", 1458 "uart_ao_rts_a"; 1459 function = "uart_ao_a"; 1460 bias-disable; 1461 }; 1462 }; 1463 1464 uart_ao_b_pins: uart_ao_b { 1465 mux { 1466 groups = "uart_ao_tx_b", 1467 "uart_ao_rx_b"; 1468 function = "uart_ao_b"; 1469 bias-disable; 1470 }; 1471 }; 1472 1473 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1474 mux { 1475 groups = "uart_ao_cts_b", 1476 "uart_ao_rts_b"; 1477 function = "uart_ao_b"; 1478 bias-disable; 1479 }; 1480 }; 1481 }; 1482 1483 sec_AO: ao-secure@140 { 1484 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1485 reg = <0x0 0x140 0x0 0x140>; 1486 amlogic,has-chip-id; 1487 }; 1488 1489 pwm_AO_cd: pwm@2000 { 1490 compatible = "amlogic,meson-axg-ao-pwm"; 1491 reg = <0x0 0x02000 0x0 0x20>; 1492 #pwm-cells = <3>; 1493 status = "disabled"; 1494 }; 1495 1496 uart_AO: serial@3000 { 1497 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1498 reg = <0x0 0x3000 0x0 0x18>; 1499 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1500 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1501 clock-names = "xtal", "pclk", "baud"; 1502 status = "disabled"; 1503 }; 1504 1505 uart_AO_B: serial@4000 { 1506 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1507 reg = <0x0 0x4000 0x0 0x18>; 1508 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1509 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1510 clock-names = "xtal", "pclk", "baud"; 1511 status = "disabled"; 1512 }; 1513 1514 i2c_AO: i2c@5000 { 1515 compatible = "amlogic,meson-axg-i2c"; 1516 reg = <0x0 0x05000 0x0 0x20>; 1517 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1518 clocks = <&clkc CLKID_AO_I2C>; 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 status = "disabled"; 1522 }; 1523 1524 pwm_AO_ab: pwm@7000 { 1525 compatible = "amlogic,meson-axg-ao-pwm"; 1526 reg = <0x0 0x07000 0x0 0x20>; 1527 #pwm-cells = <3>; 1528 status = "disabled"; 1529 }; 1530 1531 ir: ir@8000 { 1532 compatible = "amlogic,meson-gxbb-ir"; 1533 reg = <0x0 0x8000 0x0 0x20>; 1534 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1535 status = "disabled"; 1536 }; 1537 1538 saradc: adc@9000 { 1539 compatible = "amlogic,meson-axg-saradc", 1540 "amlogic,meson-saradc"; 1541 reg = <0x0 0x9000 0x0 0x38>; 1542 #io-channel-cells = <1>; 1543 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1544 clocks = <&xtal>, 1545 <&clkc_AO CLKID_AO_SAR_ADC>, 1546 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1547 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1548 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1549 status = "disabled"; 1550 }; 1551 }; 1552 1553 gic: interrupt-controller@ffc01000 { 1554 compatible = "arm,gic-400"; 1555 reg = <0x0 0xffc01000 0 0x1000>, 1556 <0x0 0xffc02000 0 0x2000>, 1557 <0x0 0xffc04000 0 0x2000>, 1558 <0x0 0xffc06000 0 0x2000>; 1559 interrupt-controller; 1560 interrupts = <GIC_PPI 9 1561 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1562 #interrupt-cells = <3>; 1563 #address-cells = <0>; 1564 }; 1565 1566 cbus: bus@ffd00000 { 1567 compatible = "simple-bus"; 1568 reg = <0x0 0xffd00000 0x0 0x25000>; 1569 #address-cells = <2>; 1570 #size-cells = <2>; 1571 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1572 1573 reset: reset-controller@1004 { 1574 compatible = "amlogic,meson-axg-reset"; 1575 reg = <0x0 0x01004 0x0 0x9c>; 1576 #reset-cells = <1>; 1577 }; 1578 1579 gpio_intc: interrupt-controller@f080 { 1580 compatible = "amlogic,meson-axg-gpio-intc", 1581 "amlogic,meson-gpio-intc"; 1582 reg = <0x0 0xf080 0x0 0x10>; 1583 interrupt-controller; 1584 #interrupt-cells = <2>; 1585 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1586 }; 1587 1588 watchdog@f0d0 { 1589 compatible = "amlogic,meson-gxbb-wdt"; 1590 reg = <0x0 0xf0d0 0x0 0x10>; 1591 clocks = <&xtal>; 1592 }; 1593 1594 pwm_ab: pwm@1b000 { 1595 compatible = "amlogic,meson-axg-ee-pwm"; 1596 reg = <0x0 0x1b000 0x0 0x20>; 1597 #pwm-cells = <3>; 1598 status = "disabled"; 1599 }; 1600 1601 pwm_cd: pwm@1a000 { 1602 compatible = "amlogic,meson-axg-ee-pwm"; 1603 reg = <0x0 0x1a000 0x0 0x20>; 1604 #pwm-cells = <3>; 1605 status = "disabled"; 1606 }; 1607 1608 spicc0: spi@13000 { 1609 compatible = "amlogic,meson-axg-spicc"; 1610 reg = <0x0 0x13000 0x0 0x3c>; 1611 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&clkc CLKID_SPICC0>; 1613 clock-names = "core"; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 spicc1: spi@15000 { 1620 compatible = "amlogic,meson-axg-spicc"; 1621 reg = <0x0 0x15000 0x0 0x3c>; 1622 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&clkc CLKID_SPICC1>; 1624 clock-names = "core"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 clk_msr: clock-measure@18000 { 1631 compatible = "amlogic,meson-axg-clk-measure"; 1632 reg = <0x0 0x18000 0x0 0x10>; 1633 }; 1634 1635 i2c3: i2c@1c000 { 1636 compatible = "amlogic,meson-axg-i2c"; 1637 reg = <0x0 0x1c000 0x0 0x20>; 1638 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1639 clocks = <&clkc CLKID_I2C>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 i2c2: i2c@1d000 { 1646 compatible = "amlogic,meson-axg-i2c"; 1647 reg = <0x0 0x1d000 0x0 0x20>; 1648 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1649 clocks = <&clkc CLKID_I2C>; 1650 #address-cells = <1>; 1651 #size-cells = <0>; 1652 status = "disabled"; 1653 }; 1654 1655 i2c1: i2c@1e000 { 1656 compatible = "amlogic,meson-axg-i2c"; 1657 reg = <0x0 0x1e000 0x0 0x20>; 1658 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1659 clocks = <&clkc CLKID_I2C>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 status = "disabled"; 1663 }; 1664 1665 i2c0: i2c@1f000 { 1666 compatible = "amlogic,meson-axg-i2c"; 1667 reg = <0x0 0x1f000 0x0 0x20>; 1668 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1669 clocks = <&clkc CLKID_I2C>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 uart_B: serial@23000 { 1676 compatible = "amlogic,meson-gx-uart"; 1677 reg = <0x0 0x23000 0x0 0x18>; 1678 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1679 status = "disabled"; 1680 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1681 clock-names = "xtal", "pclk", "baud"; 1682 }; 1683 1684 uart_A: serial@24000 { 1685 compatible = "amlogic,meson-gx-uart"; 1686 reg = <0x0 0x24000 0x0 0x18>; 1687 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1688 status = "disabled"; 1689 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1690 clock-names = "xtal", "pclk", "baud"; 1691 }; 1692 }; 1693 1694 apb: bus@ffe00000 { 1695 compatible = "simple-bus"; 1696 reg = <0x0 0xffe00000 0x0 0x200000>; 1697 #address-cells = <2>; 1698 #size-cells = <2>; 1699 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1700 1701 sd_emmc_b: sd@5000 { 1702 compatible = "amlogic,meson-axg-mmc"; 1703 reg = <0x0 0x5000 0x0 0x800>; 1704 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1705 status = "disabled"; 1706 clocks = <&clkc CLKID_SD_EMMC_B>, 1707 <&clkc CLKID_SD_EMMC_B_CLK0>, 1708 <&clkc CLKID_FCLK_DIV2>; 1709 clock-names = "core", "clkin0", "clkin1"; 1710 resets = <&reset RESET_SD_EMMC_B>; 1711 }; 1712 1713 sd_emmc_c: mmc@7000 { 1714 compatible = "amlogic,meson-axg-mmc"; 1715 reg = <0x0 0x7000 0x0 0x800>; 1716 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1717 status = "disabled"; 1718 clocks = <&clkc CLKID_SD_EMMC_C>, 1719 <&clkc CLKID_SD_EMMC_C_CLK0>, 1720 <&clkc CLKID_FCLK_DIV2>; 1721 clock-names = "core", "clkin0", "clkin1"; 1722 resets = <&reset RESET_SD_EMMC_C>; 1723 }; 1724 }; 1725 1726 sram: sram@fffc0000 { 1727 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1728 reg = <0x0 0xfffc0000 0x0 0x20000>; 1729 #address-cells = <1>; 1730 #size-cells = <1>; 1731 ranges = <0 0x0 0xfffc0000 0x20000>; 1732 1733 cpu_scp_lpri: scp-shmem@13000 { 1734 compatible = "amlogic,meson-axg-scp-shmem"; 1735 reg = <0x13000 0x400>; 1736 }; 1737 1738 cpu_scp_hpri: scp-shmem@13400 { 1739 compatible = "amlogic,meson-axg-scp-shmem"; 1740 reg = <0x13400 0x400>; 1741 }; 1742 }; 1743 }; 1744 1745 timer { 1746 compatible = "arm,armv8-timer"; 1747 interrupts = <GIC_PPI 13 1748 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1749 <GIC_PPI 14 1750 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1751 <GIC_PPI 11 1752 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1753 <GIC_PPI 10 1754 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1755 }; 1756 1757 xtal: xtal-clk { 1758 compatible = "fixed-clock"; 1759 clock-frequency = <24000000>; 1760 clock-output-names = "xtal"; 1761 #clock-cells = <0>; 1762 }; 1763}; 1764