1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-clkc.h> 10#include <dt-bindings/clock/axg-aoclkc.h> 11#include <dt-bindings/gpio/meson-axg-gpio.h> 12#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 13 14/ { 15 compatible = "amlogic,meson-axg"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 /* 16 MiB reserved for Hardware ROM Firmware */ 27 hwrom_reserved: hwrom@0 { 28 reg = <0x0 0x0 0x0 0x1000000>; 29 no-map; 30 }; 31 32 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 33 secmon_reserved: secmon@5000000 { 34 reg = <0x0 0x05000000 0x0 0x300000>; 35 no-map; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <0x2>; 41 #size-cells = <0x0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53", "arm,armv8"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&l2>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 next-level-cache = <&l2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <0x0 0x2>; 63 enable-method = "psci"; 64 next-level-cache = <&l2>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0x0 0x3>; 71 enable-method = "psci"; 72 next-level-cache = <&l2>; 73 }; 74 75 l2: l2-cache0 { 76 compatible = "cache"; 77 }; 78 }; 79 80 arm-pmu { 81 compatible = "arm,cortex-a53-pmu"; 82 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0"; 91 method = "smc"; 92 }; 93 94 vddio_ao18: regulator-vddio_ao18 { 95 compatible = "regulator-fixed"; 96 regulator-name = "VDDIO_AO18"; 97 regulator-min-microvolt = <1800000>; 98 regulator-max-microvolt = <1800000>; 99 }; 100 101 timer { 102 compatible = "arm,armv8-timer"; 103 interrupts = <GIC_PPI 13 104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 105 <GIC_PPI 14 106 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 107 <GIC_PPI 11 108 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 10 110 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 111 }; 112 113 xtal: xtal-clk { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 clock-output-names = "xtal"; 117 #clock-cells = <0>; 118 }; 119 120 ao_alt_xtal: ao_alt_xtal-clk { 121 compatible = "fixed-clock"; 122 clock-frequency = <32000000>; 123 clock-output-names = "ao_alt_xtal"; 124 #clock-cells = <0>; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 apb: apb@ffe00000 { 134 compatible = "simple-bus"; 135 reg = <0x0 0xffe00000 0x0 0x200000>; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 139 140 sd_emmc_b: sd@5000 { 141 compatible = "amlogic,meson-axg-mmc"; 142 reg = <0x0 0x5000 0x0 0x2000>; 143 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 144 status = "disabled"; 145 clocks = <&clkc CLKID_SD_EMMC_B>, 146 <&clkc CLKID_SD_EMMC_B_CLK0>, 147 <&clkc CLKID_FCLK_DIV2>; 148 clock-names = "core", "clkin0", "clkin1"; 149 resets = <&reset RESET_SD_EMMC_B>; 150 }; 151 152 sd_emmc_c: mmc@7000 { 153 compatible = "amlogic,meson-axg-mmc"; 154 reg = <0x0 0x7000 0x0 0x2000>; 155 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 156 status = "disabled"; 157 clocks = <&clkc CLKID_SD_EMMC_C>, 158 <&clkc CLKID_SD_EMMC_C_CLK0>, 159 <&clkc CLKID_FCLK_DIV2>; 160 clock-names = "core", "clkin0", "clkin1"; 161 resets = <&reset RESET_SD_EMMC_C>; 162 }; 163 }; 164 165 cbus: bus@ffd00000 { 166 compatible = "simple-bus"; 167 reg = <0x0 0xffd00000 0x0 0x25000>; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 171 172 gpio_intc: interrupt-controller@f080 { 173 compatible = "amlogic,meson-gpio-intc"; 174 reg = <0x0 0xf080 0x0 0x10>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 178 status = "disabled"; 179 }; 180 181 pwm_ab: pwm@1b000 { 182 compatible = "amlogic,meson-axg-ee-pwm"; 183 reg = <0x0 0x1b000 0x0 0x20>; 184 #pwm-cells = <3>; 185 status = "disabled"; 186 }; 187 188 pwm_cd: pwm@1a000 { 189 compatible = "amlogic,meson-axg-ee-pwm"; 190 reg = <0x0 0x1a000 0x0 0x20>; 191 #pwm-cells = <3>; 192 status = "disabled"; 193 }; 194 195 reset: reset-controller@1004 { 196 compatible = "amlogic,meson-axg-reset"; 197 reg = <0x0 0x01004 0x0 0x9c>; 198 #reset-cells = <1>; 199 }; 200 201 spicc0: spi@13000 { 202 compatible = "amlogic,meson-axg-spicc"; 203 reg = <0x0 0x13000 0x0 0x3c>; 204 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clkc CLKID_SPICC0>; 206 clock-names = "core"; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 status = "disabled"; 210 }; 211 212 spicc1: spi@15000 { 213 compatible = "amlogic,meson-axg-spicc"; 214 reg = <0x0 0x15000 0x0 0x3c>; 215 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clkc CLKID_SPICC1>; 217 clock-names = "core"; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c0: i2c@1f000 { 224 compatible = "amlogic,meson-axg-i2c"; 225 reg = <0x0 0x1f000 0x0 0x20>; 226 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 227 clocks = <&clkc CLKID_I2C>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c1: i2c@1e000 { 234 compatible = "amlogic,meson-axg-i2c"; 235 reg = <0x0 0x1e000 0x0 0x20>; 236 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 237 clocks = <&clkc CLKID_I2C>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c2: i2c@1d000 { 244 compatible = "amlogic,meson-axg-i2c"; 245 reg = <0x0 0x1d000 0x0 0x20>; 246 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 247 clocks = <&clkc CLKID_I2C>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 i2c3: i2c@1c000 { 254 compatible = "amlogic,meson-axg-i2c"; 255 reg = <0x0 0x1c000 0x0 0x20>; 256 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 257 clocks = <&clkc CLKID_I2C>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 status = "disabled"; 261 }; 262 263 uart_A: serial@24000 { 264 compatible = "amlogic,meson-gx-uart"; 265 reg = <0x0 0x24000 0x0 0x18>; 266 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 267 status = "disabled"; 268 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 269 clock-names = "xtal", "pclk", "baud"; 270 }; 271 272 uart_B: serial@23000 { 273 compatible = "amlogic,meson-gx-uart"; 274 reg = <0x0 0x23000 0x0 0x18>; 275 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 276 status = "disabled"; 277 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 278 clock-names = "xtal", "pclk", "baud"; 279 }; 280 }; 281 282 ethmac: ethernet@ff3f0000 { 283 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 284 reg = <0x0 0xff3f0000 0x0 0x10000 285 0x0 0xff634540 0x0 0x8>; 286 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 287 interrupt-names = "macirq"; 288 clocks = <&clkc CLKID_ETH>, 289 <&clkc CLKID_FCLK_DIV2>, 290 <&clkc CLKID_MPLL2>; 291 clock-names = "stmmaceth", "clkin0", "clkin1"; 292 status = "disabled"; 293 }; 294 295 gic: interrupt-controller@ffc01000 { 296 compatible = "arm,gic-400"; 297 reg = <0x0 0xffc01000 0 0x1000>, 298 <0x0 0xffc02000 0 0x2000>, 299 <0x0 0xffc04000 0 0x2000>, 300 <0x0 0xffc06000 0 0x2000>; 301 interrupt-controller; 302 interrupts = <GIC_PPI 9 303 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 304 #interrupt-cells = <3>; 305 #address-cells = <0>; 306 }; 307 308 hiubus: bus@ff63c000 { 309 compatible = "simple-bus"; 310 reg = <0x0 0xff63c000 0x0 0x1c00>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 314 315 sysctrl: system-controller@0 { 316 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 317 reg = <0 0 0 0x400>; 318 319 clkc: clock-controller { 320 compatible = "amlogic,axg-clkc"; 321 #clock-cells = <1>; 322 }; 323 }; 324 }; 325 326 mailbox: mailbox@ff63dc00 { 327 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 328 reg = <0 0xff63dc00 0 0x400>; 329 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 332 #mbox-cells = <1>; 333 }; 334 335 periphs: periphs@ff634000 { 336 compatible = "simple-bus"; 337 reg = <0x0 0xff634000 0x0 0x2000>; 338 #address-cells = <2>; 339 #size-cells = <2>; 340 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 341 342 hwrng: rng { 343 compatible = "amlogic,meson-rng"; 344 reg = <0x0 0x18 0x0 0x4>; 345 clocks = <&clkc CLKID_RNG0>; 346 clock-names = "core"; 347 }; 348 349 pinctrl_periphs: pinctrl@480 { 350 compatible = "amlogic,meson-axg-periphs-pinctrl"; 351 #address-cells = <2>; 352 #size-cells = <2>; 353 ranges; 354 355 gpio: bank@480 { 356 reg = <0x0 0x00480 0x0 0x40>, 357 <0x0 0x004e8 0x0 0x14>, 358 <0x0 0x00520 0x0 0x14>, 359 <0x0 0x00430 0x0 0x3c>; 360 reg-names = "mux", "pull", "pull-enable", "gpio"; 361 gpio-controller; 362 #gpio-cells = <2>; 363 gpio-ranges = <&pinctrl_periphs 0 0 86>; 364 }; 365 366 emmc_pins: emmc { 367 mux { 368 groups = "emmc_nand_d0", 369 "emmc_nand_d1", 370 "emmc_nand_d2", 371 "emmc_nand_d3", 372 "emmc_nand_d4", 373 "emmc_nand_d5", 374 "emmc_nand_d6", 375 "emmc_nand_d7", 376 "emmc_clk", 377 "emmc_cmd", 378 "emmc_ds"; 379 function = "emmc"; 380 }; 381 }; 382 383 emmc_clk_gate_pins: emmc_clk_gate { 384 mux { 385 groups = "BOOT_8"; 386 function = "gpio_periphs"; 387 }; 388 cfg-pull-down { 389 pins = "BOOT_8"; 390 bias-pull-down; 391 }; 392 }; 393 394 sdio_pins: sdio { 395 mux { 396 groups = "sdio_d0", 397 "sdio_d1", 398 "sdio_d2", 399 "sdio_d3", 400 "sdio_cmd", 401 "sdio_clk"; 402 function = "sdio"; 403 }; 404 }; 405 406 sdio_clk_gate_pins: sdio_clk_gate { 407 mux { 408 groups = "GPIOX_4"; 409 function = "gpio_periphs"; 410 }; 411 cfg-pull-down { 412 pins = "GPIOX_4"; 413 bias-pull-down; 414 }; 415 }; 416 417 eth_rmii_x_pins: eth-x-rmii { 418 mux { 419 groups = "eth_mdio_x", 420 "eth_mdc_x", 421 "eth_rgmii_rx_clk_x", 422 "eth_rx_dv_x", 423 "eth_rxd0_x", 424 "eth_rxd1_x", 425 "eth_txen_x", 426 "eth_txd0_x", 427 "eth_txd1_x"; 428 function = "eth"; 429 }; 430 }; 431 432 eth_rmii_y_pins: eth-y-rmii { 433 mux { 434 groups = "eth_mdio_y", 435 "eth_mdc_y", 436 "eth_rgmii_rx_clk_y", 437 "eth_rx_dv_y", 438 "eth_rxd0_y", 439 "eth_rxd1_y", 440 "eth_txen_y", 441 "eth_txd0_y", 442 "eth_txd1_y"; 443 function = "eth"; 444 }; 445 }; 446 447 eth_rgmii_x_pins: eth-x-rgmii { 448 mux { 449 groups = "eth_mdio_x", 450 "eth_mdc_x", 451 "eth_rgmii_rx_clk_x", 452 "eth_rx_dv_x", 453 "eth_rxd0_x", 454 "eth_rxd1_x", 455 "eth_rxd2_rgmii", 456 "eth_rxd3_rgmii", 457 "eth_rgmii_tx_clk", 458 "eth_txen_x", 459 "eth_txd0_x", 460 "eth_txd1_x", 461 "eth_txd2_rgmii", 462 "eth_txd3_rgmii"; 463 function = "eth"; 464 }; 465 }; 466 467 eth_rgmii_y_pins: eth-y-rgmii { 468 mux { 469 groups = "eth_mdio_y", 470 "eth_mdc_y", 471 "eth_rgmii_rx_clk_y", 472 "eth_rx_dv_y", 473 "eth_rxd0_y", 474 "eth_rxd1_y", 475 "eth_rxd2_rgmii", 476 "eth_rxd3_rgmii", 477 "eth_rgmii_tx_clk", 478 "eth_txen_y", 479 "eth_txd0_y", 480 "eth_txd1_y", 481 "eth_txd2_rgmii", 482 "eth_txd3_rgmii"; 483 function = "eth"; 484 }; 485 }; 486 487 pwm_a_a_pins: pwm_a_a { 488 mux { 489 groups = "pwm_a_a"; 490 function = "pwm_a"; 491 }; 492 }; 493 494 pwm_a_x18_pins: pwm_a_x18 { 495 mux { 496 groups = "pwm_a_x18"; 497 function = "pwm_a"; 498 }; 499 }; 500 501 pwm_a_x20_pins: pwm_a_x20 { 502 mux { 503 groups = "pwm_a_x20"; 504 function = "pwm_a"; 505 }; 506 }; 507 508 pwm_a_z_pins: pwm_a_z { 509 mux { 510 groups = "pwm_a_z"; 511 function = "pwm_a"; 512 }; 513 }; 514 515 pwm_b_a_pins: pwm_b_a { 516 mux { 517 groups = "pwm_b_a"; 518 function = "pwm_b"; 519 }; 520 }; 521 522 pwm_b_x_pins: pwm_b_x { 523 mux { 524 groups = "pwm_b_x"; 525 function = "pwm_b"; 526 }; 527 }; 528 529 pwm_b_z_pins: pwm_b_z { 530 mux { 531 groups = "pwm_b_z"; 532 function = "pwm_b"; 533 }; 534 }; 535 536 pwm_c_a_pins: pwm_c_a { 537 mux { 538 groups = "pwm_c_a"; 539 function = "pwm_c"; 540 }; 541 }; 542 543 pwm_c_x10_pins: pwm_c_x10 { 544 mux { 545 groups = "pwm_c_x10"; 546 function = "pwm_c"; 547 }; 548 }; 549 550 pwm_c_x17_pins: pwm_c_x17 { 551 mux { 552 groups = "pwm_c_x17"; 553 function = "pwm_c"; 554 }; 555 }; 556 557 pwm_d_x11_pins: pwm_d_x11 { 558 mux { 559 groups = "pwm_d_x11"; 560 function = "pwm_d"; 561 }; 562 }; 563 564 pwm_d_x16_pins: pwm_d_x16 { 565 mux { 566 groups = "pwm_d_x16"; 567 function = "pwm_d"; 568 }; 569 }; 570 571 spdif_out_z_pins: spdif_out_z { 572 mux { 573 groups = "spdif_out_z"; 574 function = "spdif_out"; 575 }; 576 }; 577 578 spdif_out_a1_pins: spdif_out_a1 { 579 mux { 580 groups = "spdif_out_a1"; 581 function = "spdif_out"; 582 }; 583 }; 584 585 spdif_out_a7_pins: spdif_out_a7 { 586 mux { 587 groups = "spdif_out_a7"; 588 function = "spdif_out"; 589 }; 590 }; 591 592 spdif_out_a11_pins: spdif_out_a11 { 593 mux { 594 groups = "spdif_out_a11"; 595 function = "spdif_out"; 596 }; 597 }; 598 599 spdif_out_a19_pins: spdif_out_a19 { 600 mux { 601 groups = "spdif_out_a19"; 602 function = "spdif_out"; 603 }; 604 }; 605 606 spdif_out_a20_pins: spdif_out_a20 { 607 mux { 608 groups = "spdif_out_a20"; 609 function = "spdif_out"; 610 }; 611 }; 612 613 spi0_pins: spi0 { 614 mux { 615 groups = "spi0_miso", 616 "spi0_mosi", 617 "spi0_clk"; 618 function = "spi0"; 619 }; 620 }; 621 622 spi0_ss0_pins: spi0_ss0 { 623 mux { 624 groups = "spi0_ss0"; 625 function = "spi0"; 626 }; 627 }; 628 629 spi0_ss1_pins: spi0_ss1 { 630 mux { 631 groups = "spi0_ss1"; 632 function = "spi0"; 633 }; 634 }; 635 636 spi0_ss2_pins: spi0_ss2 { 637 mux { 638 groups = "spi0_ss2"; 639 function = "spi0"; 640 }; 641 }; 642 643 644 spi1_a_pins: spi1_a { 645 mux { 646 groups = "spi1_miso_a", 647 "spi1_mosi_a", 648 "spi1_clk_a"; 649 function = "spi1"; 650 }; 651 }; 652 653 spi1_ss0_a_pins: spi1_ss0_a { 654 mux { 655 groups = "spi1_ss0_a"; 656 function = "spi1"; 657 }; 658 }; 659 660 spi1_ss1_pins: spi1_ss1 { 661 mux { 662 groups = "spi1_ss1"; 663 function = "spi1"; 664 }; 665 }; 666 667 spi1_x_pins: spi1_x { 668 mux { 669 groups = "spi1_miso_x", 670 "spi1_mosi_x", 671 "spi1_clk_x"; 672 function = "spi1"; 673 }; 674 }; 675 676 spi1_ss0_x_pins: spi1_ss0_x { 677 mux { 678 groups = "spi1_ss0_x"; 679 function = "spi1"; 680 }; 681 }; 682 683 i2c0_pins: i2c0 { 684 mux { 685 groups = "i2c0_sck", 686 "i2c0_sda"; 687 function = "i2c0"; 688 }; 689 }; 690 691 i2c1_z_pins: i2c1_z { 692 mux { 693 groups = "i2c1_sck_z", 694 "i2c1_sda_z"; 695 function = "i2c1"; 696 }; 697 }; 698 699 i2c1_x_pins: i2c1_x { 700 mux { 701 groups = "i2c1_sck_x", 702 "i2c1_sda_x"; 703 function = "i2c1"; 704 }; 705 }; 706 707 i2c2_x_pins: i2c2_x { 708 mux { 709 groups = "i2c2_sck_x", 710 "i2c2_sda_x"; 711 function = "i2c2"; 712 }; 713 }; 714 715 i2c2_a_pins: i2c2_a { 716 mux { 717 groups = "i2c2_sck_a", 718 "i2c2_sda_a"; 719 function = "i2c2"; 720 }; 721 }; 722 723 i2c3_a6_pins: i2c3_a6 { 724 mux { 725 groups = "i2c3_sda_a6", 726 "i2c3_sck_a7"; 727 function = "i2c3"; 728 }; 729 }; 730 731 i2c3_a12_pins: i2c3_a12 { 732 mux { 733 groups = "i2c3_sda_a12", 734 "i2c3_sck_a13"; 735 function = "i2c3"; 736 }; 737 }; 738 739 i2c3_a19_pins: i2c3_a19 { 740 mux { 741 groups = "i2c3_sda_a19", 742 "i2c3_sck_a20"; 743 function = "i2c3"; 744 }; 745 }; 746 747 uart_a_pins: uart_a { 748 mux { 749 groups = "uart_tx_a", 750 "uart_rx_a"; 751 function = "uart_a"; 752 }; 753 }; 754 755 uart_a_cts_rts_pins: uart_a_cts_rts { 756 mux { 757 groups = "uart_cts_a", 758 "uart_rts_a"; 759 function = "uart_a"; 760 }; 761 }; 762 763 uart_b_x_pins: uart_b_x { 764 mux { 765 groups = "uart_tx_b_x", 766 "uart_rx_b_x"; 767 function = "uart_b"; 768 }; 769 }; 770 771 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 772 mux { 773 groups = "uart_cts_b_x", 774 "uart_rts_b_x"; 775 function = "uart_b"; 776 }; 777 }; 778 779 uart_b_z_pins: uart_b_z { 780 mux { 781 groups = "uart_tx_b_z", 782 "uart_rx_b_z"; 783 function = "uart_b"; 784 }; 785 }; 786 787 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 788 mux { 789 groups = "uart_cts_b_z", 790 "uart_rts_b_z"; 791 function = "uart_b"; 792 }; 793 }; 794 795 uart_ao_b_z_pins: uart_ao_b_z { 796 mux { 797 groups = "uart_ao_tx_b_z", 798 "uart_ao_rx_b_z"; 799 function = "uart_ao_b_z"; 800 }; 801 }; 802 803 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 804 mux { 805 groups = "uart_ao_cts_b_z", 806 "uart_ao_rts_b_z"; 807 function = "uart_ao_b_z"; 808 }; 809 }; 810 811 mclk_b_pins: mclk_b { 812 mux { 813 groups = "mclk_b"; 814 function = "mclk_b"; 815 }; 816 }; 817 818 mclk_c_pins: mclk_c { 819 mux { 820 groups = "mclk_c"; 821 function = "mclk_c"; 822 }; 823 }; 824 825 tdma_sclk_pins: tdma_sclk { 826 mux { 827 groups = "tdma_sclk"; 828 function = "tdma"; 829 }; 830 }; 831 832 tdma_sclk_slv_pins: tdma_sclk_slv { 833 mux { 834 groups = "tdma_sclk_slv"; 835 function = "tdma"; 836 }; 837 }; 838 839 tdma_fs_pins: tdma_fs { 840 mux { 841 groups = "tdma_fs"; 842 function = "tdma"; 843 }; 844 }; 845 846 tdma_fs_slv_pins: tdma_fs_slv { 847 mux { 848 groups = "tdma_fs_slv"; 849 function = "tdma"; 850 }; 851 }; 852 853 tdma_din0_pins: tdma_din0 { 854 mux { 855 groups = "tdma_din0"; 856 function = "tdma"; 857 }; 858 }; 859 860 tdma_dout0_x14_pins: tdma_dout0_x14 { 861 mux { 862 groups = "tdma_dout0_x14"; 863 function = "tdma"; 864 }; 865 }; 866 867 tdma_dout0_x15_pins: tdma_dout0_x15 { 868 mux { 869 groups = "tdma_dout0_x15"; 870 function = "tdma"; 871 }; 872 }; 873 874 tdma_dout1_pins: tdma_dout1 { 875 mux { 876 groups = "tdma_dout1"; 877 function = "tdma"; 878 }; 879 }; 880 881 tdma_din1_pins: tdma_din1 { 882 mux { 883 groups = "tdma_din1"; 884 function = "tdma"; 885 }; 886 }; 887 888 tdmb_sclk_pins: tdmb_sclk { 889 mux { 890 groups = "tdmb_sclk"; 891 function = "tdmb"; 892 }; 893 }; 894 895 tdmb_sclk_slv_pins: tdmb_sclk_slv { 896 mux { 897 groups = "tdmb_sclk_slv"; 898 function = "tdmb"; 899 }; 900 }; 901 902 tdmb_fs_pins: tdmb_fs { 903 mux { 904 groups = "tdmb_fs"; 905 function = "tdmb"; 906 }; 907 }; 908 909 tdmb_fs_slv_pins: tdmb_fs_slv { 910 mux { 911 groups = "tdmb_fs_slv"; 912 function = "tdmb"; 913 }; 914 }; 915 916 tdmb_din0_pins: tdmb_din0 { 917 mux { 918 groups = "tdmb_din0"; 919 function = "tdmb"; 920 }; 921 }; 922 923 tdmb_dout0_pins: tdmb_dout0 { 924 mux { 925 groups = "tdmb_dout0"; 926 function = "tdmb"; 927 }; 928 }; 929 930 tdmb_din1_pins: tdmb_din1 { 931 mux { 932 groups = "tdmb_din1"; 933 function = "tdmb"; 934 }; 935 }; 936 937 tdmb_dout1_pins: tdmb_dout1 { 938 mux { 939 groups = "tdmb_dout1"; 940 function = "tdmb"; 941 }; 942 }; 943 944 tdmb_din2_pins: tdmb_din2 { 945 mux { 946 groups = "tdmb_din2"; 947 function = "tdmb"; 948 }; 949 }; 950 951 tdmb_dout2_pins: tdmb_dout2 { 952 mux { 953 groups = "tdmb_dout2"; 954 function = "tdmb"; 955 }; 956 }; 957 958 tdmb_din3_pins: tdmb_din3 { 959 mux { 960 groups = "tdmb_din3"; 961 function = "tdmb"; 962 }; 963 }; 964 965 tdmb_dout3_pins: tdmb_dout3 { 966 mux { 967 groups = "tdmb_dout3"; 968 function = "tdmb"; 969 }; 970 }; 971 972 tdmc_sclk_pins: tdmc_sclk { 973 mux { 974 groups = "tdmc_sclk"; 975 function = "tdmc"; 976 }; 977 }; 978 979 tdmc_sclk_slv_pins: tdmc_sclk_slv { 980 mux { 981 groups = "tdmc_sclk_slv"; 982 function = "tdmc"; 983 }; 984 }; 985 986 tdmc_fs_pins: tdmc_fs { 987 mux { 988 groups = "tdmc_fs"; 989 function = "tdmc"; 990 }; 991 }; 992 993 tdmc_fs_slv_pins: tdmc_fs_slv { 994 mux { 995 groups = "tdmc_fs_slv"; 996 function = "tdmc"; 997 }; 998 }; 999 1000 tdmc_din0_pins: tdmc_din0 { 1001 mux { 1002 groups = "tdmc_din0"; 1003 function = "tdmc"; 1004 }; 1005 }; 1006 1007 tdmc_dout0_pins: tdmc_dout0 { 1008 mux { 1009 groups = "tdmc_dout0"; 1010 function = "tdmc"; 1011 }; 1012 }; 1013 1014 tdmc_din1_pins: tdmc_din1 { 1015 mux { 1016 groups = "tdmc_din1"; 1017 function = "tdmc"; 1018 }; 1019 }; 1020 1021 tdmc_dout1_pins: tdmc_dout1 { 1022 mux { 1023 groups = "tdmc_dout1"; 1024 function = "tdmc"; 1025 }; 1026 }; 1027 1028 tdmc_din2_pins: tdmc_din2 { 1029 mux { 1030 groups = "tdmc_din2"; 1031 function = "tdmc"; 1032 }; 1033 }; 1034 1035 tdmc_dout2_pins: tdmc_dout2 { 1036 mux { 1037 groups = "tdmc_dout2"; 1038 function = "tdmc"; 1039 }; 1040 }; 1041 1042 tdmc_din3_pins: tdmc_din3 { 1043 mux { 1044 groups = "tdmc_din3"; 1045 function = "tdmc"; 1046 }; 1047 }; 1048 1049 tdmc_dout3_pins: tdmc_dout3 { 1050 mux { 1051 groups = "tdmc_dout3"; 1052 function = "tdmc"; 1053 }; 1054 }; 1055 }; 1056 }; 1057 1058 sram: sram@fffc0000 { 1059 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1060 reg = <0x0 0xfffc0000 0x0 0x20000>; 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 ranges = <0 0x0 0xfffc0000 0x20000>; 1064 1065 cpu_scp_lpri: scp-shmem@0 { 1066 compatible = "amlogic,meson-axg-scp-shmem"; 1067 reg = <0x13000 0x400>; 1068 }; 1069 1070 cpu_scp_hpri: scp-shmem@200 { 1071 compatible = "amlogic,meson-axg-scp-shmem"; 1072 reg = <0x13400 0x400>; 1073 }; 1074 }; 1075 1076 aobus: bus@ff800000 { 1077 compatible = "simple-bus"; 1078 reg = <0x0 0xff800000 0x0 0x100000>; 1079 #address-cells = <2>; 1080 #size-cells = <2>; 1081 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1082 1083 sysctrl_AO: sys-ctrl@0 { 1084 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd"; 1085 reg = <0x0 0x0 0x0 0x100>; 1086 1087 clkc_AO: clock-controller { 1088 compatible = "amlogic,meson-axg-aoclkc"; 1089 #clock-cells = <1>; 1090 #reset-cells = <1>; 1091 }; 1092 }; 1093 1094 pinctrl_aobus: pinctrl@14 { 1095 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1096 #address-cells = <2>; 1097 #size-cells = <2>; 1098 ranges; 1099 1100 gpio_ao: bank@14 { 1101 reg = <0x0 0x00014 0x0 0x8>, 1102 <0x0 0x0002c 0x0 0x4>, 1103 <0x0 0x00024 0x0 0x8>; 1104 reg-names = "mux", "pull", "gpio"; 1105 gpio-controller; 1106 #gpio-cells = <2>; 1107 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1108 }; 1109 1110 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1111 mux { 1112 groups = "i2c_ao_sck_4"; 1113 function = "i2c_ao"; 1114 }; 1115 }; 1116 1117 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1118 mux { 1119 groups = "i2c_ao_sck_8"; 1120 function = "i2c_ao"; 1121 }; 1122 }; 1123 1124 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1125 mux { 1126 groups = "i2c_ao_sck_10"; 1127 function = "i2c_ao"; 1128 }; 1129 }; 1130 1131 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1132 mux { 1133 groups = "i2c_ao_sda_5"; 1134 function = "i2c_ao"; 1135 }; 1136 }; 1137 1138 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1139 mux { 1140 groups = "i2c_ao_sda_9"; 1141 function = "i2c_ao"; 1142 }; 1143 }; 1144 1145 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1146 mux { 1147 groups = "i2c_ao_sda_11"; 1148 function = "i2c_ao"; 1149 }; 1150 }; 1151 1152 remote_input_ao_pins: remote_input_ao { 1153 mux { 1154 groups = "remote_input_ao"; 1155 function = "remote_input_ao"; 1156 }; 1157 }; 1158 1159 uart_ao_a_pins: uart_ao_a { 1160 mux { 1161 groups = "uart_ao_tx_a", 1162 "uart_ao_rx_a"; 1163 function = "uart_ao_a"; 1164 }; 1165 }; 1166 1167 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1168 mux { 1169 groups = "uart_ao_cts_a", 1170 "uart_ao_rts_a"; 1171 function = "uart_ao_a"; 1172 }; 1173 }; 1174 1175 uart_ao_b_pins: uart_ao_b { 1176 mux { 1177 groups = "uart_ao_tx_b", 1178 "uart_ao_rx_b"; 1179 function = "uart_ao_b"; 1180 }; 1181 }; 1182 1183 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1184 mux { 1185 groups = "uart_ao_cts_b", 1186 "uart_ao_rts_b"; 1187 function = "uart_ao_b"; 1188 }; 1189 }; 1190 }; 1191 1192 sec_AO: ao-secure@140 { 1193 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1194 reg = <0x0 0x140 0x0 0x140>; 1195 amlogic,has-chip-id; 1196 }; 1197 1198 pwm_AO_ab: pwm@7000 { 1199 compatible = "amlogic,meson-axg-ao-pwm"; 1200 reg = <0x0 0x07000 0x0 0x20>; 1201 #pwm-cells = <3>; 1202 status = "disabled"; 1203 }; 1204 1205 pwm_AO_cd: pwm@2000 { 1206 compatible = "amlogic,meson-axg-ao-pwm"; 1207 reg = <0x0 0x02000 0x0 0x20>; 1208 #pwm-cells = <3>; 1209 status = "disabled"; 1210 }; 1211 1212 i2c_AO: i2c@5000 { 1213 compatible = "amlogic,meson-axg-i2c"; 1214 reg = <0x0 0x05000 0x0 0x20>; 1215 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1216 clocks = <&clkc CLKID_AO_I2C>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 uart_AO: serial@3000 { 1223 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1224 reg = <0x0 0x3000 0x0 0x18>; 1225 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1226 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1227 clock-names = "xtal", "pclk", "baud"; 1228 status = "disabled"; 1229 }; 1230 1231 uart_AO_B: serial@4000 { 1232 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1233 reg = <0x0 0x4000 0x0 0x18>; 1234 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1235 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1236 clock-names = "xtal", "pclk", "baud"; 1237 status = "disabled"; 1238 }; 1239 1240 ir: ir@8000 { 1241 compatible = "amlogic,meson-gxbb-ir"; 1242 reg = <0x0 0x8000 0x0 0x20>; 1243 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1244 status = "disabled"; 1245 }; 1246 1247 saradc: adc@9000 { 1248 compatible = "amlogic,meson-axg-saradc", 1249 "amlogic,meson-saradc"; 1250 reg = <0x0 0x9000 0x0 0x38>; 1251 #io-channel-cells = <1>; 1252 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1253 clocks = <&xtal>, 1254 <&clkc_AO CLKID_AO_SAR_ADC>, 1255 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1256 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1257 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1258 status = "disabled"; 1259 }; 1260 }; 1261 }; 1262}; 1263