1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		cbus: bus@ffd00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffd00000 0x0 0x25000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
123
124			pwm_ab: pwm@1b000 {
125				compatible = "amlogic,meson-axg-ee-pwm";
126				reg = <0x0 0x1b000 0x0 0x20>;
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			pwm_cd: pwm@1a000 {
132				compatible = "amlogic,meson-axg-ee-pwm";
133				reg = <0x0 0x1a000 0x0 0x20>;
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			reset: reset-controller@1004 {
139				compatible = "amlogic,meson-axg-reset";
140				reg = <0x0 0x01004 0x0 0x9c>;
141				#reset-cells = <1>;
142			};
143
144			spicc0: spi@13000 {
145				compatible = "amlogic,meson-axg-spicc";
146				reg = <0x0 0x13000 0x0 0x3c>;
147				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clkc CLKID_SPICC0>;
149				clock-names = "core";
150				#address-cells = <1>;
151				#size-cells = <0>;
152				status = "disabled";
153			};
154
155			spicc1: spi@15000 {
156				compatible = "amlogic,meson-axg-spicc";
157				reg = <0x0 0x15000 0x0 0x3c>;
158				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159				clocks = <&clkc CLKID_SPICC1>;
160				clock-names = "core";
161				#address-cells = <1>;
162				#size-cells = <0>;
163				status = "disabled";
164			};
165
166			i2c0: i2c@1f000 {
167				compatible = "amlogic,meson-axg-i2c";
168				status = "disabled";
169				reg = <0x0 0x1f000 0x0 0x20>;
170				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
171					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
172				#address-cells = <1>;
173				#size-cells = <0>;
174				clocks = <&clkc CLKID_I2C>;
175				clock-names = "clk_i2c";
176			};
177
178			i2c1: i2c@1e000 {
179				compatible = "amlogic,meson-axg-i2c";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				reg = <0x0 0x1e000 0x0 0x20>;
183				status = "disabled";
184				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
185					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
186				clocks = <&clkc CLKID_I2C>;
187				clock-names = "clk_i2c";
188			};
189
190			i2c2: i2c@1d000 {
191				compatible = "amlogic,meson-axg-i2c";
192				status = "disabled";
193				reg = <0x0 0x1d000 0x0 0x20>;
194				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
195					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
196				#address-cells = <1>;
197				#size-cells = <0>;
198				clocks = <&clkc CLKID_I2C>;
199				clock-names = "clk_i2c";
200			};
201
202			i2c3: i2c@1c000 {
203				compatible = "amlogic,meson-axg-i2c";
204				status = "disabled";
205				reg = <0x0 0x1c000 0x0 0x20>;
206				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
207					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
208				#address-cells = <1>;
209				#size-cells = <0>;
210				clocks = <&clkc CLKID_I2C>;
211				clock-names = "clk_i2c";
212			};
213
214			uart_A: serial@24000 {
215				compatible = "amlogic,meson-gx-uart";
216				reg = <0x0 0x24000 0x0 0x18>;
217				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
218				status = "disabled";
219				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
220				clock-names = "xtal", "pclk", "baud";
221			};
222
223			uart_B: serial@23000 {
224				compatible = "amlogic,meson-gx-uart";
225				reg = <0x0 0x23000 0x0 0x18>;
226				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
227				status = "disabled";
228				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
229				clock-names = "xtal", "pclk", "baud";
230			};
231		};
232
233		ethmac: ethernet@ff3f0000 {
234			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
235			reg = <0x0 0xff3f0000 0x0 0x10000
236				0x0 0xff634540 0x0 0x8>;
237			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
238			interrupt-names = "macirq";
239			clocks = <&clkc CLKID_ETH>,
240				 <&clkc CLKID_FCLK_DIV2>,
241				 <&clkc CLKID_MPLL2>;
242			clock-names = "stmmaceth", "clkin0", "clkin1";
243			status = "disabled";
244		};
245
246		gic: interrupt-controller@ffc01000 {
247			compatible = "arm,gic-400";
248			reg = <0x0 0xffc01000 0 0x1000>,
249			      <0x0 0xffc02000 0 0x2000>,
250			      <0x0 0xffc04000 0 0x2000>,
251			      <0x0 0xffc06000 0 0x2000>;
252			interrupt-controller;
253			interrupts = <GIC_PPI 9
254				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
255			#interrupt-cells = <3>;
256			#address-cells = <0>;
257		};
258
259		hiubus: bus@ff63c000 {
260			compatible = "simple-bus";
261			reg = <0x0 0xff63c000 0x0 0x1c00>;
262			#address-cells = <2>;
263			#size-cells = <2>;
264			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
265
266			clkc: clock-controller@0 {
267				compatible = "amlogic,axg-clkc";
268				#clock-cells = <1>;
269				reg = <0x0 0x0 0x0 0x320>;
270			};
271		};
272
273		mailbox: mailbox@ff63dc00 {
274			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
275			reg = <0 0xff63dc00 0 0x400>;
276			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
277				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
278				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
279			#mbox-cells = <1>;
280		};
281
282		periphs: periphs@ff634000 {
283			compatible = "simple-bus";
284			reg = <0x0 0xff634000 0x0 0x2000>;
285			#address-cells = <2>;
286			#size-cells = <2>;
287			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
288
289			hwrng: rng {
290				compatible = "amlogic,meson-rng";
291				reg = <0x0 0x18 0x0 0x4>;
292				clocks = <&clkc CLKID_RNG0>;
293				clock-names = "core";
294			};
295
296			pinctrl_periphs: pinctrl@480 {
297				compatible = "amlogic,meson-axg-periphs-pinctrl";
298				#address-cells = <2>;
299				#size-cells = <2>;
300				ranges;
301
302				gpio: bank@480 {
303					reg = <0x0 0x00480 0x0 0x40>,
304						<0x0 0x004e8 0x0 0x14>,
305						<0x0 0x00520 0x0 0x14>,
306						<0x0 0x00430 0x0 0x3c>;
307					reg-names = "mux", "pull", "pull-enable", "gpio";
308					gpio-controller;
309					#gpio-cells = <2>;
310					gpio-ranges = <&pinctrl_periphs 0 0 86>;
311				};
312
313				eth_rmii_x_pins: eth-x-rmii {
314					mux {
315						groups = "eth_mdio_x",
316						       "eth_mdc_x",
317						       "eth_rgmii_rx_clk_x",
318						       "eth_rx_dv_x",
319						       "eth_rxd0_x",
320						       "eth_rxd1_x",
321						       "eth_txen_x",
322						       "eth_txd0_x",
323						       "eth_txd1_x";
324						function = "eth";
325					};
326				};
327
328				eth_rmii_y_pins: eth-y-rmii {
329					mux {
330						groups = "eth_mdio_y",
331						       "eth_mdc_y",
332						       "eth_rgmii_rx_clk_y",
333						       "eth_rx_dv_y",
334						       "eth_rxd0_y",
335						       "eth_rxd1_y",
336						       "eth_txen_y",
337						       "eth_txd0_y",
338						       "eth_txd1_y";
339						function = "eth";
340					};
341				};
342
343				eth_rgmii_x_pins: eth-x-rgmii {
344					mux {
345						groups = "eth_mdio_x",
346						       "eth_mdc_x",
347						       "eth_rgmii_rx_clk_x",
348						       "eth_rx_dv_x",
349						       "eth_rxd0_x",
350						       "eth_rxd1_x",
351						       "eth_rxd2_rgmii",
352						       "eth_rxd3_rgmii",
353						       "eth_rgmii_tx_clk",
354						       "eth_txen_x",
355						       "eth_txd0_x",
356						       "eth_txd1_x",
357						       "eth_txd2_rgmii",
358						       "eth_txd3_rgmii";
359						function = "eth";
360					};
361				};
362
363				eth_rgmii_y_pins: eth-y-rgmii {
364					mux {
365						groups = "eth_mdio_y",
366						       "eth_mdc_y",
367						       "eth_rgmii_rx_clk_y",
368						       "eth_rx_dv_y",
369						       "eth_rxd0_y",
370						       "eth_rxd1_y",
371						       "eth_rxd2_rgmii",
372						       "eth_rxd3_rgmii",
373						       "eth_rgmii_tx_clk",
374						       "eth_txen_y",
375						       "eth_txd0_y",
376						       "eth_txd1_y",
377						       "eth_txd2_rgmii",
378						       "eth_txd3_rgmii";
379						function = "eth";
380					};
381				};
382
383				pwm_a_a_pins: pwm_a_a {
384					mux {
385						groups = "pwm_a_a";
386						function = "pwm_a";
387					};
388				};
389
390				pwm_a_x18_pins: pwm_a_x18 {
391					mux {
392						groups = "pwm_a_x18";
393						function = "pwm_a";
394					};
395				};
396
397				pwm_a_x20_pins: pwm_a_x20 {
398					mux {
399						groups = "pwm_a_x20";
400						function = "pwm_a";
401					};
402				};
403
404				pwm_a_z_pins: pwm_a_z {
405					mux {
406						groups = "pwm_a_z";
407						function = "pwm_a";
408					};
409				};
410
411				pwm_b_a_pins: pwm_b_a {
412					mux {
413						groups = "pwm_b_a";
414						function = "pwm_b";
415					};
416				};
417
418				pwm_b_x_pins: pwm_b_x {
419					mux {
420						groups = "pwm_b_x";
421						function = "pwm_b";
422					};
423				};
424
425				pwm_b_z_pins: pwm_b_z {
426					mux {
427						groups = "pwm_b_z";
428						function = "pwm_b";
429					};
430				};
431
432				pwm_c_a_pins: pwm_c_a {
433					mux {
434						groups = "pwm_c_a";
435						function = "pwm_c";
436					};
437				};
438
439				pwm_c_x10_pins: pwm_c_x10 {
440					mux {
441						groups = "pwm_c_x10";
442						function = "pwm_c";
443					};
444				};
445
446				pwm_c_x17_pins: pwm_c_x17 {
447					mux {
448						groups = "pwm_c_x17";
449						function = "pwm_c";
450					};
451				};
452
453				pwm_d_x11_pins: pwm_d_x11 {
454					mux {
455						groups = "pwm_d_x11";
456						function = "pwm_d";
457					};
458				};
459
460				pwm_d_x16_pins: pwm_d_x16 {
461					mux {
462						groups = "pwm_d_x16";
463						function = "pwm_d";
464					};
465				};
466
467				spi0_pins: spi0 {
468					mux {
469						groups = "spi0_miso",
470							"spi0_mosi",
471							"spi0_clk";
472						function = "spi0";
473					};
474				};
475
476				spi0_ss0_pins: spi0_ss0 {
477					mux {
478						groups = "spi0_ss0";
479						function = "spi0";
480					};
481				};
482
483				spi0_ss1_pins: spi0_ss1 {
484					mux {
485						groups = "spi0_ss1";
486						function = "spi0";
487					};
488				};
489
490				spi0_ss2_pins: spi0_ss2 {
491					mux {
492						groups = "spi0_ss2";
493						function = "spi0";
494					};
495				};
496
497
498				spi1_a_pins: spi1_a {
499					mux {
500						groups = "spi1_miso_a",
501							"spi1_mosi_a",
502							"spi1_clk_a";
503						function = "spi1";
504					};
505				};
506
507				spi1_ss0_a_pins: spi1_ss0_a {
508					mux {
509						groups = "spi1_ss0_a";
510						function = "spi1";
511					};
512				};
513
514				spi1_ss1_pins: spi1_ss1 {
515					mux {
516						groups = "spi1_ss1";
517						function = "spi1";
518					};
519				};
520
521				spi1_x_pins: spi1_x {
522					mux {
523						groups = "spi1_miso_x",
524							"spi1_mosi_x",
525							"spi1_clk_x";
526						function = "spi1";
527					};
528				};
529
530				spi1_ss0_x_pins: spi1_ss0_x {
531					mux {
532						groups = "spi1_ss0_x";
533						function = "spi1";
534					};
535				};
536
537				i2c0_pins: i2c0 {
538					mux {
539						groups = "i2c0_sck",
540							"i2c0_sda";
541						function = "i2c0";
542					};
543				};
544
545				i2c1_z_pins: i2c1_z {
546					mux {
547						groups = "i2c1_sck_z",
548							"i2c1_sda_z";
549						function = "i2c1";
550					};
551				};
552
553				i2c1_x_pins: i2c1_x {
554					mux {
555						groups = "i2c1_sck_x",
556							"i2c1_sda_x";
557						function = "i2c1";
558					};
559				};
560
561				i2c2_x_pins: i2c2_x {
562					mux {
563						groups = "i2c2_sck_x",
564							"i2c2_sda_x";
565						function = "i2c2";
566					};
567				};
568
569				i2c2_a_pins: i2c2_a {
570					mux {
571						groups = "i2c2_sck_a",
572							"i2c2_sda_a";
573						function = "i2c2";
574					};
575				};
576
577				i2c3_a6_pins: i2c3_a6 {
578					mux {
579						groups = "i2c3_sda_a6",
580							"i2c3_sck_a7";
581						function = "i2c3";
582					};
583				};
584
585				i2c3_a12_pins: i2c3_a12 {
586					mux {
587						groups = "i2c3_sda_a12",
588							"i2c3_sck_a13";
589						function = "i2c3";
590					};
591				};
592
593				i2c3_a19_pins: i2c3_a19 {
594					mux {
595						groups = "i2c3_sda_a19",
596							"i2c3_sck_a20";
597						function = "i2c3";
598					};
599				};
600
601				uart_a_pins: uart_a {
602					mux {
603						groups = "uart_tx_a",
604							"uart_rx_a";
605						function = "uart_a";
606					};
607				};
608
609				uart_a_cts_rts_pins: uart_a_cts_rts {
610					mux {
611						groups = "uart_cts_a",
612							"uart_rts_a";
613						function = "uart_a";
614					};
615				};
616
617				uart_b_x_pins: uart_b_x {
618					mux {
619						groups = "uart_tx_b_x",
620							"uart_rx_b_x";
621						function = "uart_b";
622					};
623				};
624
625				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
626					mux {
627						groups = "uart_cts_b_x",
628							"uart_rts_b_x";
629						function = "uart_b";
630					};
631				};
632
633				uart_b_z_pins: uart_b_z {
634					mux {
635						groups = "uart_tx_b_z",
636							"uart_rx_b_z";
637						function = "uart_b";
638					};
639				};
640
641				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
642					mux {
643						groups = "uart_cts_b_z",
644							"uart_rts_b_z";
645						function = "uart_b";
646					};
647				};
648
649				uart_ao_b_z_pins: uart_ao_b_z {
650					mux {
651						groups = "uart_ao_tx_b_z",
652							"uart_ao_rx_b_z";
653						function = "uart_ao_b_z";
654					};
655				};
656
657				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
658					mux {
659						groups = "uart_ao_cts_b_z",
660							"uart_ao_rts_b_z";
661						function = "uart_ao_b_z";
662					};
663				};
664			};
665		};
666
667		sram: sram@fffc0000 {
668			compatible = "amlogic,meson-axg-sram", "mmio-sram";
669			reg = <0x0 0xfffc0000 0x0 0x20000>;
670			#address-cells = <1>;
671			#size-cells = <1>;
672			ranges = <0 0x0 0xfffc0000 0x20000>;
673
674			cpu_scp_lpri: scp-shmem@0 {
675				compatible = "amlogic,meson-axg-scp-shmem";
676				reg = <0x13000 0x400>;
677			};
678
679			cpu_scp_hpri: scp-shmem@200 {
680				compatible = "amlogic,meson-axg-scp-shmem";
681				reg = <0x13400 0x400>;
682			};
683		};
684
685		aobus: bus@ff800000 {
686			compatible = "simple-bus";
687			reg = <0x0 0xff800000 0x0 0x100000>;
688			#address-cells = <2>;
689			#size-cells = <2>;
690			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
691
692			pinctrl_aobus: pinctrl@14 {
693				compatible = "amlogic,meson-axg-aobus-pinctrl";
694				#address-cells = <2>;
695				#size-cells = <2>;
696				ranges;
697
698				gpio_ao: bank@14 {
699					reg = <0x0 0x00014 0x0 0x8>,
700						<0x0 0x0002c 0x0 0x4>,
701						<0x0 0x00024 0x0 0x8>;
702					reg-names = "mux", "pull", "gpio";
703					gpio-controller;
704					#gpio-cells = <2>;
705					gpio-ranges = <&pinctrl_aobus 0 0 15>;
706				};
707
708				remote_input_ao_pins: remote_input_ao {
709					mux {
710						groups = "remote_input_ao";
711						function = "remote_input_ao";
712					};
713				};
714
715				uart_ao_a_pins: uart_ao_a {
716					mux {
717						groups = "uart_ao_tx_a",
718							"uart_ao_rx_a";
719						function = "uart_ao_a";
720					};
721				};
722
723				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
724					mux {
725						groups = "uart_ao_cts_a",
726							"uart_ao_rts_a";
727						function = "uart_ao_a";
728					};
729				};
730
731				uart_ao_b_pins: uart_ao_b {
732					mux {
733						groups = "uart_ao_tx_b",
734							"uart_ao_rx_b";
735						function = "uart_ao_b";
736					};
737				};
738
739				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
740					mux {
741						groups = "uart_ao_cts_b",
742							"uart_ao_rts_b";
743						function = "uart_ao_b";
744					};
745				};
746			};
747
748			sec_AO: ao-secure@140 {
749				compatible = "amlogic,meson-gx-ao-secure", "syscon";
750				reg = <0x0 0x140 0x0 0x140>;
751				amlogic,has-chip-id;
752			};
753
754			pwm_AO_ab: pwm@7000 {
755				compatible = "amlogic,meson-axg-ao-pwm";
756				reg = <0x0 0x07000 0x0 0x20>;
757				#pwm-cells = <3>;
758				status = "disabled";
759			};
760
761			pwm_AO_cd: pwm@2000 {
762				compatible = "amlogic,axg-ao-pwm";
763				reg = <0x0 0x02000  0x0 0x20>;
764				#pwm-cells = <3>;
765				status = "disabled";
766			};
767
768			i2c_AO: i2c@5000 {
769				compatible = "amlogic,meson-axg-i2c";
770				status = "disabled";
771				reg = <0x0 0x05000 0x0 0x20>;
772				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
773				#address-cells = <1>;
774				#size-cells = <0>;
775				clocks = <&clkc CLKID_I2C>;
776				clock-names = "clk_i2c";
777			};
778
779			uart_AO: serial@3000 {
780				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
781				reg = <0x0 0x3000 0x0 0x18>;
782				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
783				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
784				clock-names = "xtal", "pclk", "baud";
785				status = "disabled";
786			};
787
788			uart_AO_B: serial@4000 {
789				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
790				reg = <0x0 0x4000 0x0 0x18>;
791				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
792				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
793				clock-names = "xtal", "pclk", "baud";
794				status = "disabled";
795			};
796
797			ir: ir@8000 {
798				compatible = "amlogic,meson-gxbb-ir";
799				reg = <0x0 0x8000 0x0 0x20>;
800				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
801				status = "disabled";
802			};
803		};
804	};
805};
806