1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 secure-monitor = <&sm>; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 /* 16 MiB reserved for Hardware ROM Firmware */ 134 hwrom_reserved: hwrom@0 { 135 reg = <0x0 0x0 0x0 0x1000000>; 136 no-map; 137 }; 138 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 140 secmon_reserved: secmon@5000000 { 141 reg = <0x0 0x05000000 0x0 0x300000>; 142 no-map; 143 }; 144 }; 145 146 scpi { 147 compatible = "arm,scpi-pre-1.0"; 148 mboxes = <&mailbox 1 &mailbox 2>; 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 150 151 scpi_clocks: clocks { 152 compatible = "arm,scpi-clocks"; 153 154 scpi_dvfs: clock-controller { 155 compatible = "arm,scpi-dvfs-clocks"; 156 #clock-cells = <1>; 157 clock-indices = <0>; 158 clock-output-names = "vcpu"; 159 }; 160 }; 161 162 scpi_sensors: sensors { 163 compatible = "amlogic,meson-gxbb-scpi-sensors"; 164 #thermal-sensor-cells = <1>; 165 }; 166 }; 167 168 soc { 169 compatible = "simple-bus"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 ethmac: ethernet@ff3f0000 { 175 compatible = "amlogic,meson-axg-dwmac", 176 "snps,dwmac-3.70a", 177 "snps,dwmac"; 178 reg = <0x0 0xff3f0000 0x0 0x10000>, 179 <0x0 0xff634540 0x0 0x8>; 180 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "macirq"; 182 clocks = <&clkc CLKID_ETH>, 183 <&clkc CLKID_FCLK_DIV2>, 184 <&clkc CLKID_MPLL2>; 185 clock-names = "stmmaceth", "clkin0", "clkin1"; 186 rx-fifo-depth = <4096>; 187 tx-fifo-depth = <2048>; 188 status = "disabled"; 189 }; 190 191 pdm: audio-controller@ff632000 { 192 compatible = "amlogic,axg-pdm"; 193 reg = <0x0 0xff632000 0x0 0x34>; 194 #sound-dai-cells = <0>; 195 sound-name-prefix = "PDM"; 196 clocks = <&clkc_audio AUD_CLKID_PDM>, 197 <&clkc_audio AUD_CLKID_PDM_DCLK>, 198 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 199 clock-names = "pclk", "dclk", "sysclk"; 200 status = "disabled"; 201 }; 202 203 periphs: bus@ff634000 { 204 compatible = "simple-bus"; 205 reg = <0x0 0xff634000 0x0 0x2000>; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 209 210 hwrng: rng@18 { 211 compatible = "amlogic,meson-rng"; 212 reg = <0x0 0x18 0x0 0x4>; 213 clocks = <&clkc CLKID_RNG0>; 214 clock-names = "core"; 215 }; 216 217 pinctrl_periphs: pinctrl@480 { 218 compatible = "amlogic,meson-axg-periphs-pinctrl"; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges; 222 223 gpio: bank@480 { 224 reg = <0x0 0x00480 0x0 0x40>, 225 <0x0 0x004e8 0x0 0x14>, 226 <0x0 0x00520 0x0 0x14>, 227 <0x0 0x00430 0x0 0x3c>; 228 reg-names = "mux", "pull", "pull-enable", "gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 gpio-ranges = <&pinctrl_periphs 0 0 86>; 232 }; 233 234 i2c0_pins: i2c0 { 235 mux { 236 groups = "i2c0_sck", 237 "i2c0_sda"; 238 function = "i2c0"; 239 bias-disable; 240 }; 241 }; 242 243 i2c1_x_pins: i2c1_x { 244 mux { 245 groups = "i2c1_sck_x", 246 "i2c1_sda_x"; 247 function = "i2c1"; 248 bias-disable; 249 }; 250 }; 251 252 i2c1_z_pins: i2c1_z { 253 mux { 254 groups = "i2c1_sck_z", 255 "i2c1_sda_z"; 256 function = "i2c1"; 257 bias-disable; 258 }; 259 }; 260 261 i2c2_a_pins: i2c2_a { 262 mux { 263 groups = "i2c2_sck_a", 264 "i2c2_sda_a"; 265 function = "i2c2"; 266 bias-disable; 267 }; 268 }; 269 270 i2c2_x_pins: i2c2_x { 271 mux { 272 groups = "i2c2_sck_x", 273 "i2c2_sda_x"; 274 function = "i2c2"; 275 bias-disable; 276 }; 277 }; 278 279 i2c3_a6_pins: i2c3_a6 { 280 mux { 281 groups = "i2c3_sda_a6", 282 "i2c3_sck_a7"; 283 function = "i2c3"; 284 bias-disable; 285 }; 286 }; 287 288 i2c3_a12_pins: i2c3_a12 { 289 mux { 290 groups = "i2c3_sda_a12", 291 "i2c3_sck_a13"; 292 function = "i2c3"; 293 bias-disable; 294 }; 295 }; 296 297 i2c3_a19_pins: i2c3_a19 { 298 mux { 299 groups = "i2c3_sda_a19", 300 "i2c3_sck_a20"; 301 function = "i2c3"; 302 bias-disable; 303 }; 304 }; 305 306 emmc_pins: emmc { 307 mux-0 { 308 groups = "emmc_nand_d0", 309 "emmc_nand_d1", 310 "emmc_nand_d2", 311 "emmc_nand_d3", 312 "emmc_nand_d4", 313 "emmc_nand_d5", 314 "emmc_nand_d6", 315 "emmc_nand_d7", 316 "emmc_cmd"; 317 function = "emmc"; 318 bias-pull-up; 319 }; 320 321 mux-1 { 322 groups = "emmc_clk"; 323 function = "emmc"; 324 bias-disable; 325 }; 326 }; 327 328 emmc_ds_pins: emmc_ds { 329 mux { 330 groups = "emmc_ds"; 331 function = "emmc"; 332 bias-pull-down; 333 }; 334 }; 335 336 emmc_clk_gate_pins: emmc_clk_gate { 337 mux { 338 groups = "BOOT_8"; 339 function = "gpio_periphs"; 340 bias-pull-down; 341 }; 342 }; 343 344 eth_rgmii_x_pins: eth-x-rgmii { 345 mux { 346 groups = "eth_mdio_x", 347 "eth_mdc_x", 348 "eth_rgmii_rx_clk_x", 349 "eth_rx_dv_x", 350 "eth_rxd0_x", 351 "eth_rxd1_x", 352 "eth_rxd2_rgmii", 353 "eth_rxd3_rgmii", 354 "eth_rgmii_tx_clk", 355 "eth_txen_x", 356 "eth_txd0_x", 357 "eth_txd1_x", 358 "eth_txd2_rgmii", 359 "eth_txd3_rgmii"; 360 function = "eth"; 361 bias-disable; 362 }; 363 }; 364 365 eth_rgmii_y_pins: eth-y-rgmii { 366 mux { 367 groups = "eth_mdio_y", 368 "eth_mdc_y", 369 "eth_rgmii_rx_clk_y", 370 "eth_rx_dv_y", 371 "eth_rxd0_y", 372 "eth_rxd1_y", 373 "eth_rxd2_rgmii", 374 "eth_rxd3_rgmii", 375 "eth_rgmii_tx_clk", 376 "eth_txen_y", 377 "eth_txd0_y", 378 "eth_txd1_y", 379 "eth_txd2_rgmii", 380 "eth_txd3_rgmii"; 381 function = "eth"; 382 bias-disable; 383 }; 384 }; 385 386 eth_rmii_x_pins: eth-x-rmii { 387 mux { 388 groups = "eth_mdio_x", 389 "eth_mdc_x", 390 "eth_rgmii_rx_clk_x", 391 "eth_rx_dv_x", 392 "eth_rxd0_x", 393 "eth_rxd1_x", 394 "eth_txen_x", 395 "eth_txd0_x", 396 "eth_txd1_x"; 397 function = "eth"; 398 bias-disable; 399 }; 400 }; 401 402 eth_rmii_y_pins: eth-y-rmii { 403 mux { 404 groups = "eth_mdio_y", 405 "eth_mdc_y", 406 "eth_rgmii_rx_clk_y", 407 "eth_rx_dv_y", 408 "eth_rxd0_y", 409 "eth_rxd1_y", 410 "eth_txen_y", 411 "eth_txd0_y", 412 "eth_txd1_y"; 413 function = "eth"; 414 bias-disable; 415 }; 416 }; 417 418 mclk_b_pins: mclk_b { 419 mux { 420 groups = "mclk_b"; 421 function = "mclk_b"; 422 bias-disable; 423 }; 424 }; 425 426 mclk_c_pins: mclk_c { 427 mux { 428 groups = "mclk_c"; 429 function = "mclk_c"; 430 bias-disable; 431 }; 432 }; 433 434 pdm_dclk_a14_pins: pdm_dclk_a14 { 435 mux { 436 groups = "pdm_dclk_a14"; 437 function = "pdm"; 438 bias-disable; 439 }; 440 }; 441 442 pdm_dclk_a19_pins: pdm_dclk_a19 { 443 mux { 444 groups = "pdm_dclk_a19"; 445 function = "pdm"; 446 bias-disable; 447 }; 448 }; 449 450 pdm_din0_pins: pdm_din0 { 451 mux { 452 groups = "pdm_din0"; 453 function = "pdm"; 454 bias-disable; 455 }; 456 }; 457 458 pdm_din1_pins: pdm_din1 { 459 mux { 460 groups = "pdm_din1"; 461 function = "pdm"; 462 bias-disable; 463 }; 464 }; 465 466 pdm_din2_pins: pdm_din2 { 467 mux { 468 groups = "pdm_din2"; 469 function = "pdm"; 470 bias-disable; 471 }; 472 }; 473 474 pdm_din3_pins: pdm_din3 { 475 mux { 476 groups = "pdm_din3"; 477 function = "pdm"; 478 bias-disable; 479 }; 480 }; 481 482 pwm_a_a_pins: pwm_a_a { 483 mux { 484 groups = "pwm_a_a"; 485 function = "pwm_a"; 486 bias-disable; 487 }; 488 }; 489 490 pwm_a_x18_pins: pwm_a_x18 { 491 mux { 492 groups = "pwm_a_x18"; 493 function = "pwm_a"; 494 bias-disable; 495 }; 496 }; 497 498 pwm_a_x20_pins: pwm_a_x20 { 499 mux { 500 groups = "pwm_a_x20"; 501 function = "pwm_a"; 502 bias-disable; 503 }; 504 }; 505 506 pwm_a_z_pins: pwm_a_z { 507 mux { 508 groups = "pwm_a_z"; 509 function = "pwm_a"; 510 bias-disable; 511 }; 512 }; 513 514 pwm_b_a_pins: pwm_b_a { 515 mux { 516 groups = "pwm_b_a"; 517 function = "pwm_b"; 518 bias-disable; 519 }; 520 }; 521 522 pwm_b_x_pins: pwm_b_x { 523 mux { 524 groups = "pwm_b_x"; 525 function = "pwm_b"; 526 bias-disable; 527 }; 528 }; 529 530 pwm_b_z_pins: pwm_b_z { 531 mux { 532 groups = "pwm_b_z"; 533 function = "pwm_b"; 534 bias-disable; 535 }; 536 }; 537 538 pwm_c_a_pins: pwm_c_a { 539 mux { 540 groups = "pwm_c_a"; 541 function = "pwm_c"; 542 bias-disable; 543 }; 544 }; 545 546 pwm_c_x10_pins: pwm_c_x10 { 547 mux { 548 groups = "pwm_c_x10"; 549 function = "pwm_c"; 550 bias-disable; 551 }; 552 }; 553 554 pwm_c_x17_pins: pwm_c_x17 { 555 mux { 556 groups = "pwm_c_x17"; 557 function = "pwm_c"; 558 bias-disable; 559 }; 560 }; 561 562 pwm_d_x11_pins: pwm_d_x11 { 563 mux { 564 groups = "pwm_d_x11"; 565 function = "pwm_d"; 566 bias-disable; 567 }; 568 }; 569 570 pwm_d_x16_pins: pwm_d_x16 { 571 mux { 572 groups = "pwm_d_x16"; 573 function = "pwm_d"; 574 bias-disable; 575 }; 576 }; 577 578 sdio_pins: sdio { 579 mux-0 { 580 groups = "sdio_d0", 581 "sdio_d1", 582 "sdio_d2", 583 "sdio_d3", 584 "sdio_cmd"; 585 function = "sdio"; 586 bias-pull-up; 587 }; 588 589 mux-1 { 590 groups = "sdio_clk"; 591 function = "sdio"; 592 bias-disable; 593 }; 594 }; 595 596 sdio_clk_gate_pins: sdio_clk_gate { 597 mux { 598 groups = "GPIOX_4"; 599 function = "gpio_periphs"; 600 bias-pull-down; 601 }; 602 }; 603 604 spdif_in_z_pins: spdif_in_z { 605 mux { 606 groups = "spdif_in_z"; 607 function = "spdif_in"; 608 bias-disable; 609 }; 610 }; 611 612 spdif_in_a1_pins: spdif_in_a1 { 613 mux { 614 groups = "spdif_in_a1"; 615 function = "spdif_in"; 616 bias-disable; 617 }; 618 }; 619 620 spdif_in_a7_pins: spdif_in_a7 { 621 mux { 622 groups = "spdif_in_a7"; 623 function = "spdif_in"; 624 bias-disable; 625 }; 626 }; 627 628 spdif_in_a19_pins: spdif_in_a19 { 629 mux { 630 groups = "spdif_in_a19"; 631 function = "spdif_in"; 632 bias-disable; 633 }; 634 }; 635 636 spdif_in_a20_pins: spdif_in_a20 { 637 mux { 638 groups = "spdif_in_a20"; 639 function = "spdif_in"; 640 bias-disable; 641 }; 642 }; 643 644 spdif_out_a1_pins: spdif_out_a1 { 645 mux { 646 groups = "spdif_out_a1"; 647 function = "spdif_out"; 648 bias-disable; 649 }; 650 }; 651 652 spdif_out_a11_pins: spdif_out_a11 { 653 mux { 654 groups = "spdif_out_a11"; 655 function = "spdif_out"; 656 bias-disable; 657 }; 658 }; 659 660 spdif_out_a19_pins: spdif_out_a19 { 661 mux { 662 groups = "spdif_out_a19"; 663 function = "spdif_out"; 664 bias-disable; 665 }; 666 }; 667 668 spdif_out_a20_pins: spdif_out_a20 { 669 mux { 670 groups = "spdif_out_a20"; 671 function = "spdif_out"; 672 bias-disable; 673 }; 674 }; 675 676 spdif_out_z_pins: spdif_out_z { 677 mux { 678 groups = "spdif_out_z"; 679 function = "spdif_out"; 680 bias-disable; 681 }; 682 }; 683 684 spi0_pins: spi0 { 685 mux { 686 groups = "spi0_miso", 687 "spi0_mosi", 688 "spi0_clk"; 689 function = "spi0"; 690 bias-disable; 691 }; 692 }; 693 694 spi0_ss0_pins: spi0_ss0 { 695 mux { 696 groups = "spi0_ss0"; 697 function = "spi0"; 698 bias-disable; 699 }; 700 }; 701 702 spi0_ss1_pins: spi0_ss1 { 703 mux { 704 groups = "spi0_ss1"; 705 function = "spi0"; 706 bias-disable; 707 }; 708 }; 709 710 spi0_ss2_pins: spi0_ss2 { 711 mux { 712 groups = "spi0_ss2"; 713 function = "spi0"; 714 bias-disable; 715 }; 716 }; 717 718 spi1_a_pins: spi1_a { 719 mux { 720 groups = "spi1_miso_a", 721 "spi1_mosi_a", 722 "spi1_clk_a"; 723 function = "spi1"; 724 bias-disable; 725 }; 726 }; 727 728 spi1_ss0_a_pins: spi1_ss0_a { 729 mux { 730 groups = "spi1_ss0_a"; 731 function = "spi1"; 732 bias-disable; 733 }; 734 }; 735 736 spi1_ss1_pins: spi1_ss1 { 737 mux { 738 groups = "spi1_ss1"; 739 function = "spi1"; 740 bias-disable; 741 }; 742 }; 743 744 spi1_x_pins: spi1_x { 745 mux { 746 groups = "spi1_miso_x", 747 "spi1_mosi_x", 748 "spi1_clk_x"; 749 function = "spi1"; 750 bias-disable; 751 }; 752 }; 753 754 spi1_ss0_x_pins: spi1_ss0_x { 755 mux { 756 groups = "spi1_ss0_x"; 757 function = "spi1"; 758 bias-disable; 759 }; 760 }; 761 762 tdma_din0_pins: tdma_din0 { 763 mux { 764 groups = "tdma_din0"; 765 function = "tdma"; 766 bias-disable; 767 }; 768 }; 769 770 tdma_dout0_x14_pins: tdma_dout0_x14 { 771 mux { 772 groups = "tdma_dout0_x14"; 773 function = "tdma"; 774 bias-disable; 775 }; 776 }; 777 778 tdma_dout0_x15_pins: tdma_dout0_x15 { 779 mux { 780 groups = "tdma_dout0_x15"; 781 function = "tdma"; 782 bias-disable; 783 }; 784 }; 785 786 tdma_dout1_pins: tdma_dout1 { 787 mux { 788 groups = "tdma_dout1"; 789 function = "tdma"; 790 bias-disable; 791 }; 792 }; 793 794 tdma_din1_pins: tdma_din1 { 795 mux { 796 groups = "tdma_din1"; 797 function = "tdma"; 798 bias-disable; 799 }; 800 }; 801 802 tdma_fs_pins: tdma_fs { 803 mux { 804 groups = "tdma_fs"; 805 function = "tdma"; 806 bias-disable; 807 }; 808 }; 809 810 tdma_fs_slv_pins: tdma_fs_slv { 811 mux { 812 groups = "tdma_fs_slv"; 813 function = "tdma"; 814 bias-disable; 815 }; 816 }; 817 818 tdma_sclk_pins: tdma_sclk { 819 mux { 820 groups = "tdma_sclk"; 821 function = "tdma"; 822 bias-disable; 823 }; 824 }; 825 826 tdma_sclk_slv_pins: tdma_sclk_slv { 827 mux { 828 groups = "tdma_sclk_slv"; 829 function = "tdma"; 830 bias-disable; 831 }; 832 }; 833 834 tdmb_din0_pins: tdmb_din0 { 835 mux { 836 groups = "tdmb_din0"; 837 function = "tdmb"; 838 bias-disable; 839 }; 840 }; 841 842 tdmb_din1_pins: tdmb_din1 { 843 mux { 844 groups = "tdmb_din1"; 845 function = "tdmb"; 846 bias-disable; 847 }; 848 }; 849 850 tdmb_din2_pins: tdmb_din2 { 851 mux { 852 groups = "tdmb_din2"; 853 function = "tdmb"; 854 bias-disable; 855 }; 856 }; 857 858 tdmb_din3_pins: tdmb_din3 { 859 mux { 860 groups = "tdmb_din3"; 861 function = "tdmb"; 862 bias-disable; 863 }; 864 }; 865 866 tdmb_dout0_pins: tdmb_dout0 { 867 mux { 868 groups = "tdmb_dout0"; 869 function = "tdmb"; 870 bias-disable; 871 }; 872 }; 873 874 tdmb_dout1_pins: tdmb_dout1 { 875 mux { 876 groups = "tdmb_dout1"; 877 function = "tdmb"; 878 bias-disable; 879 }; 880 }; 881 882 tdmb_dout2_pins: tdmb_dout2 { 883 mux { 884 groups = "tdmb_dout2"; 885 function = "tdmb"; 886 bias-disable; 887 }; 888 }; 889 890 tdmb_dout3_pins: tdmb_dout3 { 891 mux { 892 groups = "tdmb_dout3"; 893 function = "tdmb"; 894 bias-disable; 895 }; 896 }; 897 898 tdmb_fs_pins: tdmb_fs { 899 mux { 900 groups = "tdmb_fs"; 901 function = "tdmb"; 902 bias-disable; 903 }; 904 }; 905 906 tdmb_fs_slv_pins: tdmb_fs_slv { 907 mux { 908 groups = "tdmb_fs_slv"; 909 function = "tdmb"; 910 bias-disable; 911 }; 912 }; 913 914 tdmb_sclk_pins: tdmb_sclk { 915 mux { 916 groups = "tdmb_sclk"; 917 function = "tdmb"; 918 bias-disable; 919 }; 920 }; 921 922 tdmb_sclk_slv_pins: tdmb_sclk_slv { 923 mux { 924 groups = "tdmb_sclk_slv"; 925 function = "tdmb"; 926 bias-disable; 927 }; 928 }; 929 930 tdmc_fs_pins: tdmc_fs { 931 mux { 932 groups = "tdmc_fs"; 933 function = "tdmc"; 934 bias-disable; 935 }; 936 }; 937 938 tdmc_fs_slv_pins: tdmc_fs_slv { 939 mux { 940 groups = "tdmc_fs_slv"; 941 function = "tdmc"; 942 bias-disable; 943 }; 944 }; 945 946 tdmc_sclk_pins: tdmc_sclk { 947 mux { 948 groups = "tdmc_sclk"; 949 function = "tdmc"; 950 bias-disable; 951 }; 952 }; 953 954 tdmc_sclk_slv_pins: tdmc_sclk_slv { 955 mux { 956 groups = "tdmc_sclk_slv"; 957 function = "tdmc"; 958 bias-disable; 959 }; 960 }; 961 962 tdmc_din0_pins: tdmc_din0 { 963 mux { 964 groups = "tdmc_din0"; 965 function = "tdmc"; 966 bias-disable; 967 }; 968 }; 969 970 tdmc_din1_pins: tdmc_din1 { 971 mux { 972 groups = "tdmc_din1"; 973 function = "tdmc"; 974 bias-disable; 975 }; 976 }; 977 978 tdmc_din2_pins: tdmc_din2 { 979 mux { 980 groups = "tdmc_din2"; 981 function = "tdmc"; 982 bias-disable; 983 }; 984 }; 985 986 tdmc_din3_pins: tdmc_din3 { 987 mux { 988 groups = "tdmc_din3"; 989 function = "tdmc"; 990 bias-disable; 991 }; 992 }; 993 994 tdmc_dout0_pins: tdmc_dout0 { 995 mux { 996 groups = "tdmc_dout0"; 997 function = "tdmc"; 998 bias-disable; 999 }; 1000 }; 1001 1002 tdmc_dout1_pins: tdmc_dout1 { 1003 mux { 1004 groups = "tdmc_dout1"; 1005 function = "tdmc"; 1006 bias-disable; 1007 }; 1008 }; 1009 1010 tdmc_dout2_pins: tdmc_dout2 { 1011 mux { 1012 groups = "tdmc_dout2"; 1013 function = "tdmc"; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 tdmc_dout3_pins: tdmc_dout3 { 1019 mux { 1020 groups = "tdmc_dout3"; 1021 function = "tdmc"; 1022 bias-disable; 1023 }; 1024 }; 1025 1026 uart_a_pins: uart_a { 1027 mux { 1028 groups = "uart_tx_a", 1029 "uart_rx_a"; 1030 function = "uart_a"; 1031 bias-disable; 1032 }; 1033 }; 1034 1035 uart_a_cts_rts_pins: uart_a_cts_rts { 1036 mux { 1037 groups = "uart_cts_a", 1038 "uart_rts_a"; 1039 function = "uart_a"; 1040 bias-disable; 1041 }; 1042 }; 1043 1044 uart_b_x_pins: uart_b_x { 1045 mux { 1046 groups = "uart_tx_b_x", 1047 "uart_rx_b_x"; 1048 function = "uart_b"; 1049 bias-disable; 1050 }; 1051 }; 1052 1053 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1054 mux { 1055 groups = "uart_cts_b_x", 1056 "uart_rts_b_x"; 1057 function = "uart_b"; 1058 bias-disable; 1059 }; 1060 }; 1061 1062 uart_b_z_pins: uart_b_z { 1063 mux { 1064 groups = "uart_tx_b_z", 1065 "uart_rx_b_z"; 1066 function = "uart_b"; 1067 bias-disable; 1068 }; 1069 }; 1070 1071 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1072 mux { 1073 groups = "uart_cts_b_z", 1074 "uart_rts_b_z"; 1075 function = "uart_b"; 1076 bias-disable; 1077 }; 1078 }; 1079 1080 uart_ao_b_z_pins: uart_ao_b_z { 1081 mux { 1082 groups = "uart_ao_tx_b_z", 1083 "uart_ao_rx_b_z"; 1084 function = "uart_ao_b_z"; 1085 bias-disable; 1086 }; 1087 }; 1088 1089 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1090 mux { 1091 groups = "uart_ao_cts_b_z", 1092 "uart_ao_rts_b_z"; 1093 function = "uart_ao_b_z"; 1094 bias-disable; 1095 }; 1096 }; 1097 }; 1098 }; 1099 1100 hiubus: bus@ff63c000 { 1101 compatible = "simple-bus"; 1102 reg = <0x0 0xff63c000 0x0 0x1c00>; 1103 #address-cells = <2>; 1104 #size-cells = <2>; 1105 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1106 1107 sysctrl: system-controller@0 { 1108 compatible = "amlogic,meson-axg-hhi-sysctrl", 1109 "simple-mfd", "syscon"; 1110 reg = <0 0 0 0x400>; 1111 1112 clkc: clock-controller { 1113 compatible = "amlogic,axg-clkc"; 1114 #clock-cells = <1>; 1115 clocks = <&xtal>; 1116 clock-names = "xtal"; 1117 }; 1118 }; 1119 }; 1120 1121 mailbox: mailbox@ff63c404 { 1122 compatible = "amlogic,meson-gxbb-mhu"; 1123 reg = <0 0xff63c404 0 0x4c>; 1124 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1125 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1126 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1127 #mbox-cells = <1>; 1128 }; 1129 1130 audio: bus@ff642000 { 1131 compatible = "simple-bus"; 1132 reg = <0x0 0xff642000 0x0 0x2000>; 1133 #address-cells = <2>; 1134 #size-cells = <2>; 1135 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1136 1137 clkc_audio: clock-controller@0 { 1138 compatible = "amlogic,axg-audio-clkc"; 1139 reg = <0x0 0x0 0x0 0xb4>; 1140 #clock-cells = <1>; 1141 1142 clocks = <&clkc CLKID_AUDIO>, 1143 <&clkc CLKID_MPLL0>, 1144 <&clkc CLKID_MPLL1>, 1145 <&clkc CLKID_MPLL2>, 1146 <&clkc CLKID_MPLL3>, 1147 <&clkc CLKID_HIFI_PLL>, 1148 <&clkc CLKID_FCLK_DIV3>, 1149 <&clkc CLKID_FCLK_DIV4>, 1150 <&clkc CLKID_GP0_PLL>; 1151 clock-names = "pclk", 1152 "mst_in0", 1153 "mst_in1", 1154 "mst_in2", 1155 "mst_in3", 1156 "mst_in4", 1157 "mst_in5", 1158 "mst_in6", 1159 "mst_in7"; 1160 1161 resets = <&reset RESET_AUDIO>; 1162 }; 1163 1164 toddr_a: audio-controller@100 { 1165 compatible = "amlogic,axg-toddr"; 1166 reg = <0x0 0x100 0x0 0x2c>; 1167 #sound-dai-cells = <0>; 1168 sound-name-prefix = "TODDR_A"; 1169 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1170 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1171 resets = <&arb AXG_ARB_TODDR_A>; 1172 amlogic,fifo-depth = <512>; 1173 status = "disabled"; 1174 }; 1175 1176 toddr_b: audio-controller@140 { 1177 compatible = "amlogic,axg-toddr"; 1178 reg = <0x0 0x140 0x0 0x2c>; 1179 #sound-dai-cells = <0>; 1180 sound-name-prefix = "TODDR_B"; 1181 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1182 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1183 resets = <&arb AXG_ARB_TODDR_B>; 1184 amlogic,fifo-depth = <256>; 1185 status = "disabled"; 1186 }; 1187 1188 toddr_c: audio-controller@180 { 1189 compatible = "amlogic,axg-toddr"; 1190 reg = <0x0 0x180 0x0 0x2c>; 1191 #sound-dai-cells = <0>; 1192 sound-name-prefix = "TODDR_C"; 1193 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1194 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1195 resets = <&arb AXG_ARB_TODDR_C>; 1196 amlogic,fifo-depth = <256>; 1197 status = "disabled"; 1198 }; 1199 1200 frddr_a: audio-controller@1c0 { 1201 compatible = "amlogic,axg-frddr"; 1202 reg = <0x0 0x1c0 0x0 0x2c>; 1203 #sound-dai-cells = <0>; 1204 sound-name-prefix = "FRDDR_A"; 1205 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1206 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1207 resets = <&arb AXG_ARB_FRDDR_A>; 1208 amlogic,fifo-depth = <512>; 1209 status = "disabled"; 1210 }; 1211 1212 frddr_b: audio-controller@200 { 1213 compatible = "amlogic,axg-frddr"; 1214 reg = <0x0 0x200 0x0 0x2c>; 1215 #sound-dai-cells = <0>; 1216 sound-name-prefix = "FRDDR_B"; 1217 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1218 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1219 resets = <&arb AXG_ARB_FRDDR_B>; 1220 amlogic,fifo-depth = <256>; 1221 status = "disabled"; 1222 }; 1223 1224 frddr_c: audio-controller@240 { 1225 compatible = "amlogic,axg-frddr"; 1226 reg = <0x0 0x240 0x0 0x2c>; 1227 #sound-dai-cells = <0>; 1228 sound-name-prefix = "FRDDR_C"; 1229 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1230 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1231 resets = <&arb AXG_ARB_FRDDR_C>; 1232 amlogic,fifo-depth = <256>; 1233 status = "disabled"; 1234 }; 1235 1236 arb: reset-controller@280 { 1237 compatible = "amlogic,meson-axg-audio-arb"; 1238 reg = <0x0 0x280 0x0 0x4>; 1239 #reset-cells = <1>; 1240 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1241 }; 1242 1243 tdmin_a: audio-controller@300 { 1244 compatible = "amlogic,axg-tdmin"; 1245 reg = <0x0 0x300 0x0 0x40>; 1246 sound-name-prefix = "TDMIN_A"; 1247 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1248 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1249 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1250 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1251 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1252 clock-names = "pclk", "sclk", "sclk_sel", 1253 "lrclk", "lrclk_sel"; 1254 status = "disabled"; 1255 }; 1256 1257 tdmin_b: audio-controller@340 { 1258 compatible = "amlogic,axg-tdmin"; 1259 reg = <0x0 0x340 0x0 0x40>; 1260 sound-name-prefix = "TDMIN_B"; 1261 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1262 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1263 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1264 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1265 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1266 clock-names = "pclk", "sclk", "sclk_sel", 1267 "lrclk", "lrclk_sel"; 1268 status = "disabled"; 1269 }; 1270 1271 tdmin_c: audio-controller@380 { 1272 compatible = "amlogic,axg-tdmin"; 1273 reg = <0x0 0x380 0x0 0x40>; 1274 sound-name-prefix = "TDMIN_C"; 1275 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1276 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1277 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1278 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1279 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1280 clock-names = "pclk", "sclk", "sclk_sel", 1281 "lrclk", "lrclk_sel"; 1282 status = "disabled"; 1283 }; 1284 1285 tdmin_lb: audio-controller@3c0 { 1286 compatible = "amlogic,axg-tdmin"; 1287 reg = <0x0 0x3c0 0x0 0x40>; 1288 sound-name-prefix = "TDMIN_LB"; 1289 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1290 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1291 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1292 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1293 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1294 clock-names = "pclk", "sclk", "sclk_sel", 1295 "lrclk", "lrclk_sel"; 1296 status = "disabled"; 1297 }; 1298 1299 spdifin: audio-controller@400 { 1300 compatible = "amlogic,axg-spdifin"; 1301 reg = <0x0 0x400 0x0 0x30>; 1302 #sound-dai-cells = <0>; 1303 sound-name-prefix = "SPDIFIN"; 1304 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1305 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1306 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1307 clock-names = "pclk", "refclk"; 1308 status = "disabled"; 1309 }; 1310 1311 spdifout: audio-controller@480 { 1312 compatible = "amlogic,axg-spdifout"; 1313 reg = <0x0 0x480 0x0 0x50>; 1314 #sound-dai-cells = <0>; 1315 sound-name-prefix = "SPDIFOUT"; 1316 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1317 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1318 clock-names = "pclk", "mclk"; 1319 status = "disabled"; 1320 }; 1321 1322 tdmout_a: audio-controller@500 { 1323 compatible = "amlogic,axg-tdmout"; 1324 reg = <0x0 0x500 0x0 0x40>; 1325 sound-name-prefix = "TDMOUT_A"; 1326 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1327 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1328 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1329 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1330 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1331 clock-names = "pclk", "sclk", "sclk_sel", 1332 "lrclk", "lrclk_sel"; 1333 status = "disabled"; 1334 }; 1335 1336 tdmout_b: audio-controller@540 { 1337 compatible = "amlogic,axg-tdmout"; 1338 reg = <0x0 0x540 0x0 0x40>; 1339 sound-name-prefix = "TDMOUT_B"; 1340 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1341 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1342 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1343 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1344 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1345 clock-names = "pclk", "sclk", "sclk_sel", 1346 "lrclk", "lrclk_sel"; 1347 status = "disabled"; 1348 }; 1349 1350 tdmout_c: audio-controller@580 { 1351 compatible = "amlogic,axg-tdmout"; 1352 reg = <0x0 0x580 0x0 0x40>; 1353 sound-name-prefix = "TDMOUT_C"; 1354 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1355 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1356 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1357 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1358 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1359 clock-names = "pclk", "sclk", "sclk_sel", 1360 "lrclk", "lrclk_sel"; 1361 status = "disabled"; 1362 }; 1363 }; 1364 1365 aobus: bus@ff800000 { 1366 compatible = "simple-bus"; 1367 reg = <0x0 0xff800000 0x0 0x100000>; 1368 #address-cells = <2>; 1369 #size-cells = <2>; 1370 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1371 1372 sysctrl_AO: sys-ctrl@0 { 1373 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1374 reg = <0x0 0x0 0x0 0x100>; 1375 1376 clkc_AO: clock-controller { 1377 compatible = "amlogic,meson-axg-aoclkc"; 1378 #clock-cells = <1>; 1379 #reset-cells = <1>; 1380 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1381 clock-names = "xtal", "mpeg-clk"; 1382 }; 1383 }; 1384 1385 pinctrl_aobus: pinctrl@14 { 1386 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1387 #address-cells = <2>; 1388 #size-cells = <2>; 1389 ranges; 1390 1391 gpio_ao: bank@14 { 1392 reg = <0x0 0x00014 0x0 0x8>, 1393 <0x0 0x0002c 0x0 0x4>, 1394 <0x0 0x00024 0x0 0x8>; 1395 reg-names = "mux", "pull", "gpio"; 1396 gpio-controller; 1397 #gpio-cells = <2>; 1398 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1399 }; 1400 1401 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1402 mux { 1403 groups = "i2c_ao_sck_4"; 1404 function = "i2c_ao"; 1405 bias-disable; 1406 }; 1407 }; 1408 1409 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1410 mux { 1411 groups = "i2c_ao_sck_8"; 1412 function = "i2c_ao"; 1413 bias-disable; 1414 }; 1415 }; 1416 1417 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1418 mux { 1419 groups = "i2c_ao_sck_10"; 1420 function = "i2c_ao"; 1421 bias-disable; 1422 }; 1423 }; 1424 1425 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1426 mux { 1427 groups = "i2c_ao_sda_5"; 1428 function = "i2c_ao"; 1429 bias-disable; 1430 }; 1431 }; 1432 1433 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1434 mux { 1435 groups = "i2c_ao_sda_9"; 1436 function = "i2c_ao"; 1437 bias-disable; 1438 }; 1439 }; 1440 1441 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1442 mux { 1443 groups = "i2c_ao_sda_11"; 1444 function = "i2c_ao"; 1445 bias-disable; 1446 }; 1447 }; 1448 1449 remote_input_ao_pins: remote_input_ao { 1450 mux { 1451 groups = "remote_input_ao"; 1452 function = "remote_input_ao"; 1453 bias-disable; 1454 }; 1455 }; 1456 1457 uart_ao_a_pins: uart_ao_a { 1458 mux { 1459 groups = "uart_ao_tx_a", 1460 "uart_ao_rx_a"; 1461 function = "uart_ao_a"; 1462 bias-disable; 1463 }; 1464 }; 1465 1466 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1467 mux { 1468 groups = "uart_ao_cts_a", 1469 "uart_ao_rts_a"; 1470 function = "uart_ao_a"; 1471 bias-disable; 1472 }; 1473 }; 1474 1475 uart_ao_b_pins: uart_ao_b { 1476 mux { 1477 groups = "uart_ao_tx_b", 1478 "uart_ao_rx_b"; 1479 function = "uart_ao_b"; 1480 bias-disable; 1481 }; 1482 }; 1483 1484 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1485 mux { 1486 groups = "uart_ao_cts_b", 1487 "uart_ao_rts_b"; 1488 function = "uart_ao_b"; 1489 bias-disable; 1490 }; 1491 }; 1492 }; 1493 1494 sec_AO: ao-secure@140 { 1495 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1496 reg = <0x0 0x140 0x0 0x140>; 1497 amlogic,has-chip-id; 1498 }; 1499 1500 pwm_AO_cd: pwm@2000 { 1501 compatible = "amlogic,meson-axg-ao-pwm"; 1502 reg = <0x0 0x02000 0x0 0x20>; 1503 #pwm-cells = <3>; 1504 status = "disabled"; 1505 }; 1506 1507 uart_AO: serial@3000 { 1508 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1509 reg = <0x0 0x3000 0x0 0x18>; 1510 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1511 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1512 clock-names = "xtal", "pclk", "baud"; 1513 status = "disabled"; 1514 }; 1515 1516 uart_AO_B: serial@4000 { 1517 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1518 reg = <0x0 0x4000 0x0 0x18>; 1519 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1520 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1521 clock-names = "xtal", "pclk", "baud"; 1522 status = "disabled"; 1523 }; 1524 1525 i2c_AO: i2c@5000 { 1526 compatible = "amlogic,meson-axg-i2c"; 1527 reg = <0x0 0x05000 0x0 0x20>; 1528 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1529 clocks = <&clkc CLKID_AO_I2C>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 pwm_AO_ab: pwm@7000 { 1536 compatible = "amlogic,meson-axg-ao-pwm"; 1537 reg = <0x0 0x07000 0x0 0x20>; 1538 #pwm-cells = <3>; 1539 status = "disabled"; 1540 }; 1541 1542 ir: ir@8000 { 1543 compatible = "amlogic,meson-gxbb-ir"; 1544 reg = <0x0 0x8000 0x0 0x20>; 1545 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1546 status = "disabled"; 1547 }; 1548 1549 saradc: adc@9000 { 1550 compatible = "amlogic,meson-axg-saradc", 1551 "amlogic,meson-saradc"; 1552 reg = <0x0 0x9000 0x0 0x38>; 1553 #io-channel-cells = <1>; 1554 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1555 clocks = <&xtal>, 1556 <&clkc_AO CLKID_AO_SAR_ADC>, 1557 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1558 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1559 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1560 status = "disabled"; 1561 }; 1562 }; 1563 1564 gic: interrupt-controller@ffc01000 { 1565 compatible = "arm,gic-400"; 1566 reg = <0x0 0xffc01000 0 0x1000>, 1567 <0x0 0xffc02000 0 0x2000>, 1568 <0x0 0xffc04000 0 0x2000>, 1569 <0x0 0xffc06000 0 0x2000>; 1570 interrupt-controller; 1571 interrupts = <GIC_PPI 9 1572 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1573 #interrupt-cells = <3>; 1574 #address-cells = <0>; 1575 }; 1576 1577 cbus: bus@ffd00000 { 1578 compatible = "simple-bus"; 1579 reg = <0x0 0xffd00000 0x0 0x25000>; 1580 #address-cells = <2>; 1581 #size-cells = <2>; 1582 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1583 1584 reset: reset-controller@1004 { 1585 compatible = "amlogic,meson-axg-reset"; 1586 reg = <0x0 0x01004 0x0 0x9c>; 1587 #reset-cells = <1>; 1588 }; 1589 1590 gpio_intc: interrupt-controller@f080 { 1591 compatible = "amlogic,meson-axg-gpio-intc", 1592 "amlogic,meson-gpio-intc"; 1593 reg = <0x0 0xf080 0x0 0x10>; 1594 interrupt-controller; 1595 #interrupt-cells = <2>; 1596 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1597 }; 1598 1599 watchdog@f0d0 { 1600 compatible = "amlogic,meson-gxbb-wdt"; 1601 reg = <0x0 0xf0d0 0x0 0x10>; 1602 clocks = <&xtal>; 1603 }; 1604 1605 pwm_ab: pwm@1b000 { 1606 compatible = "amlogic,meson-axg-ee-pwm"; 1607 reg = <0x0 0x1b000 0x0 0x20>; 1608 #pwm-cells = <3>; 1609 status = "disabled"; 1610 }; 1611 1612 pwm_cd: pwm@1a000 { 1613 compatible = "amlogic,meson-axg-ee-pwm"; 1614 reg = <0x0 0x1a000 0x0 0x20>; 1615 #pwm-cells = <3>; 1616 status = "disabled"; 1617 }; 1618 1619 spicc0: spi@13000 { 1620 compatible = "amlogic,meson-axg-spicc"; 1621 reg = <0x0 0x13000 0x0 0x3c>; 1622 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&clkc CLKID_SPICC0>; 1624 clock-names = "core"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 spicc1: spi@15000 { 1631 compatible = "amlogic,meson-axg-spicc"; 1632 reg = <0x0 0x15000 0x0 0x3c>; 1633 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&clkc CLKID_SPICC1>; 1635 clock-names = "core"; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 clk_msr: clock-measure@18000 { 1642 compatible = "amlogic,meson-axg-clk-measure"; 1643 reg = <0x0 0x18000 0x0 0x10>; 1644 }; 1645 1646 i2c3: i2c@1c000 { 1647 compatible = "amlogic,meson-axg-i2c"; 1648 reg = <0x0 0x1c000 0x0 0x20>; 1649 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1650 clocks = <&clkc CLKID_I2C>; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 status = "disabled"; 1654 }; 1655 1656 i2c2: i2c@1d000 { 1657 compatible = "amlogic,meson-axg-i2c"; 1658 reg = <0x0 0x1d000 0x0 0x20>; 1659 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1660 clocks = <&clkc CLKID_I2C>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c1: i2c@1e000 { 1667 compatible = "amlogic,meson-axg-i2c"; 1668 reg = <0x0 0x1e000 0x0 0x20>; 1669 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1670 clocks = <&clkc CLKID_I2C>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 i2c0: i2c@1f000 { 1677 compatible = "amlogic,meson-axg-i2c"; 1678 reg = <0x0 0x1f000 0x0 0x20>; 1679 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1680 clocks = <&clkc CLKID_I2C>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 status = "disabled"; 1684 }; 1685 1686 uart_B: serial@23000 { 1687 compatible = "amlogic,meson-gx-uart"; 1688 reg = <0x0 0x23000 0x0 0x18>; 1689 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1690 status = "disabled"; 1691 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1692 clock-names = "xtal", "pclk", "baud"; 1693 }; 1694 1695 uart_A: serial@24000 { 1696 compatible = "amlogic,meson-gx-uart"; 1697 reg = <0x0 0x24000 0x0 0x18>; 1698 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1699 status = "disabled"; 1700 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1701 clock-names = "xtal", "pclk", "baud"; 1702 }; 1703 }; 1704 1705 apb: bus@ffe00000 { 1706 compatible = "simple-bus"; 1707 reg = <0x0 0xffe00000 0x0 0x200000>; 1708 #address-cells = <2>; 1709 #size-cells = <2>; 1710 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1711 1712 sd_emmc_b: sd@5000 { 1713 compatible = "amlogic,meson-axg-mmc"; 1714 reg = <0x0 0x5000 0x0 0x800>; 1715 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1716 status = "disabled"; 1717 clocks = <&clkc CLKID_SD_EMMC_B>, 1718 <&clkc CLKID_SD_EMMC_B_CLK0>, 1719 <&clkc CLKID_FCLK_DIV2>; 1720 clock-names = "core", "clkin0", "clkin1"; 1721 resets = <&reset RESET_SD_EMMC_B>; 1722 }; 1723 1724 sd_emmc_c: mmc@7000 { 1725 compatible = "amlogic,meson-axg-mmc"; 1726 reg = <0x0 0x7000 0x0 0x800>; 1727 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1728 status = "disabled"; 1729 clocks = <&clkc CLKID_SD_EMMC_C>, 1730 <&clkc CLKID_SD_EMMC_C_CLK0>, 1731 <&clkc CLKID_FCLK_DIV2>; 1732 clock-names = "core", "clkin0", "clkin1"; 1733 resets = <&reset RESET_SD_EMMC_C>; 1734 }; 1735 }; 1736 1737 sram: sram@fffc0000 { 1738 compatible = "mmio-sram"; 1739 reg = <0x0 0xfffc0000 0x0 0x20000>; 1740 #address-cells = <1>; 1741 #size-cells = <1>; 1742 ranges = <0 0x0 0xfffc0000 0x20000>; 1743 1744 cpu_scp_lpri: scp-sram@13000 { 1745 compatible = "amlogic,meson-axg-scp-shmem"; 1746 reg = <0x13000 0x400>; 1747 }; 1748 1749 cpu_scp_hpri: scp-sram@13400 { 1750 compatible = "amlogic,meson-axg-scp-shmem"; 1751 reg = <0x13400 0x400>; 1752 }; 1753 }; 1754 }; 1755 1756 timer { 1757 compatible = "arm,armv8-timer"; 1758 interrupts = <GIC_PPI 13 1759 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1760 <GIC_PPI 14 1761 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1762 <GIC_PPI 11 1763 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1764 <GIC_PPI 10 1765 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1766 }; 1767 1768 xtal: xtal-clk { 1769 compatible = "fixed-clock"; 1770 clock-frequency = <24000000>; 1771 clock-output-names = "xtal"; 1772 #clock-cells = <0>; 1773 }; 1774}; 1775