1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 ao_alt_xtal: ao_alt_xtal-clk { 57 compatible = "fixed-clock"; 58 clock-frequency = <32000000>; 59 clock-output-names = "ao_alt_xtal"; 60 #clock-cells = <0>; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu1: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53", "arm,armv8"; 87 reg = <0x0 0x1>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 cpu2: cpu@2 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 reg = <0x0 0x2>; 96 enable-method = "psci"; 97 next-level-cache = <&l2>; 98 }; 99 100 cpu3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53", "arm,armv8"; 103 reg = <0x0 0x3>; 104 enable-method = "psci"; 105 next-level-cache = <&l2>; 106 }; 107 108 l2: l2-cache0 { 109 compatible = "cache"; 110 }; 111 }; 112 113 sm: secure-monitor { 114 compatible = "amlogic,meson-gxbb-sm"; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 reserved-memory { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 /* 16 MiB reserved for Hardware ROM Firmware */ 128 hwrom_reserved: hwrom@0 { 129 reg = <0x0 0x0 0x0 0x1000000>; 130 no-map; 131 }; 132 133 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 134 secmon_reserved: secmon@5000000 { 135 reg = <0x0 0x05000000 0x0 0x300000>; 136 no-map; 137 }; 138 }; 139 140 soc { 141 compatible = "simple-bus"; 142 #address-cells = <2>; 143 #size-cells = <2>; 144 ranges; 145 146 ethmac: ethernet@ff3f0000 { 147 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 148 reg = <0x0 0xff3f0000 0x0 0x10000 149 0x0 0xff634540 0x0 0x8>; 150 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 151 interrupt-names = "macirq"; 152 clocks = <&clkc CLKID_ETH>, 153 <&clkc CLKID_FCLK_DIV2>, 154 <&clkc CLKID_MPLL2>; 155 clock-names = "stmmaceth", "clkin0", "clkin1"; 156 status = "disabled"; 157 }; 158 159 pdm: audio-controller@ff632000 { 160 compatible = "amlogic,axg-pdm"; 161 reg = <0x0 0xff632000 0x0 0x34>; 162 #sound-dai-cells = <0>; 163 sound-name-prefix = "PDM"; 164 clocks = <&clkc_audio AUD_CLKID_PDM>, 165 <&clkc_audio AUD_CLKID_PDM_DCLK>, 166 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 167 clock-names = "pclk", "dclk", "sysclk"; 168 status = "disabled"; 169 }; 170 171 periphs: bus@ff634000 { 172 compatible = "simple-bus"; 173 reg = <0x0 0xff634000 0x0 0x2000>; 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 177 178 hwrng: rng@18 { 179 compatible = "amlogic,meson-rng"; 180 reg = <0x0 0x18 0x0 0x4>; 181 clocks = <&clkc CLKID_RNG0>; 182 clock-names = "core"; 183 }; 184 185 pinctrl_periphs: pinctrl@480 { 186 compatible = "amlogic,meson-axg-periphs-pinctrl"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 gpio: bank@480 { 192 reg = <0x0 0x00480 0x0 0x40>, 193 <0x0 0x004e8 0x0 0x14>, 194 <0x0 0x00520 0x0 0x14>, 195 <0x0 0x00430 0x0 0x3c>; 196 reg-names = "mux", "pull", "pull-enable", "gpio"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 gpio-ranges = <&pinctrl_periphs 0 0 86>; 200 }; 201 202 i2c0_pins: i2c0 { 203 mux { 204 groups = "i2c0_sck", 205 "i2c0_sda"; 206 function = "i2c0"; 207 }; 208 }; 209 210 i2c1_x_pins: i2c1_x { 211 mux { 212 groups = "i2c1_sck_x", 213 "i2c1_sda_x"; 214 function = "i2c1"; 215 }; 216 }; 217 218 i2c1_z_pins: i2c1_z { 219 mux { 220 groups = "i2c1_sck_z", 221 "i2c1_sda_z"; 222 function = "i2c1"; 223 }; 224 }; 225 226 i2c2_a_pins: i2c2_a { 227 mux { 228 groups = "i2c2_sck_a", 229 "i2c2_sda_a"; 230 function = "i2c2"; 231 }; 232 }; 233 234 i2c2_x_pins: i2c2_x { 235 mux { 236 groups = "i2c2_sck_x", 237 "i2c2_sda_x"; 238 function = "i2c2"; 239 }; 240 }; 241 242 i2c3_a6_pins: i2c3_a6 { 243 mux { 244 groups = "i2c3_sda_a6", 245 "i2c3_sck_a7"; 246 function = "i2c3"; 247 }; 248 }; 249 250 i2c3_a12_pins: i2c3_a12 { 251 mux { 252 groups = "i2c3_sda_a12", 253 "i2c3_sck_a13"; 254 function = "i2c3"; 255 }; 256 }; 257 258 i2c3_a19_pins: i2c3_a19 { 259 mux { 260 groups = "i2c3_sda_a19", 261 "i2c3_sck_a20"; 262 function = "i2c3"; 263 }; 264 }; 265 266 emmc_pins: emmc { 267 mux { 268 groups = "emmc_nand_d0", 269 "emmc_nand_d1", 270 "emmc_nand_d2", 271 "emmc_nand_d3", 272 "emmc_nand_d4", 273 "emmc_nand_d5", 274 "emmc_nand_d6", 275 "emmc_nand_d7", 276 "emmc_clk", 277 "emmc_cmd", 278 "emmc_ds"; 279 function = "emmc"; 280 }; 281 }; 282 283 emmc_clk_gate_pins: emmc_clk_gate { 284 mux { 285 groups = "BOOT_8"; 286 function = "gpio_periphs"; 287 }; 288 cfg-pull-down { 289 pins = "BOOT_8"; 290 bias-pull-down; 291 }; 292 }; 293 294 eth_rgmii_x_pins: eth-x-rgmii { 295 mux { 296 groups = "eth_mdio_x", 297 "eth_mdc_x", 298 "eth_rgmii_rx_clk_x", 299 "eth_rx_dv_x", 300 "eth_rxd0_x", 301 "eth_rxd1_x", 302 "eth_rxd2_rgmii", 303 "eth_rxd3_rgmii", 304 "eth_rgmii_tx_clk", 305 "eth_txen_x", 306 "eth_txd0_x", 307 "eth_txd1_x", 308 "eth_txd2_rgmii", 309 "eth_txd3_rgmii"; 310 function = "eth"; 311 }; 312 }; 313 314 eth_rgmii_y_pins: eth-y-rgmii { 315 mux { 316 groups = "eth_mdio_y", 317 "eth_mdc_y", 318 "eth_rgmii_rx_clk_y", 319 "eth_rx_dv_y", 320 "eth_rxd0_y", 321 "eth_rxd1_y", 322 "eth_rxd2_rgmii", 323 "eth_rxd3_rgmii", 324 "eth_rgmii_tx_clk", 325 "eth_txen_y", 326 "eth_txd0_y", 327 "eth_txd1_y", 328 "eth_txd2_rgmii", 329 "eth_txd3_rgmii"; 330 function = "eth"; 331 }; 332 }; 333 334 eth_rmii_x_pins: eth-x-rmii { 335 mux { 336 groups = "eth_mdio_x", 337 "eth_mdc_x", 338 "eth_rgmii_rx_clk_x", 339 "eth_rx_dv_x", 340 "eth_rxd0_x", 341 "eth_rxd1_x", 342 "eth_txen_x", 343 "eth_txd0_x", 344 "eth_txd1_x"; 345 function = "eth"; 346 }; 347 }; 348 349 eth_rmii_y_pins: eth-y-rmii { 350 mux { 351 groups = "eth_mdio_y", 352 "eth_mdc_y", 353 "eth_rgmii_rx_clk_y", 354 "eth_rx_dv_y", 355 "eth_rxd0_y", 356 "eth_rxd1_y", 357 "eth_txen_y", 358 "eth_txd0_y", 359 "eth_txd1_y"; 360 function = "eth"; 361 }; 362 }; 363 364 mclk_b_pins: mclk_b { 365 mux { 366 groups = "mclk_b"; 367 function = "mclk_b"; 368 }; 369 }; 370 371 mclk_c_pins: mclk_c { 372 mux { 373 groups = "mclk_c"; 374 function = "mclk_c"; 375 }; 376 }; 377 378 pdm_dclk_a14_pins: pdm_dclk_a14 { 379 mux { 380 groups = "pdm_dclk_a14"; 381 function = "pdm"; 382 }; 383 }; 384 385 pdm_dclk_a19_pins: pdm_dclk_a19 { 386 mux { 387 groups = "pdm_dclk_a19"; 388 function = "pdm"; 389 }; 390 }; 391 392 pdm_din0_pins: pdm_din0 { 393 mux { 394 groups = "pdm_din0"; 395 function = "pdm"; 396 }; 397 }; 398 399 pdm_din1_pins: pdm_din1 { 400 mux { 401 groups = "pdm_din1"; 402 function = "pdm"; 403 }; 404 }; 405 406 pdm_din2_pins: pdm_din2 { 407 mux { 408 groups = "pdm_din2"; 409 function = "pdm"; 410 }; 411 }; 412 413 pdm_din3_pins: pdm_din3 { 414 mux { 415 groups = "pdm_din3"; 416 function = "pdm"; 417 }; 418 }; 419 420 pwm_a_a_pins: pwm_a_a { 421 mux { 422 groups = "pwm_a_a"; 423 function = "pwm_a"; 424 }; 425 }; 426 427 pwm_a_x18_pins: pwm_a_x18 { 428 mux { 429 groups = "pwm_a_x18"; 430 function = "pwm_a"; 431 }; 432 }; 433 434 pwm_a_x20_pins: pwm_a_x20 { 435 mux { 436 groups = "pwm_a_x20"; 437 function = "pwm_a"; 438 }; 439 }; 440 441 pwm_a_z_pins: pwm_a_z { 442 mux { 443 groups = "pwm_a_z"; 444 function = "pwm_a"; 445 }; 446 }; 447 448 pwm_b_a_pins: pwm_b_a { 449 mux { 450 groups = "pwm_b_a"; 451 function = "pwm_b"; 452 }; 453 }; 454 455 pwm_b_x_pins: pwm_b_x { 456 mux { 457 groups = "pwm_b_x"; 458 function = "pwm_b"; 459 }; 460 }; 461 462 pwm_b_z_pins: pwm_b_z { 463 mux { 464 groups = "pwm_b_z"; 465 function = "pwm_b"; 466 }; 467 }; 468 469 pwm_c_a_pins: pwm_c_a { 470 mux { 471 groups = "pwm_c_a"; 472 function = "pwm_c"; 473 }; 474 }; 475 476 pwm_c_x10_pins: pwm_c_x10 { 477 mux { 478 groups = "pwm_c_x10"; 479 function = "pwm_c"; 480 }; 481 }; 482 483 pwm_c_x17_pins: pwm_c_x17 { 484 mux { 485 groups = "pwm_c_x17"; 486 function = "pwm_c"; 487 }; 488 }; 489 490 pwm_d_x11_pins: pwm_d_x11 { 491 mux { 492 groups = "pwm_d_x11"; 493 function = "pwm_d"; 494 }; 495 }; 496 497 pwm_d_x16_pins: pwm_d_x16 { 498 mux { 499 groups = "pwm_d_x16"; 500 function = "pwm_d"; 501 }; 502 }; 503 504 sdio_pins: sdio { 505 mux { 506 groups = "sdio_d0", 507 "sdio_d1", 508 "sdio_d2", 509 "sdio_d3", 510 "sdio_cmd", 511 "sdio_clk"; 512 function = "sdio"; 513 }; 514 }; 515 516 sdio_clk_gate_pins: sdio_clk_gate { 517 mux { 518 groups = "GPIOX_4"; 519 function = "gpio_periphs"; 520 }; 521 cfg-pull-down { 522 pins = "GPIOX_4"; 523 bias-pull-down; 524 }; 525 }; 526 527 spdif_in_z_pins: spdif_in_z { 528 mux { 529 groups = "spdif_in_z"; 530 function = "spdif_in"; 531 }; 532 }; 533 534 spdif_in_a1_pins: spdif_in_a1 { 535 mux { 536 groups = "spdif_in_a1"; 537 function = "spdif_in"; 538 }; 539 }; 540 541 spdif_in_a7_pins: spdif_in_a7 { 542 mux { 543 groups = "spdif_in_a7"; 544 function = "spdif_in"; 545 }; 546 }; 547 548 spdif_in_a19_pins: spdif_in_a19 { 549 mux { 550 groups = "spdif_in_a19"; 551 function = "spdif_in"; 552 }; 553 }; 554 555 spdif_in_a20_pins: spdif_in_a20 { 556 mux { 557 groups = "spdif_in_a20"; 558 function = "spdif_in"; 559 }; 560 }; 561 562 spdif_out_a1_pins: spdif_out_a1 { 563 mux { 564 groups = "spdif_out_a1"; 565 function = "spdif_out"; 566 }; 567 }; 568 569 spdif_out_a11_pins: spdif_out_a11 { 570 mux { 571 groups = "spdif_out_a11"; 572 function = "spdif_out"; 573 }; 574 }; 575 576 spdif_out_a19_pins: spdif_out_a19 { 577 mux { 578 groups = "spdif_out_a19"; 579 function = "spdif_out"; 580 }; 581 }; 582 583 spdif_out_a20_pins: spdif_out_a20 { 584 mux { 585 groups = "spdif_out_a20"; 586 function = "spdif_out"; 587 }; 588 }; 589 590 spdif_out_z_pins: spdif_out_z { 591 mux { 592 groups = "spdif_out_z"; 593 function = "spdif_out"; 594 }; 595 }; 596 597 spi0_pins: spi0 { 598 mux { 599 groups = "spi0_miso", 600 "spi0_mosi", 601 "spi0_clk"; 602 function = "spi0"; 603 }; 604 }; 605 606 spi0_ss0_pins: spi0_ss0 { 607 mux { 608 groups = "spi0_ss0"; 609 function = "spi0"; 610 }; 611 }; 612 613 spi0_ss1_pins: spi0_ss1 { 614 mux { 615 groups = "spi0_ss1"; 616 function = "spi0"; 617 }; 618 }; 619 620 spi0_ss2_pins: spi0_ss2 { 621 mux { 622 groups = "spi0_ss2"; 623 function = "spi0"; 624 }; 625 }; 626 627 spi1_a_pins: spi1_a { 628 mux { 629 groups = "spi1_miso_a", 630 "spi1_mosi_a", 631 "spi1_clk_a"; 632 function = "spi1"; 633 }; 634 }; 635 636 spi1_ss0_a_pins: spi1_ss0_a { 637 mux { 638 groups = "spi1_ss0_a"; 639 function = "spi1"; 640 }; 641 }; 642 643 spi1_ss1_pins: spi1_ss1 { 644 mux { 645 groups = "spi1_ss1"; 646 function = "spi1"; 647 }; 648 }; 649 650 spi1_x_pins: spi1_x { 651 mux { 652 groups = "spi1_miso_x", 653 "spi1_mosi_x", 654 "spi1_clk_x"; 655 function = "spi1"; 656 }; 657 }; 658 659 spi1_ss0_x_pins: spi1_ss0_x { 660 mux { 661 groups = "spi1_ss0_x"; 662 function = "spi1"; 663 }; 664 }; 665 666 tdma_din0_pins: tdma_din0 { 667 mux { 668 groups = "tdma_din0"; 669 function = "tdma"; 670 }; 671 }; 672 673 tdma_dout0_x14_pins: tdma_dout0_x14 { 674 mux { 675 groups = "tdma_dout0_x14"; 676 function = "tdma"; 677 }; 678 }; 679 680 tdma_dout0_x15_pins: tdma_dout0_x15 { 681 mux { 682 groups = "tdma_dout0_x15"; 683 function = "tdma"; 684 }; 685 }; 686 687 tdma_dout1_pins: tdma_dout1 { 688 mux { 689 groups = "tdma_dout1"; 690 function = "tdma"; 691 }; 692 }; 693 694 tdma_din1_pins: tdma_din1 { 695 mux { 696 groups = "tdma_din1"; 697 function = "tdma"; 698 }; 699 }; 700 701 tdma_fs_pins: tdma_fs { 702 mux { 703 groups = "tdma_fs"; 704 function = "tdma"; 705 }; 706 }; 707 708 tdma_fs_slv_pins: tdma_fs_slv { 709 mux { 710 groups = "tdma_fs_slv"; 711 function = "tdma"; 712 }; 713 }; 714 715 tdma_sclk_pins: tdma_sclk { 716 mux { 717 groups = "tdma_sclk"; 718 function = "tdma"; 719 }; 720 }; 721 722 tdma_sclk_slv_pins: tdma_sclk_slv { 723 mux { 724 groups = "tdma_sclk_slv"; 725 function = "tdma"; 726 }; 727 }; 728 729 tdmb_din0_pins: tdmb_din0 { 730 mux { 731 groups = "tdmb_din0"; 732 function = "tdmb"; 733 }; 734 }; 735 736 tdmb_din1_pins: tdmb_din1 { 737 mux { 738 groups = "tdmb_din1"; 739 function = "tdmb"; 740 }; 741 }; 742 743 tdmb_din2_pins: tdmb_din2 { 744 mux { 745 groups = "tdmb_din2"; 746 function = "tdmb"; 747 }; 748 }; 749 750 tdmb_din3_pins: tdmb_din3 { 751 mux { 752 groups = "tdmb_din3"; 753 function = "tdmb"; 754 }; 755 }; 756 757 tdmb_dout0_pins: tdmb_dout0 { 758 mux { 759 groups = "tdmb_dout0"; 760 function = "tdmb"; 761 }; 762 }; 763 764 tdmb_dout1_pins: tdmb_dout1 { 765 mux { 766 groups = "tdmb_dout1"; 767 function = "tdmb"; 768 }; 769 }; 770 771 tdmb_dout2_pins: tdmb_dout2 { 772 mux { 773 groups = "tdmb_dout2"; 774 function = "tdmb"; 775 }; 776 }; 777 778 tdmb_dout3_pins: tdmb_dout3 { 779 mux { 780 groups = "tdmb_dout3"; 781 function = "tdmb"; 782 }; 783 }; 784 785 tdmb_fs_pins: tdmb_fs { 786 mux { 787 groups = "tdmb_fs"; 788 function = "tdmb"; 789 }; 790 }; 791 792 tdmb_fs_slv_pins: tdmb_fs_slv { 793 mux { 794 groups = "tdmb_fs_slv"; 795 function = "tdmb"; 796 }; 797 }; 798 799 tdmb_sclk_pins: tdmb_sclk { 800 mux { 801 groups = "tdmb_sclk"; 802 function = "tdmb"; 803 }; 804 }; 805 806 tdmb_sclk_slv_pins: tdmb_sclk_slv { 807 mux { 808 groups = "tdmb_sclk_slv"; 809 function = "tdmb"; 810 }; 811 }; 812 813 tdmc_fs_pins: tdmc_fs { 814 mux { 815 groups = "tdmc_fs"; 816 function = "tdmc"; 817 }; 818 }; 819 820 tdmc_fs_slv_pins: tdmc_fs_slv { 821 mux { 822 groups = "tdmc_fs_slv"; 823 function = "tdmc"; 824 }; 825 }; 826 827 tdmc_sclk_pins: tdmc_sclk { 828 mux { 829 groups = "tdmc_sclk"; 830 function = "tdmc"; 831 }; 832 }; 833 834 tdmc_sclk_slv_pins: tdmc_sclk_slv { 835 mux { 836 groups = "tdmc_sclk_slv"; 837 function = "tdmc"; 838 }; 839 }; 840 841 tdmc_din0_pins: tdmc_din0 { 842 mux { 843 groups = "tdmc_din0"; 844 function = "tdmc"; 845 }; 846 }; 847 848 tdmc_din1_pins: tdmc_din1 { 849 mux { 850 groups = "tdmc_din1"; 851 function = "tdmc"; 852 }; 853 }; 854 855 tdmc_din2_pins: tdmc_din2 { 856 mux { 857 groups = "tdmc_din2"; 858 function = "tdmc"; 859 }; 860 }; 861 862 tdmc_din3_pins: tdmc_din3 { 863 mux { 864 groups = "tdmc_din3"; 865 function = "tdmc"; 866 }; 867 }; 868 869 tdmc_dout0_pins: tdmc_dout0 { 870 mux { 871 groups = "tdmc_dout0"; 872 function = "tdmc"; 873 }; 874 }; 875 876 tdmc_dout1_pins: tdmc_dout1 { 877 mux { 878 groups = "tdmc_dout1"; 879 function = "tdmc"; 880 }; 881 }; 882 883 tdmc_dout2_pins: tdmc_dout2 { 884 mux { 885 groups = "tdmc_dout2"; 886 function = "tdmc"; 887 }; 888 }; 889 890 tdmc_dout3_pins: tdmc_dout3 { 891 mux { 892 groups = "tdmc_dout3"; 893 function = "tdmc"; 894 }; 895 }; 896 897 uart_a_pins: uart_a { 898 mux { 899 groups = "uart_tx_a", 900 "uart_rx_a"; 901 function = "uart_a"; 902 }; 903 }; 904 905 uart_a_cts_rts_pins: uart_a_cts_rts { 906 mux { 907 groups = "uart_cts_a", 908 "uart_rts_a"; 909 function = "uart_a"; 910 }; 911 }; 912 913 uart_b_x_pins: uart_b_x { 914 mux { 915 groups = "uart_tx_b_x", 916 "uart_rx_b_x"; 917 function = "uart_b"; 918 }; 919 }; 920 921 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 922 mux { 923 groups = "uart_cts_b_x", 924 "uart_rts_b_x"; 925 function = "uart_b"; 926 }; 927 }; 928 929 uart_b_z_pins: uart_b_z { 930 mux { 931 groups = "uart_tx_b_z", 932 "uart_rx_b_z"; 933 function = "uart_b"; 934 }; 935 }; 936 937 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 938 mux { 939 groups = "uart_cts_b_z", 940 "uart_rts_b_z"; 941 function = "uart_b"; 942 }; 943 }; 944 945 uart_ao_b_z_pins: uart_ao_b_z { 946 mux { 947 groups = "uart_ao_tx_b_z", 948 "uart_ao_rx_b_z"; 949 function = "uart_ao_b_z"; 950 }; 951 }; 952 953 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 954 mux { 955 groups = "uart_ao_cts_b_z", 956 "uart_ao_rts_b_z"; 957 function = "uart_ao_b_z"; 958 }; 959 }; 960 }; 961 }; 962 963 hiubus: bus@ff63c000 { 964 compatible = "simple-bus"; 965 reg = <0x0 0xff63c000 0x0 0x1c00>; 966 #address-cells = <2>; 967 #size-cells = <2>; 968 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 969 970 sysctrl: system-controller@0 { 971 compatible = "amlogic,meson-axg-hhi-sysctrl", 972 "simple-mfd", "syscon"; 973 reg = <0 0 0 0x400>; 974 975 clkc: clock-controller { 976 compatible = "amlogic,axg-clkc"; 977 #clock-cells = <1>; 978 }; 979 }; 980 }; 981 982 mailbox: mailbox@ff63dc00 { 983 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 984 reg = <0 0xff63dc00 0 0x400>; 985 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 986 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 987 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 988 #mbox-cells = <1>; 989 }; 990 991 audio: bus@ff642000 { 992 compatible = "simple-bus"; 993 reg = <0x0 0xff642000 0x0 0x2000>; 994 #address-cells = <2>; 995 #size-cells = <2>; 996 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 997 998 clkc_audio: clock-controller@0 { 999 compatible = "amlogic,axg-audio-clkc"; 1000 reg = <0x0 0x0 0x0 0xb4>; 1001 #clock-cells = <1>; 1002 1003 clocks = <&clkc CLKID_AUDIO>, 1004 <&clkc CLKID_MPLL0>, 1005 <&clkc CLKID_MPLL1>, 1006 <&clkc CLKID_MPLL2>, 1007 <&clkc CLKID_MPLL3>, 1008 <&clkc CLKID_HIFI_PLL>, 1009 <&clkc CLKID_FCLK_DIV3>, 1010 <&clkc CLKID_FCLK_DIV4>, 1011 <&clkc CLKID_GP0_PLL>; 1012 clock-names = "pclk", 1013 "mst_in0", 1014 "mst_in1", 1015 "mst_in2", 1016 "mst_in3", 1017 "mst_in4", 1018 "mst_in5", 1019 "mst_in6", 1020 "mst_in7"; 1021 1022 resets = <&reset RESET_AUDIO>; 1023 }; 1024 1025 toddr_a: audio-controller@100 { 1026 compatible = "amlogic,axg-toddr"; 1027 reg = <0x0 0x100 0x0 0x1c>; 1028 #sound-dai-cells = <0>; 1029 sound-name-prefix = "TODDR_A"; 1030 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1031 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1032 resets = <&arb AXG_ARB_TODDR_A>; 1033 status = "disabled"; 1034 }; 1035 1036 toddr_b: audio-controller@140 { 1037 compatible = "amlogic,axg-toddr"; 1038 reg = <0x0 0x140 0x0 0x1c>; 1039 #sound-dai-cells = <0>; 1040 sound-name-prefix = "TODDR_B"; 1041 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1042 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1043 resets = <&arb AXG_ARB_TODDR_B>; 1044 status = "disabled"; 1045 }; 1046 1047 toddr_c: audio-controller@180 { 1048 compatible = "amlogic,axg-toddr"; 1049 reg = <0x0 0x180 0x0 0x1c>; 1050 #sound-dai-cells = <0>; 1051 sound-name-prefix = "TODDR_C"; 1052 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1053 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1054 resets = <&arb AXG_ARB_TODDR_C>; 1055 status = "disabled"; 1056 }; 1057 1058 frddr_a: audio-controller@1c0 { 1059 compatible = "amlogic,axg-frddr"; 1060 reg = <0x0 0x1c0 0x0 0x1c>; 1061 #sound-dai-cells = <0>; 1062 sound-name-prefix = "FRDDR_A"; 1063 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1064 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1065 resets = <&arb AXG_ARB_FRDDR_A>; 1066 status = "disabled"; 1067 }; 1068 1069 frddr_b: audio-controller@200 { 1070 compatible = "amlogic,axg-frddr"; 1071 reg = <0x0 0x200 0x0 0x1c>; 1072 #sound-dai-cells = <0>; 1073 sound-name-prefix = "FRDDR_B"; 1074 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1075 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1076 resets = <&arb AXG_ARB_FRDDR_B>; 1077 status = "disabled"; 1078 }; 1079 1080 frddr_c: audio-controller@240 { 1081 compatible = "amlogic,axg-frddr"; 1082 reg = <0x0 0x240 0x0 0x1c>; 1083 #sound-dai-cells = <0>; 1084 sound-name-prefix = "FRDDR_C"; 1085 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1086 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1087 resets = <&arb AXG_ARB_FRDDR_C>; 1088 status = "disabled"; 1089 }; 1090 1091 arb: reset-controller@280 { 1092 compatible = "amlogic,meson-axg-audio-arb"; 1093 reg = <0x0 0x280 0x0 0x4>; 1094 #reset-cells = <1>; 1095 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1096 }; 1097 1098 tdmin_a: audio-controller@300 { 1099 compatible = "amlogic,axg-tdmin"; 1100 reg = <0x0 0x300 0x0 0x40>; 1101 sound-name-prefix = "TDMIN_A"; 1102 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1103 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1104 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1105 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1106 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1107 clock-names = "pclk", "sclk", "sclk_sel", 1108 "lrclk", "lrclk_sel"; 1109 status = "disabled"; 1110 }; 1111 1112 tdmin_b: audio-controller@340 { 1113 compatible = "amlogic,axg-tdmin"; 1114 reg = <0x0 0x340 0x0 0x40>; 1115 sound-name-prefix = "TDMIN_B"; 1116 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1117 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1118 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1119 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1120 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1121 clock-names = "pclk", "sclk", "sclk_sel", 1122 "lrclk", "lrclk_sel"; 1123 status = "disabled"; 1124 }; 1125 1126 tdmin_c: audio-controller@380 { 1127 compatible = "amlogic,axg-tdmin"; 1128 reg = <0x0 0x380 0x0 0x40>; 1129 sound-name-prefix = "TDMIN_C"; 1130 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1131 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1132 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1133 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1134 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1135 clock-names = "pclk", "sclk", "sclk_sel", 1136 "lrclk", "lrclk_sel"; 1137 status = "disabled"; 1138 }; 1139 1140 tdmin_lb: audio-controller@3c0 { 1141 compatible = "amlogic,axg-tdmin"; 1142 reg = <0x0 0x3c0 0x0 0x40>; 1143 sound-name-prefix = "TDMIN_LB"; 1144 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1145 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1146 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1147 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1148 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1149 clock-names = "pclk", "sclk", "sclk_sel", 1150 "lrclk", "lrclk_sel"; 1151 status = "disabled"; 1152 }; 1153 1154 spdifout: audio-controller@480 { 1155 compatible = "amlogic,axg-spdifout"; 1156 reg = <0x0 0x480 0x0 0x50>; 1157 #sound-dai-cells = <0>; 1158 sound-name-prefix = "SPDIFOUT"; 1159 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1160 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1161 clock-names = "pclk", "mclk"; 1162 status = "disabled"; 1163 }; 1164 1165 tdmout_a: audio-controller@500 { 1166 compatible = "amlogic,axg-tdmout"; 1167 reg = <0x0 0x500 0x0 0x40>; 1168 sound-name-prefix = "TDMOUT_A"; 1169 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1170 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1171 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1172 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1173 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1174 clock-names = "pclk", "sclk", "sclk_sel", 1175 "lrclk", "lrclk_sel"; 1176 status = "disabled"; 1177 }; 1178 1179 tdmout_b: audio-controller@540 { 1180 compatible = "amlogic,axg-tdmout"; 1181 reg = <0x0 0x540 0x0 0x40>; 1182 sound-name-prefix = "TDMOUT_B"; 1183 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1184 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1185 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1186 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1187 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1188 clock-names = "pclk", "sclk", "sclk_sel", 1189 "lrclk", "lrclk_sel"; 1190 status = "disabled"; 1191 }; 1192 1193 tdmout_c: audio-controller@580 { 1194 compatible = "amlogic,axg-tdmout"; 1195 reg = <0x0 0x580 0x0 0x40>; 1196 sound-name-prefix = "TDMOUT_C"; 1197 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1198 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1199 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1200 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1201 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1202 clock-names = "pclk", "sclk", "sclk_sel", 1203 "lrclk", "lrclk_sel"; 1204 status = "disabled"; 1205 }; 1206 }; 1207 1208 aobus: bus@ff800000 { 1209 compatible = "simple-bus"; 1210 reg = <0x0 0xff800000 0x0 0x100000>; 1211 #address-cells = <2>; 1212 #size-cells = <2>; 1213 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1214 1215 sysctrl_AO: sys-ctrl@0 { 1216 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1217 reg = <0x0 0x0 0x0 0x100>; 1218 1219 clkc_AO: clock-controller { 1220 compatible = "amlogic,meson-axg-aoclkc"; 1221 #clock-cells = <1>; 1222 #reset-cells = <1>; 1223 }; 1224 }; 1225 1226 pinctrl_aobus: pinctrl@14 { 1227 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1228 #address-cells = <2>; 1229 #size-cells = <2>; 1230 ranges; 1231 1232 gpio_ao: bank@14 { 1233 reg = <0x0 0x00014 0x0 0x8>, 1234 <0x0 0x0002c 0x0 0x4>, 1235 <0x0 0x00024 0x0 0x8>; 1236 reg-names = "mux", "pull", "gpio"; 1237 gpio-controller; 1238 #gpio-cells = <2>; 1239 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1240 }; 1241 1242 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1243 mux { 1244 groups = "i2c_ao_sck_4"; 1245 function = "i2c_ao"; 1246 }; 1247 }; 1248 1249 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1250 mux { 1251 groups = "i2c_ao_sck_8"; 1252 function = "i2c_ao"; 1253 }; 1254 }; 1255 1256 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1257 mux { 1258 groups = "i2c_ao_sck_10"; 1259 function = "i2c_ao"; 1260 }; 1261 }; 1262 1263 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1264 mux { 1265 groups = "i2c_ao_sda_5"; 1266 function = "i2c_ao"; 1267 }; 1268 }; 1269 1270 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1271 mux { 1272 groups = "i2c_ao_sda_9"; 1273 function = "i2c_ao"; 1274 }; 1275 }; 1276 1277 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1278 mux { 1279 groups = "i2c_ao_sda_11"; 1280 function = "i2c_ao"; 1281 }; 1282 }; 1283 1284 remote_input_ao_pins: remote_input_ao { 1285 mux { 1286 groups = "remote_input_ao"; 1287 function = "remote_input_ao"; 1288 }; 1289 }; 1290 1291 uart_ao_a_pins: uart_ao_a { 1292 mux { 1293 groups = "uart_ao_tx_a", 1294 "uart_ao_rx_a"; 1295 function = "uart_ao_a"; 1296 }; 1297 }; 1298 1299 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1300 mux { 1301 groups = "uart_ao_cts_a", 1302 "uart_ao_rts_a"; 1303 function = "uart_ao_a"; 1304 }; 1305 }; 1306 1307 uart_ao_b_pins: uart_ao_b { 1308 mux { 1309 groups = "uart_ao_tx_b", 1310 "uart_ao_rx_b"; 1311 function = "uart_ao_b"; 1312 }; 1313 }; 1314 1315 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1316 mux { 1317 groups = "uart_ao_cts_b", 1318 "uart_ao_rts_b"; 1319 function = "uart_ao_b"; 1320 }; 1321 }; 1322 }; 1323 1324 sec_AO: ao-secure@140 { 1325 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1326 reg = <0x0 0x140 0x0 0x140>; 1327 amlogic,has-chip-id; 1328 }; 1329 1330 pwm_AO_cd: pwm@2000 { 1331 compatible = "amlogic,meson-axg-ao-pwm"; 1332 reg = <0x0 0x02000 0x0 0x20>; 1333 #pwm-cells = <3>; 1334 status = "disabled"; 1335 }; 1336 1337 uart_AO: serial@3000 { 1338 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1339 reg = <0x0 0x3000 0x0 0x18>; 1340 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1341 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1342 clock-names = "xtal", "pclk", "baud"; 1343 status = "disabled"; 1344 }; 1345 1346 uart_AO_B: serial@4000 { 1347 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1348 reg = <0x0 0x4000 0x0 0x18>; 1349 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1350 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1351 clock-names = "xtal", "pclk", "baud"; 1352 status = "disabled"; 1353 }; 1354 1355 i2c_AO: i2c@5000 { 1356 compatible = "amlogic,meson-axg-i2c"; 1357 reg = <0x0 0x05000 0x0 0x20>; 1358 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1359 clocks = <&clkc CLKID_AO_I2C>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 pwm_AO_ab: pwm@7000 { 1366 compatible = "amlogic,meson-axg-ao-pwm"; 1367 reg = <0x0 0x07000 0x0 0x20>; 1368 #pwm-cells = <3>; 1369 status = "disabled"; 1370 }; 1371 1372 ir: ir@8000 { 1373 compatible = "amlogic,meson-gxbb-ir"; 1374 reg = <0x0 0x8000 0x0 0x20>; 1375 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1376 status = "disabled"; 1377 }; 1378 1379 saradc: adc@9000 { 1380 compatible = "amlogic,meson-axg-saradc", 1381 "amlogic,meson-saradc"; 1382 reg = <0x0 0x9000 0x0 0x38>; 1383 #io-channel-cells = <1>; 1384 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1385 clocks = <&xtal>, 1386 <&clkc_AO CLKID_AO_SAR_ADC>, 1387 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1388 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1389 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1390 status = "disabled"; 1391 }; 1392 }; 1393 1394 gic: interrupt-controller@ffc01000 { 1395 compatible = "arm,gic-400"; 1396 reg = <0x0 0xffc01000 0 0x1000>, 1397 <0x0 0xffc02000 0 0x2000>, 1398 <0x0 0xffc04000 0 0x2000>, 1399 <0x0 0xffc06000 0 0x2000>; 1400 interrupt-controller; 1401 interrupts = <GIC_PPI 9 1402 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1403 #interrupt-cells = <3>; 1404 #address-cells = <0>; 1405 }; 1406 1407 cbus: bus@ffd00000 { 1408 compatible = "simple-bus"; 1409 reg = <0x0 0xffd00000 0x0 0x25000>; 1410 #address-cells = <2>; 1411 #size-cells = <2>; 1412 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1413 1414 reset: reset-controller@1004 { 1415 compatible = "amlogic,meson-axg-reset"; 1416 reg = <0x0 0x01004 0x0 0x9c>; 1417 #reset-cells = <1>; 1418 }; 1419 1420 gpio_intc: interrupt-controller@f080 { 1421 compatible = "amlogic,meson-gpio-intc"; 1422 reg = <0x0 0xf080 0x0 0x10>; 1423 interrupt-controller; 1424 #interrupt-cells = <2>; 1425 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1426 status = "disabled"; 1427 }; 1428 1429 pwm_ab: pwm@1b000 { 1430 compatible = "amlogic,meson-axg-ee-pwm"; 1431 reg = <0x0 0x1b000 0x0 0x20>; 1432 #pwm-cells = <3>; 1433 status = "disabled"; 1434 }; 1435 1436 pwm_cd: pwm@1a000 { 1437 compatible = "amlogic,meson-axg-ee-pwm"; 1438 reg = <0x0 0x1a000 0x0 0x20>; 1439 #pwm-cells = <3>; 1440 status = "disabled"; 1441 }; 1442 1443 spicc0: spi@13000 { 1444 compatible = "amlogic,meson-axg-spicc"; 1445 reg = <0x0 0x13000 0x0 0x3c>; 1446 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&clkc CLKID_SPICC0>; 1448 clock-names = "core"; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 spicc1: spi@15000 { 1455 compatible = "amlogic,meson-axg-spicc"; 1456 reg = <0x0 0x15000 0x0 0x3c>; 1457 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&clkc CLKID_SPICC1>; 1459 clock-names = "core"; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 1465 i2c3: i2c@1c000 { 1466 compatible = "amlogic,meson-axg-i2c"; 1467 reg = <0x0 0x1c000 0x0 0x20>; 1468 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1469 clocks = <&clkc CLKID_I2C>; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 i2c2: i2c@1d000 { 1476 compatible = "amlogic,meson-axg-i2c"; 1477 reg = <0x0 0x1d000 0x0 0x20>; 1478 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1479 clocks = <&clkc CLKID_I2C>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 status = "disabled"; 1483 }; 1484 1485 i2c1: i2c@1e000 { 1486 compatible = "amlogic,meson-axg-i2c"; 1487 reg = <0x0 0x1e000 0x0 0x20>; 1488 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1489 clocks = <&clkc CLKID_I2C>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 i2c0: i2c@1f000 { 1496 compatible = "amlogic,meson-axg-i2c"; 1497 reg = <0x0 0x1f000 0x0 0x20>; 1498 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1499 clocks = <&clkc CLKID_I2C>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 uart_B: serial@23000 { 1506 compatible = "amlogic,meson-gx-uart"; 1507 reg = <0x0 0x23000 0x0 0x18>; 1508 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1509 status = "disabled"; 1510 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1511 clock-names = "xtal", "pclk", "baud"; 1512 }; 1513 1514 uart_A: serial@24000 { 1515 compatible = "amlogic,meson-gx-uart"; 1516 reg = <0x0 0x24000 0x0 0x18>; 1517 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1518 status = "disabled"; 1519 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1520 clock-names = "xtal", "pclk", "baud"; 1521 }; 1522 }; 1523 1524 apb: bus@ffe00000 { 1525 compatible = "simple-bus"; 1526 reg = <0x0 0xffe00000 0x0 0x200000>; 1527 #address-cells = <2>; 1528 #size-cells = <2>; 1529 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1530 1531 sd_emmc_b: sd@5000 { 1532 compatible = "amlogic,meson-axg-mmc"; 1533 reg = <0x0 0x5000 0x0 0x800>; 1534 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1535 status = "disabled"; 1536 clocks = <&clkc CLKID_SD_EMMC_B>, 1537 <&clkc CLKID_SD_EMMC_B_CLK0>, 1538 <&clkc CLKID_FCLK_DIV2>; 1539 clock-names = "core", "clkin0", "clkin1"; 1540 resets = <&reset RESET_SD_EMMC_B>; 1541 }; 1542 1543 sd_emmc_c: mmc@7000 { 1544 compatible = "amlogic,meson-axg-mmc"; 1545 reg = <0x0 0x7000 0x0 0x800>; 1546 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1547 status = "disabled"; 1548 clocks = <&clkc CLKID_SD_EMMC_C>, 1549 <&clkc CLKID_SD_EMMC_C_CLK0>, 1550 <&clkc CLKID_FCLK_DIV2>; 1551 clock-names = "core", "clkin0", "clkin1"; 1552 resets = <&reset RESET_SD_EMMC_C>; 1553 }; 1554 }; 1555 1556 sram: sram@fffc0000 { 1557 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1558 reg = <0x0 0xfffc0000 0x0 0x20000>; 1559 #address-cells = <1>; 1560 #size-cells = <1>; 1561 ranges = <0 0x0 0xfffc0000 0x20000>; 1562 1563 cpu_scp_lpri: scp-shmem@0 { 1564 compatible = "amlogic,meson-axg-scp-shmem"; 1565 reg = <0x13000 0x400>; 1566 }; 1567 1568 cpu_scp_hpri: scp-shmem@200 { 1569 compatible = "amlogic,meson-axg-scp-shmem"; 1570 reg = <0x13400 0x400>; 1571 }; 1572 }; 1573 }; 1574 1575 timer { 1576 compatible = "arm,armv8-timer"; 1577 interrupts = <GIC_PPI 13 1578 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1579 <GIC_PPI 14 1580 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1581 <GIC_PPI 11 1582 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1583 <GIC_PPI 10 1584 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1585 }; 1586 1587 xtal: xtal-clk { 1588 compatible = "fixed-clock"; 1589 clock-frequency = <24000000>; 1590 clock-output-names = "xtal"; 1591 #clock-cells = <0>; 1592 }; 1593}; 1594