1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 ao_alt_xtal: ao_alt_xtal-clk { 57 compatible = "fixed-clock"; 58 clock-frequency = <32000000>; 59 clock-output-names = "ao_alt_xtal"; 60 #clock-cells = <0>; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 clocks = <&scpi_dvfs 0>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 next-level-cache = <&l2>; 91 clocks = <&scpi_dvfs 0>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0x0 0x2>; 98 enable-method = "psci"; 99 next-level-cache = <&l2>; 100 clocks = <&scpi_dvfs 0>; 101 }; 102 103 cpu3: cpu@3 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53", "arm,armv8"; 106 reg = <0x0 0x3>; 107 enable-method = "psci"; 108 next-level-cache = <&l2>; 109 clocks = <&scpi_dvfs 0>; 110 }; 111 112 l2: l2-cache0 { 113 compatible = "cache"; 114 }; 115 }; 116 117 sm: secure-monitor { 118 compatible = "amlogic,meson-gxbb-sm"; 119 }; 120 121 psci { 122 compatible = "arm,psci-1.0"; 123 method = "smc"; 124 }; 125 126 reserved-memory { 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 /* 16 MiB reserved for Hardware ROM Firmware */ 132 hwrom_reserved: hwrom@0 { 133 reg = <0x0 0x0 0x0 0x1000000>; 134 no-map; 135 }; 136 137 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 138 secmon_reserved: secmon@5000000 { 139 reg = <0x0 0x05000000 0x0 0x300000>; 140 no-map; 141 }; 142 }; 143 144 scpi { 145 compatible = "arm,scpi-pre-1.0"; 146 mboxes = <&mailbox 1 &mailbox 2>; 147 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 148 149 scpi_clocks: clocks { 150 compatible = "arm,scpi-clocks"; 151 152 scpi_dvfs: clock-controller { 153 compatible = "arm,scpi-dvfs-clocks"; 154 #clock-cells = <1>; 155 clock-indices = <0>; 156 clock-output-names = "vcpu"; 157 }; 158 }; 159 160 scpi_sensors: sensors { 161 compatible = "amlogic,meson-gxbb-scpi-sensors"; 162 #thermal-sensor-cells = <1>; 163 }; 164 }; 165 166 soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 ethmac: ethernet@ff3f0000 { 173 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 174 reg = <0x0 0xff3f0000 0x0 0x10000 175 0x0 0xff634540 0x0 0x8>; 176 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "macirq"; 178 clocks = <&clkc CLKID_ETH>, 179 <&clkc CLKID_FCLK_DIV2>, 180 <&clkc CLKID_MPLL2>; 181 clock-names = "stmmaceth", "clkin0", "clkin1"; 182 status = "disabled"; 183 }; 184 185 pdm: audio-controller@ff632000 { 186 compatible = "amlogic,axg-pdm"; 187 reg = <0x0 0xff632000 0x0 0x34>; 188 #sound-dai-cells = <0>; 189 sound-name-prefix = "PDM"; 190 clocks = <&clkc_audio AUD_CLKID_PDM>, 191 <&clkc_audio AUD_CLKID_PDM_DCLK>, 192 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 193 clock-names = "pclk", "dclk", "sysclk"; 194 status = "disabled"; 195 }; 196 197 periphs: bus@ff634000 { 198 compatible = "simple-bus"; 199 reg = <0x0 0xff634000 0x0 0x2000>; 200 #address-cells = <2>; 201 #size-cells = <2>; 202 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 203 204 hwrng: rng@18 { 205 compatible = "amlogic,meson-rng"; 206 reg = <0x0 0x18 0x0 0x4>; 207 clocks = <&clkc CLKID_RNG0>; 208 clock-names = "core"; 209 }; 210 211 pinctrl_periphs: pinctrl@480 { 212 compatible = "amlogic,meson-axg-periphs-pinctrl"; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 ranges; 216 217 gpio: bank@480 { 218 reg = <0x0 0x00480 0x0 0x40>, 219 <0x0 0x004e8 0x0 0x14>, 220 <0x0 0x00520 0x0 0x14>, 221 <0x0 0x00430 0x0 0x3c>; 222 reg-names = "mux", "pull", "pull-enable", "gpio"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 gpio-ranges = <&pinctrl_periphs 0 0 86>; 226 }; 227 228 i2c0_pins: i2c0 { 229 mux { 230 groups = "i2c0_sck", 231 "i2c0_sda"; 232 function = "i2c0"; 233 }; 234 }; 235 236 i2c1_x_pins: i2c1_x { 237 mux { 238 groups = "i2c1_sck_x", 239 "i2c1_sda_x"; 240 function = "i2c1"; 241 }; 242 }; 243 244 i2c1_z_pins: i2c1_z { 245 mux { 246 groups = "i2c1_sck_z", 247 "i2c1_sda_z"; 248 function = "i2c1"; 249 }; 250 }; 251 252 i2c2_a_pins: i2c2_a { 253 mux { 254 groups = "i2c2_sck_a", 255 "i2c2_sda_a"; 256 function = "i2c2"; 257 }; 258 }; 259 260 i2c2_x_pins: i2c2_x { 261 mux { 262 groups = "i2c2_sck_x", 263 "i2c2_sda_x"; 264 function = "i2c2"; 265 }; 266 }; 267 268 i2c3_a6_pins: i2c3_a6 { 269 mux { 270 groups = "i2c3_sda_a6", 271 "i2c3_sck_a7"; 272 function = "i2c3"; 273 }; 274 }; 275 276 i2c3_a12_pins: i2c3_a12 { 277 mux { 278 groups = "i2c3_sda_a12", 279 "i2c3_sck_a13"; 280 function = "i2c3"; 281 }; 282 }; 283 284 i2c3_a19_pins: i2c3_a19 { 285 mux { 286 groups = "i2c3_sda_a19", 287 "i2c3_sck_a20"; 288 function = "i2c3"; 289 }; 290 }; 291 292 emmc_pins: emmc { 293 mux { 294 groups = "emmc_nand_d0", 295 "emmc_nand_d1", 296 "emmc_nand_d2", 297 "emmc_nand_d3", 298 "emmc_nand_d4", 299 "emmc_nand_d5", 300 "emmc_nand_d6", 301 "emmc_nand_d7", 302 "emmc_clk", 303 "emmc_cmd", 304 "emmc_ds"; 305 function = "emmc"; 306 bias-disable; 307 }; 308 }; 309 310 emmc_clk_gate_pins: emmc_clk_gate { 311 mux { 312 groups = "BOOT_8"; 313 function = "gpio_periphs"; 314 bias-pull-down; 315 }; 316 }; 317 318 eth_rgmii_x_pins: eth-x-rgmii { 319 mux { 320 groups = "eth_mdio_x", 321 "eth_mdc_x", 322 "eth_rgmii_rx_clk_x", 323 "eth_rx_dv_x", 324 "eth_rxd0_x", 325 "eth_rxd1_x", 326 "eth_rxd2_rgmii", 327 "eth_rxd3_rgmii", 328 "eth_rgmii_tx_clk", 329 "eth_txen_x", 330 "eth_txd0_x", 331 "eth_txd1_x", 332 "eth_txd2_rgmii", 333 "eth_txd3_rgmii"; 334 function = "eth"; 335 }; 336 }; 337 338 eth_rgmii_y_pins: eth-y-rgmii { 339 mux { 340 groups = "eth_mdio_y", 341 "eth_mdc_y", 342 "eth_rgmii_rx_clk_y", 343 "eth_rx_dv_y", 344 "eth_rxd0_y", 345 "eth_rxd1_y", 346 "eth_rxd2_rgmii", 347 "eth_rxd3_rgmii", 348 "eth_rgmii_tx_clk", 349 "eth_txen_y", 350 "eth_txd0_y", 351 "eth_txd1_y", 352 "eth_txd2_rgmii", 353 "eth_txd3_rgmii"; 354 function = "eth"; 355 }; 356 }; 357 358 eth_rmii_x_pins: eth-x-rmii { 359 mux { 360 groups = "eth_mdio_x", 361 "eth_mdc_x", 362 "eth_rgmii_rx_clk_x", 363 "eth_rx_dv_x", 364 "eth_rxd0_x", 365 "eth_rxd1_x", 366 "eth_txen_x", 367 "eth_txd0_x", 368 "eth_txd1_x"; 369 function = "eth"; 370 }; 371 }; 372 373 eth_rmii_y_pins: eth-y-rmii { 374 mux { 375 groups = "eth_mdio_y", 376 "eth_mdc_y", 377 "eth_rgmii_rx_clk_y", 378 "eth_rx_dv_y", 379 "eth_rxd0_y", 380 "eth_rxd1_y", 381 "eth_txen_y", 382 "eth_txd0_y", 383 "eth_txd1_y"; 384 function = "eth"; 385 }; 386 }; 387 388 mclk_b_pins: mclk_b { 389 mux { 390 groups = "mclk_b"; 391 function = "mclk_b"; 392 }; 393 }; 394 395 mclk_c_pins: mclk_c { 396 mux { 397 groups = "mclk_c"; 398 function = "mclk_c"; 399 }; 400 }; 401 402 pdm_dclk_a14_pins: pdm_dclk_a14 { 403 mux { 404 groups = "pdm_dclk_a14"; 405 function = "pdm"; 406 }; 407 }; 408 409 pdm_dclk_a19_pins: pdm_dclk_a19 { 410 mux { 411 groups = "pdm_dclk_a19"; 412 function = "pdm"; 413 }; 414 }; 415 416 pdm_din0_pins: pdm_din0 { 417 mux { 418 groups = "pdm_din0"; 419 function = "pdm"; 420 }; 421 }; 422 423 pdm_din1_pins: pdm_din1 { 424 mux { 425 groups = "pdm_din1"; 426 function = "pdm"; 427 }; 428 }; 429 430 pdm_din2_pins: pdm_din2 { 431 mux { 432 groups = "pdm_din2"; 433 function = "pdm"; 434 }; 435 }; 436 437 pdm_din3_pins: pdm_din3 { 438 mux { 439 groups = "pdm_din3"; 440 function = "pdm"; 441 }; 442 }; 443 444 pwm_a_a_pins: pwm_a_a { 445 mux { 446 groups = "pwm_a_a"; 447 function = "pwm_a"; 448 }; 449 }; 450 451 pwm_a_x18_pins: pwm_a_x18 { 452 mux { 453 groups = "pwm_a_x18"; 454 function = "pwm_a"; 455 }; 456 }; 457 458 pwm_a_x20_pins: pwm_a_x20 { 459 mux { 460 groups = "pwm_a_x20"; 461 function = "pwm_a"; 462 }; 463 }; 464 465 pwm_a_z_pins: pwm_a_z { 466 mux { 467 groups = "pwm_a_z"; 468 function = "pwm_a"; 469 }; 470 }; 471 472 pwm_b_a_pins: pwm_b_a { 473 mux { 474 groups = "pwm_b_a"; 475 function = "pwm_b"; 476 }; 477 }; 478 479 pwm_b_x_pins: pwm_b_x { 480 mux { 481 groups = "pwm_b_x"; 482 function = "pwm_b"; 483 }; 484 }; 485 486 pwm_b_z_pins: pwm_b_z { 487 mux { 488 groups = "pwm_b_z"; 489 function = "pwm_b"; 490 }; 491 }; 492 493 pwm_c_a_pins: pwm_c_a { 494 mux { 495 groups = "pwm_c_a"; 496 function = "pwm_c"; 497 }; 498 }; 499 500 pwm_c_x10_pins: pwm_c_x10 { 501 mux { 502 groups = "pwm_c_x10"; 503 function = "pwm_c"; 504 }; 505 }; 506 507 pwm_c_x17_pins: pwm_c_x17 { 508 mux { 509 groups = "pwm_c_x17"; 510 function = "pwm_c"; 511 }; 512 }; 513 514 pwm_d_x11_pins: pwm_d_x11 { 515 mux { 516 groups = "pwm_d_x11"; 517 function = "pwm_d"; 518 }; 519 }; 520 521 pwm_d_x16_pins: pwm_d_x16 { 522 mux { 523 groups = "pwm_d_x16"; 524 function = "pwm_d"; 525 }; 526 }; 527 528 sdio_pins: sdio { 529 mux { 530 groups = "sdio_d0", 531 "sdio_d1", 532 "sdio_d2", 533 "sdio_d3", 534 "sdio_cmd", 535 "sdio_clk"; 536 function = "sdio"; 537 bias-disable; 538 }; 539 }; 540 541 sdio_clk_gate_pins: sdio_clk_gate { 542 mux { 543 groups = "GPIOX_4"; 544 function = "gpio_periphs"; 545 bias-pull-down; 546 }; 547 }; 548 549 spdif_in_z_pins: spdif_in_z { 550 mux { 551 groups = "spdif_in_z"; 552 function = "spdif_in"; 553 }; 554 }; 555 556 spdif_in_a1_pins: spdif_in_a1 { 557 mux { 558 groups = "spdif_in_a1"; 559 function = "spdif_in"; 560 }; 561 }; 562 563 spdif_in_a7_pins: spdif_in_a7 { 564 mux { 565 groups = "spdif_in_a7"; 566 function = "spdif_in"; 567 }; 568 }; 569 570 spdif_in_a19_pins: spdif_in_a19 { 571 mux { 572 groups = "spdif_in_a19"; 573 function = "spdif_in"; 574 }; 575 }; 576 577 spdif_in_a20_pins: spdif_in_a20 { 578 mux { 579 groups = "spdif_in_a20"; 580 function = "spdif_in"; 581 }; 582 }; 583 584 spdif_out_a1_pins: spdif_out_a1 { 585 mux { 586 groups = "spdif_out_a1"; 587 function = "spdif_out"; 588 }; 589 }; 590 591 spdif_out_a11_pins: spdif_out_a11 { 592 mux { 593 groups = "spdif_out_a11"; 594 function = "spdif_out"; 595 }; 596 }; 597 598 spdif_out_a19_pins: spdif_out_a19 { 599 mux { 600 groups = "spdif_out_a19"; 601 function = "spdif_out"; 602 }; 603 }; 604 605 spdif_out_a20_pins: spdif_out_a20 { 606 mux { 607 groups = "spdif_out_a20"; 608 function = "spdif_out"; 609 }; 610 }; 611 612 spdif_out_z_pins: spdif_out_z { 613 mux { 614 groups = "spdif_out_z"; 615 function = "spdif_out"; 616 }; 617 }; 618 619 spi0_pins: spi0 { 620 mux { 621 groups = "spi0_miso", 622 "spi0_mosi", 623 "spi0_clk"; 624 function = "spi0"; 625 }; 626 }; 627 628 spi0_ss0_pins: spi0_ss0 { 629 mux { 630 groups = "spi0_ss0"; 631 function = "spi0"; 632 }; 633 }; 634 635 spi0_ss1_pins: spi0_ss1 { 636 mux { 637 groups = "spi0_ss1"; 638 function = "spi0"; 639 }; 640 }; 641 642 spi0_ss2_pins: spi0_ss2 { 643 mux { 644 groups = "spi0_ss2"; 645 function = "spi0"; 646 }; 647 }; 648 649 spi1_a_pins: spi1_a { 650 mux { 651 groups = "spi1_miso_a", 652 "spi1_mosi_a", 653 "spi1_clk_a"; 654 function = "spi1"; 655 }; 656 }; 657 658 spi1_ss0_a_pins: spi1_ss0_a { 659 mux { 660 groups = "spi1_ss0_a"; 661 function = "spi1"; 662 }; 663 }; 664 665 spi1_ss1_pins: spi1_ss1 { 666 mux { 667 groups = "spi1_ss1"; 668 function = "spi1"; 669 }; 670 }; 671 672 spi1_x_pins: spi1_x { 673 mux { 674 groups = "spi1_miso_x", 675 "spi1_mosi_x", 676 "spi1_clk_x"; 677 function = "spi1"; 678 }; 679 }; 680 681 spi1_ss0_x_pins: spi1_ss0_x { 682 mux { 683 groups = "spi1_ss0_x"; 684 function = "spi1"; 685 }; 686 }; 687 688 tdma_din0_pins: tdma_din0 { 689 mux { 690 groups = "tdma_din0"; 691 function = "tdma"; 692 }; 693 }; 694 695 tdma_dout0_x14_pins: tdma_dout0_x14 { 696 mux { 697 groups = "tdma_dout0_x14"; 698 function = "tdma"; 699 }; 700 }; 701 702 tdma_dout0_x15_pins: tdma_dout0_x15 { 703 mux { 704 groups = "tdma_dout0_x15"; 705 function = "tdma"; 706 }; 707 }; 708 709 tdma_dout1_pins: tdma_dout1 { 710 mux { 711 groups = "tdma_dout1"; 712 function = "tdma"; 713 }; 714 }; 715 716 tdma_din1_pins: tdma_din1 { 717 mux { 718 groups = "tdma_din1"; 719 function = "tdma"; 720 }; 721 }; 722 723 tdma_fs_pins: tdma_fs { 724 mux { 725 groups = "tdma_fs"; 726 function = "tdma"; 727 }; 728 }; 729 730 tdma_fs_slv_pins: tdma_fs_slv { 731 mux { 732 groups = "tdma_fs_slv"; 733 function = "tdma"; 734 }; 735 }; 736 737 tdma_sclk_pins: tdma_sclk { 738 mux { 739 groups = "tdma_sclk"; 740 function = "tdma"; 741 }; 742 }; 743 744 tdma_sclk_slv_pins: tdma_sclk_slv { 745 mux { 746 groups = "tdma_sclk_slv"; 747 function = "tdma"; 748 }; 749 }; 750 751 tdmb_din0_pins: tdmb_din0 { 752 mux { 753 groups = "tdmb_din0"; 754 function = "tdmb"; 755 }; 756 }; 757 758 tdmb_din1_pins: tdmb_din1 { 759 mux { 760 groups = "tdmb_din1"; 761 function = "tdmb"; 762 }; 763 }; 764 765 tdmb_din2_pins: tdmb_din2 { 766 mux { 767 groups = "tdmb_din2"; 768 function = "tdmb"; 769 }; 770 }; 771 772 tdmb_din3_pins: tdmb_din3 { 773 mux { 774 groups = "tdmb_din3"; 775 function = "tdmb"; 776 }; 777 }; 778 779 tdmb_dout0_pins: tdmb_dout0 { 780 mux { 781 groups = "tdmb_dout0"; 782 function = "tdmb"; 783 }; 784 }; 785 786 tdmb_dout1_pins: tdmb_dout1 { 787 mux { 788 groups = "tdmb_dout1"; 789 function = "tdmb"; 790 }; 791 }; 792 793 tdmb_dout2_pins: tdmb_dout2 { 794 mux { 795 groups = "tdmb_dout2"; 796 function = "tdmb"; 797 }; 798 }; 799 800 tdmb_dout3_pins: tdmb_dout3 { 801 mux { 802 groups = "tdmb_dout3"; 803 function = "tdmb"; 804 }; 805 }; 806 807 tdmb_fs_pins: tdmb_fs { 808 mux { 809 groups = "tdmb_fs"; 810 function = "tdmb"; 811 }; 812 }; 813 814 tdmb_fs_slv_pins: tdmb_fs_slv { 815 mux { 816 groups = "tdmb_fs_slv"; 817 function = "tdmb"; 818 }; 819 }; 820 821 tdmb_sclk_pins: tdmb_sclk { 822 mux { 823 groups = "tdmb_sclk"; 824 function = "tdmb"; 825 }; 826 }; 827 828 tdmb_sclk_slv_pins: tdmb_sclk_slv { 829 mux { 830 groups = "tdmb_sclk_slv"; 831 function = "tdmb"; 832 }; 833 }; 834 835 tdmc_fs_pins: tdmc_fs { 836 mux { 837 groups = "tdmc_fs"; 838 function = "tdmc"; 839 }; 840 }; 841 842 tdmc_fs_slv_pins: tdmc_fs_slv { 843 mux { 844 groups = "tdmc_fs_slv"; 845 function = "tdmc"; 846 }; 847 }; 848 849 tdmc_sclk_pins: tdmc_sclk { 850 mux { 851 groups = "tdmc_sclk"; 852 function = "tdmc"; 853 }; 854 }; 855 856 tdmc_sclk_slv_pins: tdmc_sclk_slv { 857 mux { 858 groups = "tdmc_sclk_slv"; 859 function = "tdmc"; 860 }; 861 }; 862 863 tdmc_din0_pins: tdmc_din0 { 864 mux { 865 groups = "tdmc_din0"; 866 function = "tdmc"; 867 }; 868 }; 869 870 tdmc_din1_pins: tdmc_din1 { 871 mux { 872 groups = "tdmc_din1"; 873 function = "tdmc"; 874 }; 875 }; 876 877 tdmc_din2_pins: tdmc_din2 { 878 mux { 879 groups = "tdmc_din2"; 880 function = "tdmc"; 881 }; 882 }; 883 884 tdmc_din3_pins: tdmc_din3 { 885 mux { 886 groups = "tdmc_din3"; 887 function = "tdmc"; 888 }; 889 }; 890 891 tdmc_dout0_pins: tdmc_dout0 { 892 mux { 893 groups = "tdmc_dout0"; 894 function = "tdmc"; 895 }; 896 }; 897 898 tdmc_dout1_pins: tdmc_dout1 { 899 mux { 900 groups = "tdmc_dout1"; 901 function = "tdmc"; 902 }; 903 }; 904 905 tdmc_dout2_pins: tdmc_dout2 { 906 mux { 907 groups = "tdmc_dout2"; 908 function = "tdmc"; 909 }; 910 }; 911 912 tdmc_dout3_pins: tdmc_dout3 { 913 mux { 914 groups = "tdmc_dout3"; 915 function = "tdmc"; 916 }; 917 }; 918 919 uart_a_pins: uart_a { 920 mux { 921 groups = "uart_tx_a", 922 "uart_rx_a"; 923 function = "uart_a"; 924 }; 925 }; 926 927 uart_a_cts_rts_pins: uart_a_cts_rts { 928 mux { 929 groups = "uart_cts_a", 930 "uart_rts_a"; 931 function = "uart_a"; 932 }; 933 }; 934 935 uart_b_x_pins: uart_b_x { 936 mux { 937 groups = "uart_tx_b_x", 938 "uart_rx_b_x"; 939 function = "uart_b"; 940 }; 941 }; 942 943 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 944 mux { 945 groups = "uart_cts_b_x", 946 "uart_rts_b_x"; 947 function = "uart_b"; 948 }; 949 }; 950 951 uart_b_z_pins: uart_b_z { 952 mux { 953 groups = "uart_tx_b_z", 954 "uart_rx_b_z"; 955 function = "uart_b"; 956 }; 957 }; 958 959 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 960 mux { 961 groups = "uart_cts_b_z", 962 "uart_rts_b_z"; 963 function = "uart_b"; 964 }; 965 }; 966 967 uart_ao_b_z_pins: uart_ao_b_z { 968 mux { 969 groups = "uart_ao_tx_b_z", 970 "uart_ao_rx_b_z"; 971 function = "uart_ao_b_z"; 972 }; 973 }; 974 975 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 976 mux { 977 groups = "uart_ao_cts_b_z", 978 "uart_ao_rts_b_z"; 979 function = "uart_ao_b_z"; 980 }; 981 }; 982 }; 983 }; 984 985 hiubus: bus@ff63c000 { 986 compatible = "simple-bus"; 987 reg = <0x0 0xff63c000 0x0 0x1c00>; 988 #address-cells = <2>; 989 #size-cells = <2>; 990 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 991 992 sysctrl: system-controller@0 { 993 compatible = "amlogic,meson-axg-hhi-sysctrl", 994 "simple-mfd", "syscon"; 995 reg = <0 0 0 0x400>; 996 997 clkc: clock-controller { 998 compatible = "amlogic,axg-clkc"; 999 #clock-cells = <1>; 1000 }; 1001 }; 1002 }; 1003 1004 mailbox: mailbox@ff63c404 { 1005 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1006 reg = <0 0xff63c404 0 0x4c>; 1007 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1008 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1009 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1010 #mbox-cells = <1>; 1011 }; 1012 1013 audio: bus@ff642000 { 1014 compatible = "simple-bus"; 1015 reg = <0x0 0xff642000 0x0 0x2000>; 1016 #address-cells = <2>; 1017 #size-cells = <2>; 1018 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1019 1020 clkc_audio: clock-controller@0 { 1021 compatible = "amlogic,axg-audio-clkc"; 1022 reg = <0x0 0x0 0x0 0xb4>; 1023 #clock-cells = <1>; 1024 1025 clocks = <&clkc CLKID_AUDIO>, 1026 <&clkc CLKID_MPLL0>, 1027 <&clkc CLKID_MPLL1>, 1028 <&clkc CLKID_MPLL2>, 1029 <&clkc CLKID_MPLL3>, 1030 <&clkc CLKID_HIFI_PLL>, 1031 <&clkc CLKID_FCLK_DIV3>, 1032 <&clkc CLKID_FCLK_DIV4>, 1033 <&clkc CLKID_GP0_PLL>; 1034 clock-names = "pclk", 1035 "mst_in0", 1036 "mst_in1", 1037 "mst_in2", 1038 "mst_in3", 1039 "mst_in4", 1040 "mst_in5", 1041 "mst_in6", 1042 "mst_in7"; 1043 1044 resets = <&reset RESET_AUDIO>; 1045 }; 1046 1047 toddr_a: audio-controller@100 { 1048 compatible = "amlogic,axg-toddr"; 1049 reg = <0x0 0x100 0x0 0x1c>; 1050 #sound-dai-cells = <0>; 1051 sound-name-prefix = "TODDR_A"; 1052 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1053 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1054 resets = <&arb AXG_ARB_TODDR_A>; 1055 status = "disabled"; 1056 }; 1057 1058 toddr_b: audio-controller@140 { 1059 compatible = "amlogic,axg-toddr"; 1060 reg = <0x0 0x140 0x0 0x1c>; 1061 #sound-dai-cells = <0>; 1062 sound-name-prefix = "TODDR_B"; 1063 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1064 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1065 resets = <&arb AXG_ARB_TODDR_B>; 1066 status = "disabled"; 1067 }; 1068 1069 toddr_c: audio-controller@180 { 1070 compatible = "amlogic,axg-toddr"; 1071 reg = <0x0 0x180 0x0 0x1c>; 1072 #sound-dai-cells = <0>; 1073 sound-name-prefix = "TODDR_C"; 1074 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1075 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1076 resets = <&arb AXG_ARB_TODDR_C>; 1077 status = "disabled"; 1078 }; 1079 1080 frddr_a: audio-controller@1c0 { 1081 compatible = "amlogic,axg-frddr"; 1082 reg = <0x0 0x1c0 0x0 0x1c>; 1083 #sound-dai-cells = <0>; 1084 sound-name-prefix = "FRDDR_A"; 1085 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1086 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1087 resets = <&arb AXG_ARB_FRDDR_A>; 1088 status = "disabled"; 1089 }; 1090 1091 frddr_b: audio-controller@200 { 1092 compatible = "amlogic,axg-frddr"; 1093 reg = <0x0 0x200 0x0 0x1c>; 1094 #sound-dai-cells = <0>; 1095 sound-name-prefix = "FRDDR_B"; 1096 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1097 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1098 resets = <&arb AXG_ARB_FRDDR_B>; 1099 status = "disabled"; 1100 }; 1101 1102 frddr_c: audio-controller@240 { 1103 compatible = "amlogic,axg-frddr"; 1104 reg = <0x0 0x240 0x0 0x1c>; 1105 #sound-dai-cells = <0>; 1106 sound-name-prefix = "FRDDR_C"; 1107 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1108 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1109 resets = <&arb AXG_ARB_FRDDR_C>; 1110 status = "disabled"; 1111 }; 1112 1113 arb: reset-controller@280 { 1114 compatible = "amlogic,meson-axg-audio-arb"; 1115 reg = <0x0 0x280 0x0 0x4>; 1116 #reset-cells = <1>; 1117 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1118 }; 1119 1120 tdmin_a: audio-controller@300 { 1121 compatible = "amlogic,axg-tdmin"; 1122 reg = <0x0 0x300 0x0 0x40>; 1123 sound-name-prefix = "TDMIN_A"; 1124 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1125 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1126 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1127 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1128 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1129 clock-names = "pclk", "sclk", "sclk_sel", 1130 "lrclk", "lrclk_sel"; 1131 status = "disabled"; 1132 }; 1133 1134 tdmin_b: audio-controller@340 { 1135 compatible = "amlogic,axg-tdmin"; 1136 reg = <0x0 0x340 0x0 0x40>; 1137 sound-name-prefix = "TDMIN_B"; 1138 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1139 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1140 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1141 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1142 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1143 clock-names = "pclk", "sclk", "sclk_sel", 1144 "lrclk", "lrclk_sel"; 1145 status = "disabled"; 1146 }; 1147 1148 tdmin_c: audio-controller@380 { 1149 compatible = "amlogic,axg-tdmin"; 1150 reg = <0x0 0x380 0x0 0x40>; 1151 sound-name-prefix = "TDMIN_C"; 1152 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1153 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1154 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1155 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1156 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1157 clock-names = "pclk", "sclk", "sclk_sel", 1158 "lrclk", "lrclk_sel"; 1159 status = "disabled"; 1160 }; 1161 1162 tdmin_lb: audio-controller@3c0 { 1163 compatible = "amlogic,axg-tdmin"; 1164 reg = <0x0 0x3c0 0x0 0x40>; 1165 sound-name-prefix = "TDMIN_LB"; 1166 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1167 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1168 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1169 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1170 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1171 clock-names = "pclk", "sclk", "sclk_sel", 1172 "lrclk", "lrclk_sel"; 1173 status = "disabled"; 1174 }; 1175 1176 spdifout: audio-controller@480 { 1177 compatible = "amlogic,axg-spdifout"; 1178 reg = <0x0 0x480 0x0 0x50>; 1179 #sound-dai-cells = <0>; 1180 sound-name-prefix = "SPDIFOUT"; 1181 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1182 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1183 clock-names = "pclk", "mclk"; 1184 status = "disabled"; 1185 }; 1186 1187 tdmout_a: audio-controller@500 { 1188 compatible = "amlogic,axg-tdmout"; 1189 reg = <0x0 0x500 0x0 0x40>; 1190 sound-name-prefix = "TDMOUT_A"; 1191 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1192 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1193 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1194 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1195 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1196 clock-names = "pclk", "sclk", "sclk_sel", 1197 "lrclk", "lrclk_sel"; 1198 status = "disabled"; 1199 }; 1200 1201 tdmout_b: audio-controller@540 { 1202 compatible = "amlogic,axg-tdmout"; 1203 reg = <0x0 0x540 0x0 0x40>; 1204 sound-name-prefix = "TDMOUT_B"; 1205 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1206 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1207 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1208 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1209 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1210 clock-names = "pclk", "sclk", "sclk_sel", 1211 "lrclk", "lrclk_sel"; 1212 status = "disabled"; 1213 }; 1214 1215 tdmout_c: audio-controller@580 { 1216 compatible = "amlogic,axg-tdmout"; 1217 reg = <0x0 0x580 0x0 0x40>; 1218 sound-name-prefix = "TDMOUT_C"; 1219 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1220 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1221 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1222 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1223 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1224 clock-names = "pclk", "sclk", "sclk_sel", 1225 "lrclk", "lrclk_sel"; 1226 status = "disabled"; 1227 }; 1228 }; 1229 1230 aobus: bus@ff800000 { 1231 compatible = "simple-bus"; 1232 reg = <0x0 0xff800000 0x0 0x100000>; 1233 #address-cells = <2>; 1234 #size-cells = <2>; 1235 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1236 1237 sysctrl_AO: sys-ctrl@0 { 1238 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1239 reg = <0x0 0x0 0x0 0x100>; 1240 1241 clkc_AO: clock-controller { 1242 compatible = "amlogic,meson-axg-aoclkc"; 1243 #clock-cells = <1>; 1244 #reset-cells = <1>; 1245 }; 1246 }; 1247 1248 pinctrl_aobus: pinctrl@14 { 1249 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1250 #address-cells = <2>; 1251 #size-cells = <2>; 1252 ranges; 1253 1254 gpio_ao: bank@14 { 1255 reg = <0x0 0x00014 0x0 0x8>, 1256 <0x0 0x0002c 0x0 0x4>, 1257 <0x0 0x00024 0x0 0x8>; 1258 reg-names = "mux", "pull", "gpio"; 1259 gpio-controller; 1260 #gpio-cells = <2>; 1261 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1262 }; 1263 1264 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1265 mux { 1266 groups = "i2c_ao_sck_4"; 1267 function = "i2c_ao"; 1268 }; 1269 }; 1270 1271 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1272 mux { 1273 groups = "i2c_ao_sck_8"; 1274 function = "i2c_ao"; 1275 }; 1276 }; 1277 1278 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1279 mux { 1280 groups = "i2c_ao_sck_10"; 1281 function = "i2c_ao"; 1282 }; 1283 }; 1284 1285 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1286 mux { 1287 groups = "i2c_ao_sda_5"; 1288 function = "i2c_ao"; 1289 }; 1290 }; 1291 1292 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1293 mux { 1294 groups = "i2c_ao_sda_9"; 1295 function = "i2c_ao"; 1296 }; 1297 }; 1298 1299 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1300 mux { 1301 groups = "i2c_ao_sda_11"; 1302 function = "i2c_ao"; 1303 }; 1304 }; 1305 1306 remote_input_ao_pins: remote_input_ao { 1307 mux { 1308 groups = "remote_input_ao"; 1309 function = "remote_input_ao"; 1310 }; 1311 }; 1312 1313 uart_ao_a_pins: uart_ao_a { 1314 mux { 1315 groups = "uart_ao_tx_a", 1316 "uart_ao_rx_a"; 1317 function = "uart_ao_a"; 1318 }; 1319 }; 1320 1321 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1322 mux { 1323 groups = "uart_ao_cts_a", 1324 "uart_ao_rts_a"; 1325 function = "uart_ao_a"; 1326 }; 1327 }; 1328 1329 uart_ao_b_pins: uart_ao_b { 1330 mux { 1331 groups = "uart_ao_tx_b", 1332 "uart_ao_rx_b"; 1333 function = "uart_ao_b"; 1334 }; 1335 }; 1336 1337 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1338 mux { 1339 groups = "uart_ao_cts_b", 1340 "uart_ao_rts_b"; 1341 function = "uart_ao_b"; 1342 }; 1343 }; 1344 }; 1345 1346 sec_AO: ao-secure@140 { 1347 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1348 reg = <0x0 0x140 0x0 0x140>; 1349 amlogic,has-chip-id; 1350 }; 1351 1352 pwm_AO_cd: pwm@2000 { 1353 compatible = "amlogic,meson-axg-ao-pwm"; 1354 reg = <0x0 0x02000 0x0 0x20>; 1355 #pwm-cells = <3>; 1356 status = "disabled"; 1357 }; 1358 1359 uart_AO: serial@3000 { 1360 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1361 reg = <0x0 0x3000 0x0 0x18>; 1362 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1363 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1364 clock-names = "xtal", "pclk", "baud"; 1365 status = "disabled"; 1366 }; 1367 1368 uart_AO_B: serial@4000 { 1369 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1370 reg = <0x0 0x4000 0x0 0x18>; 1371 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1372 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1373 clock-names = "xtal", "pclk", "baud"; 1374 status = "disabled"; 1375 }; 1376 1377 i2c_AO: i2c@5000 { 1378 compatible = "amlogic,meson-axg-i2c"; 1379 reg = <0x0 0x05000 0x0 0x20>; 1380 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1381 clocks = <&clkc CLKID_AO_I2C>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 pwm_AO_ab: pwm@7000 { 1388 compatible = "amlogic,meson-axg-ao-pwm"; 1389 reg = <0x0 0x07000 0x0 0x20>; 1390 #pwm-cells = <3>; 1391 status = "disabled"; 1392 }; 1393 1394 ir: ir@8000 { 1395 compatible = "amlogic,meson-gxbb-ir"; 1396 reg = <0x0 0x8000 0x0 0x20>; 1397 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1398 status = "disabled"; 1399 }; 1400 1401 saradc: adc@9000 { 1402 compatible = "amlogic,meson-axg-saradc", 1403 "amlogic,meson-saradc"; 1404 reg = <0x0 0x9000 0x0 0x38>; 1405 #io-channel-cells = <1>; 1406 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1407 clocks = <&xtal>, 1408 <&clkc_AO CLKID_AO_SAR_ADC>, 1409 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1410 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1411 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1412 status = "disabled"; 1413 }; 1414 }; 1415 1416 gic: interrupt-controller@ffc01000 { 1417 compatible = "arm,gic-400"; 1418 reg = <0x0 0xffc01000 0 0x1000>, 1419 <0x0 0xffc02000 0 0x2000>, 1420 <0x0 0xffc04000 0 0x2000>, 1421 <0x0 0xffc06000 0 0x2000>; 1422 interrupt-controller; 1423 interrupts = <GIC_PPI 9 1424 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1425 #interrupt-cells = <3>; 1426 #address-cells = <0>; 1427 }; 1428 1429 cbus: bus@ffd00000 { 1430 compatible = "simple-bus"; 1431 reg = <0x0 0xffd00000 0x0 0x25000>; 1432 #address-cells = <2>; 1433 #size-cells = <2>; 1434 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1435 1436 reset: reset-controller@1004 { 1437 compatible = "amlogic,meson-axg-reset"; 1438 reg = <0x0 0x01004 0x0 0x9c>; 1439 #reset-cells = <1>; 1440 }; 1441 1442 gpio_intc: interrupt-controller@f080 { 1443 compatible = "amlogic,meson-gpio-intc"; 1444 reg = <0x0 0xf080 0x0 0x10>; 1445 interrupt-controller; 1446 #interrupt-cells = <2>; 1447 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1448 status = "disabled"; 1449 }; 1450 1451 pwm_ab: pwm@1b000 { 1452 compatible = "amlogic,meson-axg-ee-pwm"; 1453 reg = <0x0 0x1b000 0x0 0x20>; 1454 #pwm-cells = <3>; 1455 status = "disabled"; 1456 }; 1457 1458 pwm_cd: pwm@1a000 { 1459 compatible = "amlogic,meson-axg-ee-pwm"; 1460 reg = <0x0 0x1a000 0x0 0x20>; 1461 #pwm-cells = <3>; 1462 status = "disabled"; 1463 }; 1464 1465 spicc0: spi@13000 { 1466 compatible = "amlogic,meson-axg-spicc"; 1467 reg = <0x0 0x13000 0x0 0x3c>; 1468 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&clkc CLKID_SPICC0>; 1470 clock-names = "core"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 spicc1: spi@15000 { 1477 compatible = "amlogic,meson-axg-spicc"; 1478 reg = <0x0 0x15000 0x0 0x3c>; 1479 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&clkc CLKID_SPICC1>; 1481 clock-names = "core"; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 i2c3: i2c@1c000 { 1488 compatible = "amlogic,meson-axg-i2c"; 1489 reg = <0x0 0x1c000 0x0 0x20>; 1490 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1491 clocks = <&clkc CLKID_I2C>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 status = "disabled"; 1495 }; 1496 1497 i2c2: i2c@1d000 { 1498 compatible = "amlogic,meson-axg-i2c"; 1499 reg = <0x0 0x1d000 0x0 0x20>; 1500 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1501 clocks = <&clkc CLKID_I2C>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 1507 i2c1: i2c@1e000 { 1508 compatible = "amlogic,meson-axg-i2c"; 1509 reg = <0x0 0x1e000 0x0 0x20>; 1510 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1511 clocks = <&clkc CLKID_I2C>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 }; 1516 1517 i2c0: i2c@1f000 { 1518 compatible = "amlogic,meson-axg-i2c"; 1519 reg = <0x0 0x1f000 0x0 0x20>; 1520 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1521 clocks = <&clkc CLKID_I2C>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 uart_B: serial@23000 { 1528 compatible = "amlogic,meson-gx-uart"; 1529 reg = <0x0 0x23000 0x0 0x18>; 1530 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1531 status = "disabled"; 1532 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1533 clock-names = "xtal", "pclk", "baud"; 1534 }; 1535 1536 uart_A: serial@24000 { 1537 compatible = "amlogic,meson-gx-uart"; 1538 reg = <0x0 0x24000 0x0 0x18>; 1539 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1540 status = "disabled"; 1541 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1542 clock-names = "xtal", "pclk", "baud"; 1543 }; 1544 }; 1545 1546 apb: bus@ffe00000 { 1547 compatible = "simple-bus"; 1548 reg = <0x0 0xffe00000 0x0 0x200000>; 1549 #address-cells = <2>; 1550 #size-cells = <2>; 1551 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1552 1553 sd_emmc_b: sd@5000 { 1554 compatible = "amlogic,meson-axg-mmc"; 1555 reg = <0x0 0x5000 0x0 0x800>; 1556 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1557 status = "disabled"; 1558 clocks = <&clkc CLKID_SD_EMMC_B>, 1559 <&clkc CLKID_SD_EMMC_B_CLK0>, 1560 <&clkc CLKID_FCLK_DIV2>; 1561 clock-names = "core", "clkin0", "clkin1"; 1562 resets = <&reset RESET_SD_EMMC_B>; 1563 }; 1564 1565 sd_emmc_c: mmc@7000 { 1566 compatible = "amlogic,meson-axg-mmc"; 1567 reg = <0x0 0x7000 0x0 0x800>; 1568 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1569 status = "disabled"; 1570 clocks = <&clkc CLKID_SD_EMMC_C>, 1571 <&clkc CLKID_SD_EMMC_C_CLK0>, 1572 <&clkc CLKID_FCLK_DIV2>; 1573 clock-names = "core", "clkin0", "clkin1"; 1574 resets = <&reset RESET_SD_EMMC_C>; 1575 }; 1576 }; 1577 1578 sram: sram@fffc0000 { 1579 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1580 reg = <0x0 0xfffc0000 0x0 0x20000>; 1581 #address-cells = <1>; 1582 #size-cells = <1>; 1583 ranges = <0 0x0 0xfffc0000 0x20000>; 1584 1585 cpu_scp_lpri: scp-shmem@13000 { 1586 compatible = "amlogic,meson-axg-scp-shmem"; 1587 reg = <0x13000 0x400>; 1588 }; 1589 1590 cpu_scp_hpri: scp-shmem@13400 { 1591 compatible = "amlogic,meson-axg-scp-shmem"; 1592 reg = <0x13400 0x400>; 1593 }; 1594 }; 1595 }; 1596 1597 timer { 1598 compatible = "arm,armv8-timer"; 1599 interrupts = <GIC_PPI 13 1600 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1601 <GIC_PPI 14 1602 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1603 <GIC_PPI 11 1604 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1605 <GIC_PPI 10 1606 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1607 }; 1608 1609 xtal: xtal-clk { 1610 compatible = "fixed-clock"; 1611 clock-frequency = <24000000>; 1612 clock-output-names = "xtal"; 1613 #clock-cells = <0>; 1614 }; 1615}; 1616