1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		cbus: bus@ffd00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffd00000 0x0 0x25000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
123
124			pwm_ab: pwm@1b000 {
125				compatible = "amlogic,meson-axg-ee-pwm";
126				reg = <0x0 0x1b000 0x0 0x20>;
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			pwm_cd: pwm@1a000 {
132				compatible = "amlogic,meson-axg-ee-pwm";
133				reg = <0x0 0x1a000 0x0 0x20>;
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			reset: reset-controller@1004 {
139				compatible = "amlogic,meson-axg-reset";
140				reg = <0x0 0x01004 0x0 0x9c>;
141				#reset-cells = <1>;
142			};
143
144			spicc0: spi@13000 {
145				compatible = "amlogic,meson-axg-spicc";
146				reg = <0x0 0x13000 0x0 0x3c>;
147				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clkc CLKID_SPICC0>;
149				clock-names = "core";
150				#address-cells = <1>;
151				#size-cells = <0>;
152				status = "disabled";
153			};
154
155			spicc1: spi@15000 {
156				compatible = "amlogic,meson-axg-spicc";
157				reg = <0x0 0x15000 0x0 0x3c>;
158				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159				clocks = <&clkc CLKID_SPICC1>;
160				clock-names = "core";
161				#address-cells = <1>;
162				#size-cells = <0>;
163				status = "disabled";
164			};
165
166			uart_A: serial@24000 {
167				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
168				reg = <0x0 0x24000 0x0 0x14>;
169				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
170				status = "disabled";
171			};
172
173			uart_B: serial@23000 {
174				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
175				reg = <0x0 0x23000 0x0 0x14>;
176				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
177				status = "disabled";
178			};
179		};
180
181		gic: interrupt-controller@ffc01000 {
182			compatible = "arm,gic-400";
183			reg = <0x0 0xffc01000 0 0x1000>,
184			      <0x0 0xffc02000 0 0x2000>,
185			      <0x0 0xffc04000 0 0x2000>,
186			      <0x0 0xffc06000 0 0x2000>;
187			interrupt-controller;
188			interrupts = <GIC_PPI 9
189				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
190			#interrupt-cells = <3>;
191			#address-cells = <0>;
192		};
193
194		hiubus: bus@ff63c000 {
195			compatible = "simple-bus";
196			reg = <0x0 0xff63c000 0x0 0x1c00>;
197			#address-cells = <2>;
198			#size-cells = <2>;
199			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
200
201			clkc: clock-controller@0 {
202				compatible = "amlogic,axg-clkc";
203				#clock-cells = <1>;
204				reg = <0x0 0x0 0x0 0x320>;
205			};
206		};
207
208		mailbox: mailbox@ff63dc00 {
209			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
210			reg = <0 0xff63dc00 0 0x400>;
211			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
212				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
213				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
214			#mbox-cells = <1>;
215		};
216
217		periphs: periphs@ff634000 {
218			compatible = "simple-bus";
219			reg = <0x0 0xff634000 0x0 0x2000>;
220			#address-cells = <2>;
221			#size-cells = <2>;
222			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
223
224			pinctrl_periphs: pinctrl@480 {
225				compatible = "amlogic,meson-axg-periphs-pinctrl";
226				#address-cells = <2>;
227				#size-cells = <2>;
228				ranges;
229
230				gpio: bank@480 {
231					reg = <0x0 0x00480 0x0 0x40>,
232						<0x0 0x004e8 0x0 0x14>,
233						<0x0 0x00520 0x0 0x14>,
234						<0x0 0x00430 0x0 0x3c>;
235					reg-names = "mux", "pull", "pull-enable", "gpio";
236					gpio-controller;
237					#gpio-cells = <2>;
238					gpio-ranges = <&pinctrl_periphs 0 0 86>;
239				};
240
241				pwm_a_a_pins: pwm_a_a {
242					mux {
243						groups = "pwm_a_a";
244						function = "pwm_a";
245					};
246				};
247
248				pwm_a_x18_pins: pwm_a_x18 {
249					mux {
250						groups = "pwm_a_x18";
251						function = "pwm_a";
252					};
253				};
254
255				pwm_a_x20_pins: pwm_a_x20 {
256					mux {
257						groups = "pwm_a_x20";
258						function = "pwm_a";
259					};
260				};
261
262				pwm_a_z_pins: pwm_a_z {
263					mux {
264						groups = "pwm_a_z";
265						function = "pwm_a";
266					};
267				};
268
269				pwm_b_a_pins: pwm_b_a {
270					mux {
271						groups = "pwm_b_a";
272						function = "pwm_b";
273					};
274				};
275
276				pwm_b_x_pins: pwm_b_x {
277					mux {
278						groups = "pwm_b_x";
279						function = "pwm_b";
280					};
281				};
282
283				pwm_b_z_pins: pwm_b_z {
284					mux {
285						groups = "pwm_b_z";
286						function = "pwm_b";
287					};
288				};
289
290				pwm_c_a_pins: pwm_c_a {
291					mux {
292						groups = "pwm_c_a";
293						function = "pwm_c";
294					};
295				};
296
297				pwm_c_x10_pins: pwm_c_x10 {
298					mux {
299						groups = "pwm_c_x10";
300						function = "pwm_c";
301					};
302				};
303
304				pwm_c_x17_pins: pwm_c_x17 {
305					mux {
306						groups = "pwm_c_x17";
307						function = "pwm_c";
308					};
309				};
310
311				pwm_d_x11_pins: pwm_d_x11 {
312					mux {
313						groups = "pwm_d_x11";
314						function = "pwm_d";
315					};
316				};
317
318				pwm_d_x16_pins: pwm_d_x16 {
319					mux {
320						groups = "pwm_d_x16";
321						function = "pwm_d";
322					};
323				};
324
325				spi0_pins: spi0 {
326					mux {
327						groups = "spi0_miso",
328							"spi0_mosi",
329							"spi0_clk";
330						function = "spi0";
331					};
332				};
333
334				spi0_ss0_pins: spi0_ss0 {
335					mux {
336						groups = "spi0_ss0";
337						function = "spi0";
338					};
339				};
340
341				spi0_ss1_pins: spi0_ss1 {
342					mux {
343						groups = "spi0_ss1";
344						function = "spi0";
345					};
346				};
347
348				spi0_ss2_pins: spi0_ss2 {
349					mux {
350						groups = "spi0_ss2";
351						function = "spi0";
352					};
353				};
354
355
356				spi1_a_pins: spi1_a {
357					mux {
358						groups = "spi1_miso_a",
359							"spi1_mosi_a",
360							"spi1_clk_a";
361						function = "spi1";
362					};
363				};
364
365				spi1_ss0_a_pins: spi1_ss0_a {
366					mux {
367						groups = "spi1_ss0_a";
368						function = "spi1";
369					};
370				};
371
372				spi1_ss1_pins: spi1_ss1 {
373					mux {
374						groups = "spi1_ss1";
375						function = "spi1";
376					};
377				};
378
379				spi1_x_pins: spi1_x {
380					mux {
381						groups = "spi1_miso_x",
382							"spi1_mosi_x",
383							"spi1_clk_x";
384						function = "spi1";
385					};
386				};
387
388				spi1_ss0_x_pins: spi1_ss0_x {
389					mux {
390						groups = "spi1_ss0_x";
391						function = "spi1";
392					};
393				};
394			};
395		};
396
397		sram: sram@fffc0000 {
398			compatible = "amlogic,meson-axg-sram", "mmio-sram";
399			reg = <0x0 0xfffc0000 0x0 0x20000>;
400			#address-cells = <1>;
401			#size-cells = <1>;
402			ranges = <0 0x0 0xfffc0000 0x20000>;
403
404			cpu_scp_lpri: scp-shmem@0 {
405				compatible = "amlogic,meson-axg-scp-shmem";
406				reg = <0x13000 0x400>;
407			};
408
409			cpu_scp_hpri: scp-shmem@200 {
410				compatible = "amlogic,meson-axg-scp-shmem";
411				reg = <0x13400 0x400>;
412			};
413		};
414
415		aobus: bus@ff800000 {
416			compatible = "simple-bus";
417			reg = <0x0 0xff800000 0x0 0x100000>;
418			#address-cells = <2>;
419			#size-cells = <2>;
420			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
421
422			pinctrl_aobus: pinctrl@14 {
423				compatible = "amlogic,meson-axg-aobus-pinctrl";
424				#address-cells = <2>;
425				#size-cells = <2>;
426				ranges;
427
428				gpio_ao: bank@14 {
429					reg = <0x0 0x00014 0x0 0x8>,
430						<0x0 0x0002c 0x0 0x4>,
431						<0x0 0x00024 0x0 0x8>;
432					reg-names = "mux", "pull", "gpio";
433					gpio-controller;
434					#gpio-cells = <2>;
435					gpio-ranges = <&pinctrl_aobus 0 0 15>;
436				};
437
438				remote_input_ao_pins: remote_input_ao {
439					mux {
440						groups = "remote_input_ao";
441						function = "remote_input_ao";
442					};
443				};
444			};
445
446			pwm_AO_ab: pwm@7000 {
447				compatible = "amlogic,meson-axg-ao-pwm";
448				reg = <0x0 0x07000 0x0 0x20>;
449				#pwm-cells = <3>;
450				status = "disabled";
451			};
452
453			pwm_AO_cd: pwm@2000 {
454				compatible = "amlogic,axg-ao-pwm";
455				reg = <0x0 0x02000  0x0 0x20>;
456				#pwm-cells = <3>;
457				status = "disabled";
458			};
459
460			uart_AO: serial@3000 {
461				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
462				reg = <0x0 0x3000 0x0 0x18>;
463				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
464				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
465				clock-names = "xtal", "pclk", "baud";
466				status = "disabled";
467			};
468
469			uart_AO_B: serial@4000 {
470				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
471				reg = <0x0 0x4000 0x0 0x18>;
472				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
473				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
474				clock-names = "xtal", "pclk", "baud";
475				status = "disabled";
476			};
477
478			ir: ir@8000 {
479				compatible = "amlogic,meson-gxbb-ir";
480				reg = <0x0 0x8000 0x0 0x20>;
481				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
482				status = "disabled";
483			};
484		};
485	};
486};
487