1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10#include <dt-bindings/clock/axg-aoclkc.h>
11#include <dt-bindings/gpio/meson-axg-gpio.h>
12#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
13
14/ {
15	compatible = "amlogic,meson-axg";
16
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	reserved-memory {
22		#address-cells = <2>;
23		#size-cells = <2>;
24		ranges;
25
26		/* 16 MiB reserved for Hardware ROM Firmware */
27		hwrom_reserved: hwrom@0 {
28			reg = <0x0 0x0 0x0 0x1000000>;
29			no-map;
30		};
31
32		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
33		secmon_reserved: secmon@5000000 {
34			reg = <0x0 0x05000000 0x0 0x300000>;
35			no-map;
36		};
37	};
38
39	cpus {
40		#address-cells = <0x2>;
41		#size-cells = <0x0>;
42
43		cpu0: cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53", "arm,armv8";
46			reg = <0x0 0x0>;
47			enable-method = "psci";
48			next-level-cache = <&l2>;
49		};
50
51		cpu1: cpu@1 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53", "arm,armv8";
54			reg = <0x0 0x1>;
55			enable-method = "psci";
56			next-level-cache = <&l2>;
57		};
58
59		cpu2: cpu@2 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53", "arm,armv8";
62			reg = <0x0 0x2>;
63			enable-method = "psci";
64			next-level-cache = <&l2>;
65		};
66
67		cpu3: cpu@3 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53", "arm,armv8";
70			reg = <0x0 0x3>;
71			enable-method = "psci";
72			next-level-cache = <&l2>;
73		};
74
75		l2: l2-cache0 {
76			compatible = "cache";
77		};
78	};
79
80	arm-pmu {
81		compatible = "arm,cortex-a53-pmu";
82		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
87	};
88
89	psci {
90		compatible = "arm,psci-1.0";
91		method = "smc";
92	};
93
94	timer {
95		compatible = "arm,armv8-timer";
96		interrupts = <GIC_PPI 13
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 14
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 11
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
102			     <GIC_PPI 10
103			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
104	};
105
106	xtal: xtal-clk {
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "xtal";
110		#clock-cells = <0>;
111	};
112
113	ao_alt_xtal: ao_alt_xtal-clk {
114		compatible = "fixed-clock";
115		clock-frequency = <32000000>;
116		clock-output-names = "ao_alt_xtal";
117		#clock-cells = <0>;
118	};
119
120	soc {
121		compatible = "simple-bus";
122		#address-cells = <2>;
123		#size-cells = <2>;
124		ranges;
125
126		apb: apb@ffe00000 {
127			compatible = "simple-bus";
128			reg = <0x0 0xffe00000 0x0 0x200000>;
129			#address-cells = <2>;
130			#size-cells = <2>;
131			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
132
133			sd_emmc_b: sd@5000 {
134				compatible = "amlogic,meson-axg-mmc";
135				reg = <0x0 0x5000 0x0 0x800>;
136				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
137				status = "disabled";
138				clocks = <&clkc CLKID_SD_EMMC_B>,
139					<&clkc CLKID_SD_EMMC_B_CLK0>,
140					<&clkc CLKID_FCLK_DIV2>;
141				clock-names = "core", "clkin0", "clkin1";
142				resets = <&reset RESET_SD_EMMC_B>;
143			};
144
145			sd_emmc_c: mmc@7000 {
146				compatible = "amlogic,meson-axg-mmc";
147				reg = <0x0 0x7000 0x0 0x800>;
148				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
149				status = "disabled";
150				clocks = <&clkc CLKID_SD_EMMC_C>,
151					<&clkc CLKID_SD_EMMC_C_CLK0>,
152					<&clkc CLKID_FCLK_DIV2>;
153				clock-names = "core", "clkin0", "clkin1";
154				resets = <&reset RESET_SD_EMMC_C>;
155			};
156		};
157
158		cbus: bus@ffd00000 {
159			compatible = "simple-bus";
160			reg = <0x0 0xffd00000 0x0 0x25000>;
161			#address-cells = <2>;
162			#size-cells = <2>;
163			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
164
165			gpio_intc: interrupt-controller@f080 {
166				compatible = "amlogic,meson-gpio-intc";
167				reg = <0x0 0xf080 0x0 0x10>;
168				interrupt-controller;
169				#interrupt-cells = <2>;
170				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
171				status = "disabled";
172			};
173
174			pwm_ab: pwm@1b000 {
175				compatible = "amlogic,meson-axg-ee-pwm";
176				reg = <0x0 0x1b000 0x0 0x20>;
177				#pwm-cells = <3>;
178				status = "disabled";
179			};
180
181			pwm_cd: pwm@1a000 {
182				compatible = "amlogic,meson-axg-ee-pwm";
183				reg = <0x0 0x1a000 0x0 0x20>;
184				#pwm-cells = <3>;
185				status = "disabled";
186			};
187
188			reset: reset-controller@1004 {
189				compatible = "amlogic,meson-axg-reset";
190				reg = <0x0 0x01004 0x0 0x9c>;
191				#reset-cells = <1>;
192			};
193
194			spicc0: spi@13000 {
195				compatible = "amlogic,meson-axg-spicc";
196				reg = <0x0 0x13000 0x0 0x3c>;
197				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
198				clocks = <&clkc CLKID_SPICC0>;
199				clock-names = "core";
200				#address-cells = <1>;
201				#size-cells = <0>;
202				status = "disabled";
203			};
204
205			spicc1: spi@15000 {
206				compatible = "amlogic,meson-axg-spicc";
207				reg = <0x0 0x15000 0x0 0x3c>;
208				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
209				clocks = <&clkc CLKID_SPICC1>;
210				clock-names = "core";
211				#address-cells = <1>;
212				#size-cells = <0>;
213				status = "disabled";
214			};
215
216			i2c0: i2c@1f000 {
217				compatible = "amlogic,meson-axg-i2c";
218				reg = <0x0 0x1f000 0x0 0x20>;
219				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
220				clocks = <&clkc CLKID_I2C>;
221				#address-cells = <1>;
222				#size-cells = <0>;
223				status = "disabled";
224			};
225
226			i2c1: i2c@1e000 {
227				compatible = "amlogic,meson-axg-i2c";
228				reg = <0x0 0x1e000 0x0 0x20>;
229				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
230				clocks = <&clkc CLKID_I2C>;
231				#address-cells = <1>;
232				#size-cells = <0>;
233				status = "disabled";
234			};
235
236			i2c2: i2c@1d000 {
237				compatible = "amlogic,meson-axg-i2c";
238				reg = <0x0 0x1d000 0x0 0x20>;
239				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
240				clocks = <&clkc CLKID_I2C>;
241				#address-cells = <1>;
242				#size-cells = <0>;
243				status = "disabled";
244			};
245
246			i2c3: i2c@1c000 {
247				compatible = "amlogic,meson-axg-i2c";
248				reg = <0x0 0x1c000 0x0 0x20>;
249				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
250				clocks = <&clkc CLKID_I2C>;
251				#address-cells = <1>;
252				#size-cells = <0>;
253				status = "disabled";
254			};
255
256			uart_A: serial@24000 {
257				compatible = "amlogic,meson-gx-uart";
258				reg = <0x0 0x24000 0x0 0x18>;
259				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
260				status = "disabled";
261				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
262				clock-names = "xtal", "pclk", "baud";
263			};
264
265			uart_B: serial@23000 {
266				compatible = "amlogic,meson-gx-uart";
267				reg = <0x0 0x23000 0x0 0x18>;
268				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
269				status = "disabled";
270				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
271				clock-names = "xtal", "pclk", "baud";
272			};
273		};
274
275		ethmac: ethernet@ff3f0000 {
276			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
277			reg = <0x0 0xff3f0000 0x0 0x10000
278				0x0 0xff634540 0x0 0x8>;
279			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
280			interrupt-names = "macirq";
281			clocks = <&clkc CLKID_ETH>,
282				 <&clkc CLKID_FCLK_DIV2>,
283				 <&clkc CLKID_MPLL2>;
284			clock-names = "stmmaceth", "clkin0", "clkin1";
285			status = "disabled";
286		};
287
288		gic: interrupt-controller@ffc01000 {
289			compatible = "arm,gic-400";
290			reg = <0x0 0xffc01000 0 0x1000>,
291			      <0x0 0xffc02000 0 0x2000>,
292			      <0x0 0xffc04000 0 0x2000>,
293			      <0x0 0xffc06000 0 0x2000>;
294			interrupt-controller;
295			interrupts = <GIC_PPI 9
296				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
297			#interrupt-cells = <3>;
298			#address-cells = <0>;
299		};
300
301		hiubus: bus@ff63c000 {
302			compatible = "simple-bus";
303			reg = <0x0 0xff63c000 0x0 0x1c00>;
304			#address-cells = <2>;
305			#size-cells = <2>;
306			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
307
308			sysctrl: system-controller@0 {
309				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
310				reg = <0 0 0 0x400>;
311
312				clkc: clock-controller {
313					compatible = "amlogic,axg-clkc";
314					#clock-cells = <1>;
315				};
316			};
317		};
318
319		mailbox: mailbox@ff63dc00 {
320			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
321			reg = <0 0xff63dc00 0 0x400>;
322			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
323				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
324				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
325			#mbox-cells = <1>;
326		};
327
328		periphs: periphs@ff634000 {
329			compatible = "simple-bus";
330			reg = <0x0 0xff634000 0x0 0x2000>;
331			#address-cells = <2>;
332			#size-cells = <2>;
333			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
334
335			hwrng: rng {
336				compatible = "amlogic,meson-rng";
337				reg = <0x0 0x18 0x0 0x4>;
338				clocks = <&clkc CLKID_RNG0>;
339				clock-names = "core";
340			};
341
342			pinctrl_periphs: pinctrl@480 {
343				compatible = "amlogic,meson-axg-periphs-pinctrl";
344				#address-cells = <2>;
345				#size-cells = <2>;
346				ranges;
347
348				gpio: bank@480 {
349					reg = <0x0 0x00480 0x0 0x40>,
350						<0x0 0x004e8 0x0 0x14>,
351						<0x0 0x00520 0x0 0x14>,
352						<0x0 0x00430 0x0 0x3c>;
353					reg-names = "mux", "pull", "pull-enable", "gpio";
354					gpio-controller;
355					#gpio-cells = <2>;
356					gpio-ranges = <&pinctrl_periphs 0 0 86>;
357				};
358
359				emmc_pins: emmc {
360					mux {
361						groups = "emmc_nand_d0",
362							"emmc_nand_d1",
363							"emmc_nand_d2",
364							"emmc_nand_d3",
365							"emmc_nand_d4",
366							"emmc_nand_d5",
367							"emmc_nand_d6",
368							"emmc_nand_d7",
369							"emmc_clk",
370							"emmc_cmd",
371							"emmc_ds";
372						function = "emmc";
373					};
374				};
375
376				emmc_clk_gate_pins: emmc_clk_gate {
377					mux {
378						groups = "BOOT_8";
379						function = "gpio_periphs";
380					};
381					cfg-pull-down {
382						pins = "BOOT_8";
383						bias-pull-down;
384					};
385				};
386
387				sdio_pins: sdio {
388					mux {
389						groups = "sdio_d0",
390							"sdio_d1",
391							"sdio_d2",
392							"sdio_d3",
393							"sdio_cmd",
394							"sdio_clk";
395						function = "sdio";
396					};
397				};
398
399				sdio_clk_gate_pins: sdio_clk_gate {
400					mux {
401						groups = "GPIOX_4";
402						function = "gpio_periphs";
403					};
404					cfg-pull-down {
405						pins = "GPIOX_4";
406						bias-pull-down;
407					};
408				};
409
410				eth_rmii_x_pins: eth-x-rmii {
411					mux {
412						groups = "eth_mdio_x",
413						       "eth_mdc_x",
414						       "eth_rgmii_rx_clk_x",
415						       "eth_rx_dv_x",
416						       "eth_rxd0_x",
417						       "eth_rxd1_x",
418						       "eth_txen_x",
419						       "eth_txd0_x",
420						       "eth_txd1_x";
421						function = "eth";
422					};
423				};
424
425				eth_rmii_y_pins: eth-y-rmii {
426					mux {
427						groups = "eth_mdio_y",
428						       "eth_mdc_y",
429						       "eth_rgmii_rx_clk_y",
430						       "eth_rx_dv_y",
431						       "eth_rxd0_y",
432						       "eth_rxd1_y",
433						       "eth_txen_y",
434						       "eth_txd0_y",
435						       "eth_txd1_y";
436						function = "eth";
437					};
438				};
439
440				eth_rgmii_x_pins: eth-x-rgmii {
441					mux {
442						groups = "eth_mdio_x",
443						       "eth_mdc_x",
444						       "eth_rgmii_rx_clk_x",
445						       "eth_rx_dv_x",
446						       "eth_rxd0_x",
447						       "eth_rxd1_x",
448						       "eth_rxd2_rgmii",
449						       "eth_rxd3_rgmii",
450						       "eth_rgmii_tx_clk",
451						       "eth_txen_x",
452						       "eth_txd0_x",
453						       "eth_txd1_x",
454						       "eth_txd2_rgmii",
455						       "eth_txd3_rgmii";
456						function = "eth";
457					};
458				};
459
460				eth_rgmii_y_pins: eth-y-rgmii {
461					mux {
462						groups = "eth_mdio_y",
463						       "eth_mdc_y",
464						       "eth_rgmii_rx_clk_y",
465						       "eth_rx_dv_y",
466						       "eth_rxd0_y",
467						       "eth_rxd1_y",
468						       "eth_rxd2_rgmii",
469						       "eth_rxd3_rgmii",
470						       "eth_rgmii_tx_clk",
471						       "eth_txen_y",
472						       "eth_txd0_y",
473						       "eth_txd1_y",
474						       "eth_txd2_rgmii",
475						       "eth_txd3_rgmii";
476						function = "eth";
477					};
478				};
479
480				pdm_dclk_a14_pins: pdm_dclk_a14 {
481					mux {
482						groups = "pdm_dclk_a14";
483						function = "pdm";
484					};
485				};
486
487				pdm_dclk_a19_pins: pdm_dclk_a19 {
488					mux {
489						groups = "pdm_dclk_a19";
490						function = "pdm";
491					};
492				};
493
494				pdm_din0_pins: pdm_din0 {
495					mux {
496						groups = "pdm_din0";
497						function = "pdm";
498					};
499				};
500
501				pdm_din1_pins: pdm_din1 {
502					mux {
503						groups = "pdm_din1";
504						function = "pdm";
505					};
506				};
507
508				pdm_din2_pins: pdm_din2 {
509					mux {
510						groups = "pdm_din2";
511						function = "pdm";
512					};
513				};
514
515				pdm_din3_pins: pdm_din3 {
516					mux {
517						groups = "pdm_din3";
518						function = "pdm";
519					};
520				};
521
522				pwm_a_a_pins: pwm_a_a {
523					mux {
524						groups = "pwm_a_a";
525						function = "pwm_a";
526					};
527				};
528
529				pwm_a_x18_pins: pwm_a_x18 {
530					mux {
531						groups = "pwm_a_x18";
532						function = "pwm_a";
533					};
534				};
535
536				pwm_a_x20_pins: pwm_a_x20 {
537					mux {
538						groups = "pwm_a_x20";
539						function = "pwm_a";
540					};
541				};
542
543				pwm_a_z_pins: pwm_a_z {
544					mux {
545						groups = "pwm_a_z";
546						function = "pwm_a";
547					};
548				};
549
550				pwm_b_a_pins: pwm_b_a {
551					mux {
552						groups = "pwm_b_a";
553						function = "pwm_b";
554					};
555				};
556
557				pwm_b_x_pins: pwm_b_x {
558					mux {
559						groups = "pwm_b_x";
560						function = "pwm_b";
561					};
562				};
563
564				pwm_b_z_pins: pwm_b_z {
565					mux {
566						groups = "pwm_b_z";
567						function = "pwm_b";
568					};
569				};
570
571				pwm_c_a_pins: pwm_c_a {
572					mux {
573						groups = "pwm_c_a";
574						function = "pwm_c";
575					};
576				};
577
578				pwm_c_x10_pins: pwm_c_x10 {
579					mux {
580						groups = "pwm_c_x10";
581						function = "pwm_c";
582					};
583				};
584
585				pwm_c_x17_pins: pwm_c_x17 {
586					mux {
587						groups = "pwm_c_x17";
588						function = "pwm_c";
589					};
590				};
591
592				pwm_d_x11_pins: pwm_d_x11 {
593					mux {
594						groups = "pwm_d_x11";
595						function = "pwm_d";
596					};
597				};
598
599				pwm_d_x16_pins: pwm_d_x16 {
600					mux {
601						groups = "pwm_d_x16";
602						function = "pwm_d";
603					};
604				};
605
606				spdif_in_z_pins: spdif_in_z {
607					mux {
608						groups = "spdif_in_z";
609						function = "spdif_in";
610					};
611				};
612
613				spdif_in_a1_pins: spdif_in_a1 {
614					mux {
615						groups = "spdif_in_a1";
616						function = "spdif_in";
617					};
618				};
619
620				spdif_in_a7_pins: spdif_in_a7 {
621					mux {
622						groups = "spdif_in_a7";
623						function = "spdif_in";
624					};
625				};
626
627				spdif_in_a19_pins: spdif_in_a19 {
628					mux {
629						groups = "spdif_in_a19";
630						function = "spdif_in";
631					};
632				};
633
634				spdif_in_a20_pins: spdif_in_a20 {
635					mux {
636						groups = "spdif_in_a20";
637						function = "spdif_in";
638					};
639				};
640
641				spdif_out_z_pins: spdif_out_z {
642					mux {
643						groups = "spdif_out_z";
644						function = "spdif_out";
645					};
646				};
647
648				spdif_out_a1_pins: spdif_out_a1 {
649					mux {
650						groups = "spdif_out_a1";
651						function = "spdif_out";
652					};
653				};
654
655				spdif_out_a11_pins: spdif_out_a11 {
656					mux {
657						groups = "spdif_out_a11";
658						function = "spdif_out";
659					};
660				};
661
662				spdif_out_a19_pins: spdif_out_a19 {
663					mux {
664						groups = "spdif_out_a19";
665						function = "spdif_out";
666					};
667				};
668
669				spdif_out_a20_pins: spdif_out_a20 {
670					mux {
671						groups = "spdif_out_a20";
672						function = "spdif_out";
673					};
674				};
675
676				spi0_pins: spi0 {
677					mux {
678						groups = "spi0_miso",
679							"spi0_mosi",
680							"spi0_clk";
681						function = "spi0";
682					};
683				};
684
685				spi0_ss0_pins: spi0_ss0 {
686					mux {
687						groups = "spi0_ss0";
688						function = "spi0";
689					};
690				};
691
692				spi0_ss1_pins: spi0_ss1 {
693					mux {
694						groups = "spi0_ss1";
695						function = "spi0";
696					};
697				};
698
699				spi0_ss2_pins: spi0_ss2 {
700					mux {
701						groups = "spi0_ss2";
702						function = "spi0";
703					};
704				};
705
706
707				spi1_a_pins: spi1_a {
708					mux {
709						groups = "spi1_miso_a",
710							"spi1_mosi_a",
711							"spi1_clk_a";
712						function = "spi1";
713					};
714				};
715
716				spi1_ss0_a_pins: spi1_ss0_a {
717					mux {
718						groups = "spi1_ss0_a";
719						function = "spi1";
720					};
721				};
722
723				spi1_ss1_pins: spi1_ss1 {
724					mux {
725						groups = "spi1_ss1";
726						function = "spi1";
727					};
728				};
729
730				spi1_x_pins: spi1_x {
731					mux {
732						groups = "spi1_miso_x",
733							"spi1_mosi_x",
734							"spi1_clk_x";
735						function = "spi1";
736					};
737				};
738
739				spi1_ss0_x_pins: spi1_ss0_x {
740					mux {
741						groups = "spi1_ss0_x";
742						function = "spi1";
743					};
744				};
745
746				i2c0_pins: i2c0 {
747					mux {
748						groups = "i2c0_sck",
749							"i2c0_sda";
750						function = "i2c0";
751					};
752				};
753
754				i2c1_z_pins: i2c1_z {
755					mux {
756						groups = "i2c1_sck_z",
757							"i2c1_sda_z";
758						function = "i2c1";
759					};
760				};
761
762				i2c1_x_pins: i2c1_x {
763					mux {
764						groups = "i2c1_sck_x",
765							"i2c1_sda_x";
766						function = "i2c1";
767					};
768				};
769
770				i2c2_x_pins: i2c2_x {
771					mux {
772						groups = "i2c2_sck_x",
773							"i2c2_sda_x";
774						function = "i2c2";
775					};
776				};
777
778				i2c2_a_pins: i2c2_a {
779					mux {
780						groups = "i2c2_sck_a",
781							"i2c2_sda_a";
782						function = "i2c2";
783					};
784				};
785
786				i2c3_a6_pins: i2c3_a6 {
787					mux {
788						groups = "i2c3_sda_a6",
789							"i2c3_sck_a7";
790						function = "i2c3";
791					};
792				};
793
794				i2c3_a12_pins: i2c3_a12 {
795					mux {
796						groups = "i2c3_sda_a12",
797							"i2c3_sck_a13";
798						function = "i2c3";
799					};
800				};
801
802				i2c3_a19_pins: i2c3_a19 {
803					mux {
804						groups = "i2c3_sda_a19",
805							"i2c3_sck_a20";
806						function = "i2c3";
807					};
808				};
809
810				uart_a_pins: uart_a {
811					mux {
812						groups = "uart_tx_a",
813							"uart_rx_a";
814						function = "uart_a";
815					};
816				};
817
818				uart_a_cts_rts_pins: uart_a_cts_rts {
819					mux {
820						groups = "uart_cts_a",
821							"uart_rts_a";
822						function = "uart_a";
823					};
824				};
825
826				uart_b_x_pins: uart_b_x {
827					mux {
828						groups = "uart_tx_b_x",
829							"uart_rx_b_x";
830						function = "uart_b";
831					};
832				};
833
834				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
835					mux {
836						groups = "uart_cts_b_x",
837							"uart_rts_b_x";
838						function = "uart_b";
839					};
840				};
841
842				uart_b_z_pins: uart_b_z {
843					mux {
844						groups = "uart_tx_b_z",
845							"uart_rx_b_z";
846						function = "uart_b";
847					};
848				};
849
850				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
851					mux {
852						groups = "uart_cts_b_z",
853							"uart_rts_b_z";
854						function = "uart_b";
855					};
856				};
857
858				uart_ao_b_z_pins: uart_ao_b_z {
859					mux {
860						groups = "uart_ao_tx_b_z",
861							"uart_ao_rx_b_z";
862						function = "uart_ao_b_z";
863					};
864				};
865
866				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
867					mux {
868						groups = "uart_ao_cts_b_z",
869							"uart_ao_rts_b_z";
870						function = "uart_ao_b_z";
871					};
872				};
873
874				mclk_b_pins: mclk_b {
875					mux {
876						groups = "mclk_b";
877						function = "mclk_b";
878					};
879				};
880
881				mclk_c_pins: mclk_c {
882					mux {
883						groups = "mclk_c";
884						function = "mclk_c";
885					};
886				};
887
888				tdma_sclk_pins: tdma_sclk {
889					mux {
890						groups = "tdma_sclk";
891						function = "tdma";
892					};
893				};
894
895				tdma_sclk_slv_pins: tdma_sclk_slv {
896					mux {
897						groups = "tdma_sclk_slv";
898						function = "tdma";
899					};
900				};
901
902				tdma_fs_pins: tdma_fs {
903					mux {
904						groups = "tdma_fs";
905						function = "tdma";
906					};
907				};
908
909				tdma_fs_slv_pins: tdma_fs_slv {
910					mux {
911						groups = "tdma_fs_slv";
912						function = "tdma";
913					};
914				};
915
916				tdma_din0_pins: tdma_din0 {
917					mux {
918						groups = "tdma_din0";
919						function = "tdma";
920					};
921				};
922
923				tdma_dout0_x14_pins: tdma_dout0_x14 {
924					mux {
925						groups = "tdma_dout0_x14";
926						function = "tdma";
927					};
928				};
929
930				tdma_dout0_x15_pins: tdma_dout0_x15 {
931					mux {
932						groups = "tdma_dout0_x15";
933						function = "tdma";
934					};
935				};
936
937				tdma_dout1_pins: tdma_dout1 {
938					mux {
939						groups = "tdma_dout1";
940						function = "tdma";
941					};
942				};
943
944				tdma_din1_pins: tdma_din1 {
945					mux {
946						groups = "tdma_din1";
947						function = "tdma";
948					};
949				};
950
951				tdmb_sclk_pins: tdmb_sclk {
952					mux {
953						groups = "tdmb_sclk";
954						function = "tdmb";
955					};
956				};
957
958				tdmb_sclk_slv_pins: tdmb_sclk_slv {
959					mux {
960						groups = "tdmb_sclk_slv";
961						function = "tdmb";
962					};
963				};
964
965				tdmb_fs_pins: tdmb_fs {
966					mux {
967						groups = "tdmb_fs";
968						function = "tdmb";
969					};
970				};
971
972				tdmb_fs_slv_pins: tdmb_fs_slv {
973					mux {
974						groups = "tdmb_fs_slv";
975						function = "tdmb";
976					};
977				};
978
979				tdmb_din0_pins: tdmb_din0 {
980					mux {
981						groups = "tdmb_din0";
982						function = "tdmb";
983					};
984				};
985
986				tdmb_dout0_pins: tdmb_dout0 {
987					mux {
988						groups = "tdmb_dout0";
989						function = "tdmb";
990					};
991				};
992
993				tdmb_din1_pins: tdmb_din1 {
994					mux {
995						groups = "tdmb_din1";
996						function = "tdmb";
997					};
998				};
999
1000				tdmb_dout1_pins: tdmb_dout1 {
1001					mux {
1002						groups = "tdmb_dout1";
1003						function = "tdmb";
1004					};
1005				};
1006
1007				tdmb_din2_pins: tdmb_din2 {
1008					mux {
1009						groups = "tdmb_din2";
1010						function = "tdmb";
1011					};
1012				};
1013
1014				tdmb_dout2_pins: tdmb_dout2 {
1015					mux {
1016						groups = "tdmb_dout2";
1017						function = "tdmb";
1018					};
1019				};
1020
1021				tdmb_din3_pins: tdmb_din3 {
1022					mux {
1023						groups = "tdmb_din3";
1024						function = "tdmb";
1025					};
1026				};
1027
1028				tdmb_dout3_pins: tdmb_dout3 {
1029					mux {
1030						groups = "tdmb_dout3";
1031						function = "tdmb";
1032					};
1033				};
1034
1035				tdmc_sclk_pins: tdmc_sclk {
1036					mux {
1037						groups = "tdmc_sclk";
1038						function = "tdmc";
1039					};
1040				};
1041
1042				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1043					mux {
1044						groups = "tdmc_sclk_slv";
1045						function = "tdmc";
1046					};
1047				};
1048
1049				tdmc_fs_pins: tdmc_fs {
1050					mux {
1051						groups = "tdmc_fs";
1052						function = "tdmc";
1053					};
1054				};
1055
1056				tdmc_fs_slv_pins: tdmc_fs_slv {
1057					mux {
1058						groups = "tdmc_fs_slv";
1059						function = "tdmc";
1060					};
1061				};
1062
1063				tdmc_din0_pins: tdmc_din0 {
1064					mux {
1065						groups = "tdmc_din0";
1066						function = "tdmc";
1067					};
1068				};
1069
1070				tdmc_dout0_pins: tdmc_dout0 {
1071					mux {
1072						groups = "tdmc_dout0";
1073						function = "tdmc";
1074					};
1075				};
1076
1077				tdmc_din1_pins: tdmc_din1 {
1078					mux {
1079						groups = "tdmc_din1";
1080						function = "tdmc";
1081					};
1082				};
1083
1084				tdmc_dout1_pins: tdmc_dout1 {
1085					mux {
1086						groups = "tdmc_dout1";
1087						function = "tdmc";
1088					};
1089				};
1090
1091				tdmc_din2_pins: tdmc_din2 {
1092					mux {
1093						groups = "tdmc_din2";
1094						function = "tdmc";
1095					};
1096				};
1097
1098				tdmc_dout2_pins: tdmc_dout2 {
1099					mux {
1100						groups = "tdmc_dout2";
1101						function = "tdmc";
1102					};
1103				};
1104
1105				tdmc_din3_pins: tdmc_din3 {
1106					mux {
1107						groups = "tdmc_din3";
1108						function = "tdmc";
1109					};
1110				};
1111
1112				tdmc_dout3_pins: tdmc_dout3 {
1113					mux {
1114						groups = "tdmc_dout3";
1115						function = "tdmc";
1116					};
1117				};
1118			};
1119		};
1120
1121		sram: sram@fffc0000 {
1122			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1123			reg = <0x0 0xfffc0000 0x0 0x20000>;
1124			#address-cells = <1>;
1125			#size-cells = <1>;
1126			ranges = <0 0x0 0xfffc0000 0x20000>;
1127
1128			cpu_scp_lpri: scp-shmem@0 {
1129				compatible = "amlogic,meson-axg-scp-shmem";
1130				reg = <0x13000 0x400>;
1131			};
1132
1133			cpu_scp_hpri: scp-shmem@200 {
1134				compatible = "amlogic,meson-axg-scp-shmem";
1135				reg = <0x13400 0x400>;
1136			};
1137		};
1138
1139		aobus: bus@ff800000 {
1140			compatible = "simple-bus";
1141			reg = <0x0 0xff800000 0x0 0x100000>;
1142			#address-cells = <2>;
1143			#size-cells = <2>;
1144			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1145
1146			sysctrl_AO: sys-ctrl@0 {
1147				compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1148				reg =  <0x0 0x0 0x0 0x100>;
1149
1150				clkc_AO: clock-controller {
1151					compatible = "amlogic,meson-axg-aoclkc";
1152					#clock-cells = <1>;
1153					#reset-cells = <1>;
1154				};
1155			};
1156
1157			pinctrl_aobus: pinctrl@14 {
1158				compatible = "amlogic,meson-axg-aobus-pinctrl";
1159				#address-cells = <2>;
1160				#size-cells = <2>;
1161				ranges;
1162
1163				gpio_ao: bank@14 {
1164					reg = <0x0 0x00014 0x0 0x8>,
1165						<0x0 0x0002c 0x0 0x4>,
1166						<0x0 0x00024 0x0 0x8>;
1167					reg-names = "mux", "pull", "gpio";
1168					gpio-controller;
1169					#gpio-cells = <2>;
1170					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1171				};
1172
1173				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1174					mux {
1175						groups = "i2c_ao_sck_4";
1176						function = "i2c_ao";
1177					};
1178				};
1179
1180				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1181					mux {
1182						groups = "i2c_ao_sck_8";
1183						function = "i2c_ao";
1184					};
1185				};
1186
1187				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1188					mux {
1189						groups = "i2c_ao_sck_10";
1190						function = "i2c_ao";
1191					};
1192				};
1193
1194				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1195					mux {
1196						groups = "i2c_ao_sda_5";
1197						function = "i2c_ao";
1198					};
1199				};
1200
1201				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1202					mux {
1203						groups = "i2c_ao_sda_9";
1204						function = "i2c_ao";
1205					};
1206				};
1207
1208				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1209					mux {
1210						groups = "i2c_ao_sda_11";
1211						function = "i2c_ao";
1212					};
1213				};
1214
1215				remote_input_ao_pins: remote_input_ao {
1216					mux {
1217						groups = "remote_input_ao";
1218						function = "remote_input_ao";
1219					};
1220				};
1221
1222				uart_ao_a_pins: uart_ao_a {
1223					mux {
1224						groups = "uart_ao_tx_a",
1225							"uart_ao_rx_a";
1226						function = "uart_ao_a";
1227					};
1228				};
1229
1230				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1231					mux {
1232						groups = "uart_ao_cts_a",
1233							"uart_ao_rts_a";
1234						function = "uart_ao_a";
1235					};
1236				};
1237
1238				uart_ao_b_pins: uart_ao_b {
1239					mux {
1240						groups = "uart_ao_tx_b",
1241							"uart_ao_rx_b";
1242						function = "uart_ao_b";
1243					};
1244				};
1245
1246				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1247					mux {
1248						groups = "uart_ao_cts_b",
1249							"uart_ao_rts_b";
1250						function = "uart_ao_b";
1251					};
1252				};
1253			};
1254
1255			sec_AO: ao-secure@140 {
1256				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1257				reg = <0x0 0x140 0x0 0x140>;
1258				amlogic,has-chip-id;
1259			};
1260
1261			pwm_AO_ab: pwm@7000 {
1262				compatible = "amlogic,meson-axg-ao-pwm";
1263				reg = <0x0 0x07000 0x0 0x20>;
1264				#pwm-cells = <3>;
1265				status = "disabled";
1266			};
1267
1268			pwm_AO_cd: pwm@2000 {
1269				compatible = "amlogic,meson-axg-ao-pwm";
1270				reg = <0x0 0x02000  0x0 0x20>;
1271				#pwm-cells = <3>;
1272				status = "disabled";
1273			};
1274
1275			i2c_AO: i2c@5000 {
1276				compatible = "amlogic,meson-axg-i2c";
1277				reg = <0x0 0x05000 0x0 0x20>;
1278				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1279				clocks = <&clkc CLKID_AO_I2C>;
1280				#address-cells = <1>;
1281				#size-cells = <0>;
1282				status = "disabled";
1283			};
1284
1285			uart_AO: serial@3000 {
1286				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1287				reg = <0x0 0x3000 0x0 0x18>;
1288				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1289				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1290				clock-names = "xtal", "pclk", "baud";
1291				status = "disabled";
1292			};
1293
1294			uart_AO_B: serial@4000 {
1295				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1296				reg = <0x0 0x4000 0x0 0x18>;
1297				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1298				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1299				clock-names = "xtal", "pclk", "baud";
1300				status = "disabled";
1301			};
1302
1303			ir: ir@8000 {
1304				compatible = "amlogic,meson-gxbb-ir";
1305				reg = <0x0 0x8000 0x0 0x20>;
1306				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1307				status = "disabled";
1308			};
1309
1310			saradc: adc@9000 {
1311				compatible = "amlogic,meson-axg-saradc",
1312					"amlogic,meson-saradc";
1313				reg = <0x0 0x9000 0x0 0x38>;
1314				#io-channel-cells = <1>;
1315				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1316				clocks = <&xtal>,
1317					<&clkc_AO CLKID_AO_SAR_ADC>,
1318					<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1319					<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1320				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1321				status = "disabled";
1322			};
1323		};
1324	};
1325};
1326