1/* 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/axg-clkc.h> 11 12/ { 13 compatible = "amlogic,meson-axg"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 /* 16 MiB reserved for Hardware ROM Firmware */ 25 hwrom_reserved: hwrom@0 { 26 reg = <0x0 0x0 0x0 0x1000000>; 27 no-map; 28 }; 29 30 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 31 secmon_reserved: secmon@5000000 { 32 reg = <0x0 0x05000000 0x0 0x300000>; 33 no-map; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <0x2>; 39 #size-cells = <0x0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0x0 0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x2>; 61 enable-method = "psci"; 62 next-level-cache = <&l2>; 63 }; 64 65 cpu3: cpu@3 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0x0 0x3>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 }; 72 73 l2: l2-cache0 { 74 compatible = "cache"; 75 }; 76 }; 77 78 arm-pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 102 }; 103 104 xtal: xtal-clk { 105 compatible = "fixed-clock"; 106 clock-frequency = <24000000>; 107 clock-output-names = "xtal"; 108 #clock-cells = <0>; 109 }; 110 111 soc { 112 compatible = "simple-bus"; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 cbus: bus@ffd00000 { 118 compatible = "simple-bus"; 119 reg = <0x0 0xffd00000 0x0 0x25000>; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 123 124 pwm_ab: pwm@1b000 { 125 compatible = "amlogic,meson-axg-ee-pwm"; 126 reg = <0x0 0x1b000 0x0 0x20>; 127 #pwm-cells = <3>; 128 status = "disabled"; 129 }; 130 131 pwm_cd: pwm@1a000 { 132 compatible = "amlogic,meson-axg-ee-pwm"; 133 reg = <0x0 0x1a000 0x0 0x20>; 134 #pwm-cells = <3>; 135 status = "disabled"; 136 }; 137 138 reset: reset-controller@1004 { 139 compatible = "amlogic,meson-axg-reset"; 140 reg = <0x0 0x01004 0x0 0x9c>; 141 #reset-cells = <1>; 142 }; 143 144 uart_A: serial@24000 { 145 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 146 reg = <0x0 0x24000 0x0 0x14>; 147 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 148 status = "disabled"; 149 }; 150 151 uart_B: serial@23000 { 152 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 153 reg = <0x0 0x23000 0x0 0x14>; 154 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 155 status = "disabled"; 156 }; 157 }; 158 159 gic: interrupt-controller@ffc01000 { 160 compatible = "arm,gic-400"; 161 reg = <0x0 0xffc01000 0 0x1000>, 162 <0x0 0xffc02000 0 0x2000>, 163 <0x0 0xffc04000 0 0x2000>, 164 <0x0 0xffc06000 0 0x2000>; 165 interrupt-controller; 166 interrupts = <GIC_PPI 9 167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 168 #interrupt-cells = <3>; 169 #address-cells = <0>; 170 }; 171 172 hiubus: bus@ff63c000 { 173 compatible = "simple-bus"; 174 reg = <0x0 0xff63c000 0x0 0x1c00>; 175 #address-cells = <2>; 176 #size-cells = <2>; 177 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 178 179 clkc: clock-controller@0 { 180 compatible = "amlogic,axg-clkc"; 181 #clock-cells = <1>; 182 reg = <0x0 0x0 0x0 0x320>; 183 }; 184 }; 185 186 mailbox: mailbox@ff63dc00 { 187 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 188 reg = <0 0xff63dc00 0 0x400>; 189 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 192 #mbox-cells = <1>; 193 }; 194 195 periphs: periphs@ff634000 { 196 compatible = "simple-bus"; 197 reg = <0x0 0xff634000 0x0 0x2000>; 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 201 202 pinctrl_periphs: pinctrl@480 { 203 compatible = "amlogic,meson-axg-periphs-pinctrl"; 204 #address-cells = <2>; 205 #size-cells = <2>; 206 ranges; 207 208 gpio: bank@480 { 209 reg = <0x0 0x00480 0x0 0x40>, 210 <0x0 0x004e8 0x0 0x14>, 211 <0x0 0x00520 0x0 0x14>, 212 <0x0 0x00430 0x0 0x3c>; 213 reg-names = "mux", "pull", "pull-enable", "gpio"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 gpio-ranges = <&pinctrl_periphs 0 0 86>; 217 }; 218 219 pwm_a_a_pins: pwm_a_a { 220 mux { 221 groups = "pwm_a_a"; 222 function = "pwm_a"; 223 }; 224 }; 225 226 pwm_a_x18_pins: pwm_a_x18 { 227 mux { 228 groups = "pwm_a_x18"; 229 function = "pwm_a"; 230 }; 231 }; 232 233 pwm_a_x20_pins: pwm_a_x20 { 234 mux { 235 groups = "pwm_a_x20"; 236 function = "pwm_a"; 237 }; 238 }; 239 240 pwm_a_z_pins: pwm_a_z { 241 mux { 242 groups = "pwm_a_z"; 243 function = "pwm_a"; 244 }; 245 }; 246 247 pwm_b_a_pins: pwm_b_a { 248 mux { 249 groups = "pwm_b_a"; 250 function = "pwm_b"; 251 }; 252 }; 253 254 pwm_b_x_pins: pwm_b_x { 255 mux { 256 groups = "pwm_b_x"; 257 function = "pwm_b"; 258 }; 259 }; 260 261 pwm_b_z_pins: pwm_b_z { 262 mux { 263 groups = "pwm_b_z"; 264 function = "pwm_b"; 265 }; 266 }; 267 268 pwm_c_a_pins: pwm_c_a { 269 mux { 270 groups = "pwm_c_a"; 271 function = "pwm_c"; 272 }; 273 }; 274 275 pwm_c_x10_pins: pwm_c_x10 { 276 mux { 277 groups = "pwm_c_x10"; 278 function = "pwm_c"; 279 }; 280 }; 281 282 pwm_c_x17_pins: pwm_c_x17 { 283 mux { 284 groups = "pwm_c_x17"; 285 function = "pwm_c"; 286 }; 287 }; 288 289 pwm_d_x11_pins: pwm_d_x11 { 290 mux { 291 groups = "pwm_d_x11"; 292 function = "pwm_d"; 293 }; 294 }; 295 296 pwm_d_x16_pins: pwm_d_x16 { 297 mux { 298 groups = "pwm_d_x16"; 299 function = "pwm_d"; 300 }; 301 }; 302 }; 303 }; 304 305 sram: sram@fffc0000 { 306 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 307 reg = <0x0 0xfffc0000 0x0 0x20000>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0x0 0xfffc0000 0x20000>; 311 312 cpu_scp_lpri: scp-shmem@0 { 313 compatible = "amlogic,meson-axg-scp-shmem"; 314 reg = <0x13000 0x400>; 315 }; 316 317 cpu_scp_hpri: scp-shmem@200 { 318 compatible = "amlogic,meson-axg-scp-shmem"; 319 reg = <0x13400 0x400>; 320 }; 321 }; 322 323 aobus: bus@ff800000 { 324 compatible = "simple-bus"; 325 reg = <0x0 0xff800000 0x0 0x100000>; 326 #address-cells = <2>; 327 #size-cells = <2>; 328 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 329 330 pinctrl_aobus: pinctrl@14 { 331 compatible = "amlogic,meson-axg-aobus-pinctrl"; 332 #address-cells = <2>; 333 #size-cells = <2>; 334 ranges; 335 336 gpio_ao: bank@14 { 337 reg = <0x0 0x00014 0x0 0x8>, 338 <0x0 0x0002c 0x0 0x4>, 339 <0x0 0x00024 0x0 0x8>; 340 reg-names = "mux", "pull", "gpio"; 341 gpio-controller; 342 #gpio-cells = <2>; 343 gpio-ranges = <&pinctrl_aobus 0 0 15>; 344 }; 345 346 remote_input_ao_pins: remote_input_ao { 347 mux { 348 groups = "remote_input_ao"; 349 function = "remote_input_ao"; 350 }; 351 }; 352 }; 353 354 pwm_AO_ab: pwm@7000 { 355 compatible = "amlogic,meson-axg-ao-pwm"; 356 reg = <0x0 0x07000 0x0 0x20>; 357 #pwm-cells = <3>; 358 status = "disabled"; 359 }; 360 361 pwm_AO_cd: pwm@2000 { 362 compatible = "amlogic,axg-ao-pwm"; 363 reg = <0x0 0x02000 0x0 0x20>; 364 #pwm-cells = <3>; 365 status = "disabled"; 366 }; 367 368 uart_AO: serial@3000 { 369 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 370 reg = <0x0 0x3000 0x0 0x18>; 371 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 372 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 373 clock-names = "xtal", "pclk", "baud"; 374 status = "disabled"; 375 }; 376 377 uart_AO_B: serial@4000 { 378 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 379 reg = <0x0 0x4000 0x0 0x18>; 380 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 381 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 382 clock-names = "xtal", "pclk", "baud"; 383 status = "disabled"; 384 }; 385 386 ir: ir@8000 { 387 compatible = "amlogic,meson-gxbb-ir"; 388 reg = <0x0 0x8000 0x0 0x20>; 389 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 390 status = "disabled"; 391 }; 392 }; 393 }; 394}; 395