1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		cbus: bus@ffd00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffd00000 0x0 0x25000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
123
124			pwm_ab: pwm@1b000 {
125				compatible = "amlogic,meson-axg-ee-pwm";
126				reg = <0x0 0x1b000 0x0 0x20>;
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			pwm_cd: pwm@1a000 {
132				compatible = "amlogic,meson-axg-ee-pwm";
133				reg = <0x0 0x1a000 0x0 0x20>;
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			reset: reset-controller@1004 {
139				compatible = "amlogic,meson-axg-reset";
140				reg = <0x0 0x01004 0x0 0x9c>;
141				#reset-cells = <1>;
142			};
143
144			spicc0: spi@13000 {
145				compatible = "amlogic,meson-axg-spicc";
146				reg = <0x0 0x13000 0x0 0x3c>;
147				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clkc CLKID_SPICC0>;
149				clock-names = "core";
150				#address-cells = <1>;
151				#size-cells = <0>;
152				status = "disabled";
153			};
154
155			spicc1: spi@15000 {
156				compatible = "amlogic,meson-axg-spicc";
157				reg = <0x0 0x15000 0x0 0x3c>;
158				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159				clocks = <&clkc CLKID_SPICC1>;
160				clock-names = "core";
161				#address-cells = <1>;
162				#size-cells = <0>;
163				status = "disabled";
164			};
165
166			i2c0: i2c@1f000 {
167				compatible = "amlogic,meson-axg-i2c";
168				status = "disabled";
169				reg = <0x0 0x1f000 0x0 0x20>;
170				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
171					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
172				#address-cells = <1>;
173				#size-cells = <0>;
174				clocks = <&clkc CLKID_I2C>;
175				clock-names = "clk_i2c";
176			};
177
178			i2c1: i2c@1e000 {
179				compatible = "amlogic,meson-axg-i2c";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				reg = <0x0 0x1e000 0x0 0x20>;
183				status = "disabled";
184				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
185					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
186				clocks = <&clkc CLKID_I2C>;
187				clock-names = "clk_i2c";
188			};
189
190			i2c2: i2c@1d000 {
191				compatible = "amlogic,meson-axg-i2c";
192				status = "disabled";
193				reg = <0x0 0x1d000 0x0 0x20>;
194				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
195					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
196				#address-cells = <1>;
197				#size-cells = <0>;
198				clocks = <&clkc CLKID_I2C>;
199				clock-names = "clk_i2c";
200			};
201
202			i2c3: i2c@1c000 {
203				compatible = "amlogic,meson-axg-i2c";
204				status = "disabled";
205				reg = <0x0 0x1c000 0x0 0x20>;
206				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
207					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
208				#address-cells = <1>;
209				#size-cells = <0>;
210				clocks = <&clkc CLKID_I2C>;
211				clock-names = "clk_i2c";
212			};
213
214			uart_A: serial@24000 {
215				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
216				reg = <0x0 0x24000 0x0 0x18>;
217				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
218				status = "disabled";
219			};
220
221			uart_B: serial@23000 {
222				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
223				reg = <0x0 0x23000 0x0 0x18>;
224				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
225				status = "disabled";
226			};
227		};
228
229		ethmac: ethernet@ff3f0000 {
230			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
231			reg = <0x0 0xff3f0000 0x0 0x10000
232				0x0 0xff634540 0x0 0x8>;
233			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
234			interrupt-names = "macirq";
235			clocks = <&clkc CLKID_ETH>,
236				 <&clkc CLKID_FCLK_DIV2>,
237				 <&clkc CLKID_MPLL2>;
238			clock-names = "stmmaceth", "clkin0", "clkin1";
239			status = "disabled";
240		};
241
242		gic: interrupt-controller@ffc01000 {
243			compatible = "arm,gic-400";
244			reg = <0x0 0xffc01000 0 0x1000>,
245			      <0x0 0xffc02000 0 0x2000>,
246			      <0x0 0xffc04000 0 0x2000>,
247			      <0x0 0xffc06000 0 0x2000>;
248			interrupt-controller;
249			interrupts = <GIC_PPI 9
250				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
251			#interrupt-cells = <3>;
252			#address-cells = <0>;
253		};
254
255		hiubus: bus@ff63c000 {
256			compatible = "simple-bus";
257			reg = <0x0 0xff63c000 0x0 0x1c00>;
258			#address-cells = <2>;
259			#size-cells = <2>;
260			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
261
262			clkc: clock-controller@0 {
263				compatible = "amlogic,axg-clkc";
264				#clock-cells = <1>;
265				reg = <0x0 0x0 0x0 0x320>;
266			};
267		};
268
269		mailbox: mailbox@ff63dc00 {
270			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
271			reg = <0 0xff63dc00 0 0x400>;
272			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
273				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
274				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
275			#mbox-cells = <1>;
276		};
277
278		periphs: periphs@ff634000 {
279			compatible = "simple-bus";
280			reg = <0x0 0xff634000 0x0 0x2000>;
281			#address-cells = <2>;
282			#size-cells = <2>;
283			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
284
285			hwrng: rng {
286				compatible = "amlogic,meson-rng";
287				reg = <0x0 0x18 0x0 0x4>;
288				clocks = <&clkc CLKID_RNG0>;
289				clock-names = "core";
290			};
291
292			pinctrl_periphs: pinctrl@480 {
293				compatible = "amlogic,meson-axg-periphs-pinctrl";
294				#address-cells = <2>;
295				#size-cells = <2>;
296				ranges;
297
298				gpio: bank@480 {
299					reg = <0x0 0x00480 0x0 0x40>,
300						<0x0 0x004e8 0x0 0x14>,
301						<0x0 0x00520 0x0 0x14>,
302						<0x0 0x00430 0x0 0x3c>;
303					reg-names = "mux", "pull", "pull-enable", "gpio";
304					gpio-controller;
305					#gpio-cells = <2>;
306					gpio-ranges = <&pinctrl_periphs 0 0 86>;
307				};
308
309				eth_rmii_x_pins: eth-x-rmii {
310					mux {
311						groups = "eth_mdio_x",
312						       "eth_mdc_x",
313						       "eth_rgmii_rx_clk_x",
314						       "eth_rx_dv_x",
315						       "eth_rxd0_x",
316						       "eth_rxd1_x",
317						       "eth_txen_x",
318						       "eth_txd0_x",
319						       "eth_txd1_x";
320						function = "eth";
321					};
322				};
323
324				eth_rmii_y_pins: eth-y-rmii {
325					mux {
326						groups = "eth_mdio_y",
327						       "eth_mdc_y",
328						       "eth_rgmii_rx_clk_y",
329						       "eth_rx_dv_y",
330						       "eth_rxd0_y",
331						       "eth_rxd1_y",
332						       "eth_txen_y",
333						       "eth_txd0_y",
334						       "eth_txd1_y";
335						function = "eth";
336					};
337				};
338
339				eth_rgmii_x_pins: eth-x-rgmii {
340					mux {
341						groups = "eth_mdio_x",
342						       "eth_mdc_x",
343						       "eth_rgmii_rx_clk_x",
344						       "eth_rx_dv_x",
345						       "eth_rxd0_x",
346						       "eth_rxd1_x",
347						       "eth_rxd2_rgmii",
348						       "eth_rxd3_rgmii",
349						       "eth_rgmii_tx_clk",
350						       "eth_txen_x",
351						       "eth_txd0_x",
352						       "eth_txd1_x",
353						       "eth_txd2_rgmii",
354						       "eth_txd3_rgmii";
355						function = "eth";
356					};
357				};
358
359				eth_rgmii_y_pins: eth-y-rgmii {
360					mux {
361						groups = "eth_mdio_y",
362						       "eth_mdc_y",
363						       "eth_rgmii_rx_clk_y",
364						       "eth_rx_dv_y",
365						       "eth_rxd0_y",
366						       "eth_rxd1_y",
367						       "eth_rxd2_rgmii",
368						       "eth_rxd3_rgmii",
369						       "eth_rgmii_tx_clk",
370						       "eth_txen_y",
371						       "eth_txd0_y",
372						       "eth_txd1_y",
373						       "eth_txd2_rgmii",
374						       "eth_txd3_rgmii";
375						function = "eth";
376					};
377				};
378
379				pwm_a_a_pins: pwm_a_a {
380					mux {
381						groups = "pwm_a_a";
382						function = "pwm_a";
383					};
384				};
385
386				pwm_a_x18_pins: pwm_a_x18 {
387					mux {
388						groups = "pwm_a_x18";
389						function = "pwm_a";
390					};
391				};
392
393				pwm_a_x20_pins: pwm_a_x20 {
394					mux {
395						groups = "pwm_a_x20";
396						function = "pwm_a";
397					};
398				};
399
400				pwm_a_z_pins: pwm_a_z {
401					mux {
402						groups = "pwm_a_z";
403						function = "pwm_a";
404					};
405				};
406
407				pwm_b_a_pins: pwm_b_a {
408					mux {
409						groups = "pwm_b_a";
410						function = "pwm_b";
411					};
412				};
413
414				pwm_b_x_pins: pwm_b_x {
415					mux {
416						groups = "pwm_b_x";
417						function = "pwm_b";
418					};
419				};
420
421				pwm_b_z_pins: pwm_b_z {
422					mux {
423						groups = "pwm_b_z";
424						function = "pwm_b";
425					};
426				};
427
428				pwm_c_a_pins: pwm_c_a {
429					mux {
430						groups = "pwm_c_a";
431						function = "pwm_c";
432					};
433				};
434
435				pwm_c_x10_pins: pwm_c_x10 {
436					mux {
437						groups = "pwm_c_x10";
438						function = "pwm_c";
439					};
440				};
441
442				pwm_c_x17_pins: pwm_c_x17 {
443					mux {
444						groups = "pwm_c_x17";
445						function = "pwm_c";
446					};
447				};
448
449				pwm_d_x11_pins: pwm_d_x11 {
450					mux {
451						groups = "pwm_d_x11";
452						function = "pwm_d";
453					};
454				};
455
456				pwm_d_x16_pins: pwm_d_x16 {
457					mux {
458						groups = "pwm_d_x16";
459						function = "pwm_d";
460					};
461				};
462
463				spi0_pins: spi0 {
464					mux {
465						groups = "spi0_miso",
466							"spi0_mosi",
467							"spi0_clk";
468						function = "spi0";
469					};
470				};
471
472				spi0_ss0_pins: spi0_ss0 {
473					mux {
474						groups = "spi0_ss0";
475						function = "spi0";
476					};
477				};
478
479				spi0_ss1_pins: spi0_ss1 {
480					mux {
481						groups = "spi0_ss1";
482						function = "spi0";
483					};
484				};
485
486				spi0_ss2_pins: spi0_ss2 {
487					mux {
488						groups = "spi0_ss2";
489						function = "spi0";
490					};
491				};
492
493
494				spi1_a_pins: spi1_a {
495					mux {
496						groups = "spi1_miso_a",
497							"spi1_mosi_a",
498							"spi1_clk_a";
499						function = "spi1";
500					};
501				};
502
503				spi1_ss0_a_pins: spi1_ss0_a {
504					mux {
505						groups = "spi1_ss0_a";
506						function = "spi1";
507					};
508				};
509
510				spi1_ss1_pins: spi1_ss1 {
511					mux {
512						groups = "spi1_ss1";
513						function = "spi1";
514					};
515				};
516
517				spi1_x_pins: spi1_x {
518					mux {
519						groups = "spi1_miso_x",
520							"spi1_mosi_x",
521							"spi1_clk_x";
522						function = "spi1";
523					};
524				};
525
526				spi1_ss0_x_pins: spi1_ss0_x {
527					mux {
528						groups = "spi1_ss0_x";
529						function = "spi1";
530					};
531				};
532
533				i2c0_pins: i2c0 {
534					mux {
535						groups = "i2c0_sck",
536							"i2c0_sda";
537						function = "i2c0";
538					};
539				};
540
541				i2c1_z_pins: i2c1_z {
542					mux {
543						groups = "i2c1_sck_z",
544							"i2c1_sda_z";
545						function = "i2c1";
546					};
547				};
548
549				i2c1_x_pins: i2c1_x {
550					mux {
551						groups = "i2c1_sck_x",
552							"i2c1_sda_x";
553						function = "i2c1";
554					};
555				};
556
557				i2c2_x_pins: i2c2_x {
558					mux {
559						groups = "i2c2_sck_x",
560							"i2c2_sda_x";
561						function = "i2c2";
562					};
563				};
564
565				i2c2_a_pins: i2c2_a {
566					mux {
567						groups = "i2c2_sck_a",
568							"i2c2_sda_a";
569						function = "i2c2";
570					};
571				};
572
573				i2c3_a6_pins: i2c3_a6 {
574					mux {
575						groups = "i2c3_sda_a6",
576							"i2c3_sck_a7";
577						function = "i2c3";
578					};
579				};
580
581				i2c3_a12_pins: i2c3_a12 {
582					mux {
583						groups = "i2c3_sda_a12",
584							"i2c3_sck_a13";
585						function = "i2c3";
586					};
587				};
588
589				i2c3_a19_pins: i2c3_a19 {
590					mux {
591						groups = "i2c3_sda_a19",
592							"i2c3_sck_a20";
593						function = "i2c3";
594					};
595				};
596			};
597		};
598
599		sram: sram@fffc0000 {
600			compatible = "amlogic,meson-axg-sram", "mmio-sram";
601			reg = <0x0 0xfffc0000 0x0 0x20000>;
602			#address-cells = <1>;
603			#size-cells = <1>;
604			ranges = <0 0x0 0xfffc0000 0x20000>;
605
606			cpu_scp_lpri: scp-shmem@0 {
607				compatible = "amlogic,meson-axg-scp-shmem";
608				reg = <0x13000 0x400>;
609			};
610
611			cpu_scp_hpri: scp-shmem@200 {
612				compatible = "amlogic,meson-axg-scp-shmem";
613				reg = <0x13400 0x400>;
614			};
615		};
616
617		aobus: bus@ff800000 {
618			compatible = "simple-bus";
619			reg = <0x0 0xff800000 0x0 0x100000>;
620			#address-cells = <2>;
621			#size-cells = <2>;
622			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
623
624			pinctrl_aobus: pinctrl@14 {
625				compatible = "amlogic,meson-axg-aobus-pinctrl";
626				#address-cells = <2>;
627				#size-cells = <2>;
628				ranges;
629
630				gpio_ao: bank@14 {
631					reg = <0x0 0x00014 0x0 0x8>,
632						<0x0 0x0002c 0x0 0x4>,
633						<0x0 0x00024 0x0 0x8>;
634					reg-names = "mux", "pull", "gpio";
635					gpio-controller;
636					#gpio-cells = <2>;
637					gpio-ranges = <&pinctrl_aobus 0 0 15>;
638				};
639
640				remote_input_ao_pins: remote_input_ao {
641					mux {
642						groups = "remote_input_ao";
643						function = "remote_input_ao";
644					};
645				};
646			};
647
648			pwm_AO_ab: pwm@7000 {
649				compatible = "amlogic,meson-axg-ao-pwm";
650				reg = <0x0 0x07000 0x0 0x20>;
651				#pwm-cells = <3>;
652				status = "disabled";
653			};
654
655			pwm_AO_cd: pwm@2000 {
656				compatible = "amlogic,axg-ao-pwm";
657				reg = <0x0 0x02000  0x0 0x20>;
658				#pwm-cells = <3>;
659				status = "disabled";
660			};
661
662			i2c_AO: i2c@5000 {
663				compatible = "amlogic,meson-axg-i2c";
664				status = "disabled";
665				reg = <0x0 0x05000 0x0 0x20>;
666				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
667				#address-cells = <1>;
668				#size-cells = <0>;
669				clocks = <&clkc CLKID_I2C>;
670				clock-names = "clk_i2c";
671			};
672
673			uart_AO: serial@3000 {
674				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
675				reg = <0x0 0x3000 0x0 0x18>;
676				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
677				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
678				clock-names = "xtal", "pclk", "baud";
679				status = "disabled";
680			};
681
682			uart_AO_B: serial@4000 {
683				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
684				reg = <0x0 0x4000 0x0 0x18>;
685				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
686				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
687				clock-names = "xtal", "pclk", "baud";
688				status = "disabled";
689			};
690
691			ir: ir@8000 {
692				compatible = "amlogic,meson-gxbb-ir";
693				reg = <0x0 0x8000 0x0 0x20>;
694				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
695				status = "disabled";
696			};
697		};
698	};
699};
700