1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 ao_alt_xtal: ao_alt_xtal-clk { 57 compatible = "fixed-clock"; 58 clock-frequency = <32000000>; 59 clock-output-names = "ao_alt_xtal"; 60 #clock-cells = <0>; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 clocks = <&scpi_dvfs 0>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 next-level-cache = <&l2>; 91 clocks = <&scpi_dvfs 0>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0x0 0x2>; 98 enable-method = "psci"; 99 next-level-cache = <&l2>; 100 clocks = <&scpi_dvfs 0>; 101 }; 102 103 cpu3: cpu@3 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53", "arm,armv8"; 106 reg = <0x0 0x3>; 107 enable-method = "psci"; 108 next-level-cache = <&l2>; 109 clocks = <&scpi_dvfs 0>; 110 }; 111 112 l2: l2-cache0 { 113 compatible = "cache"; 114 }; 115 }; 116 117 sm: secure-monitor { 118 compatible = "amlogic,meson-gxbb-sm"; 119 }; 120 121 psci { 122 compatible = "arm,psci-1.0"; 123 method = "smc"; 124 }; 125 126 reserved-memory { 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 /* 16 MiB reserved for Hardware ROM Firmware */ 132 hwrom_reserved: hwrom@0 { 133 reg = <0x0 0x0 0x0 0x1000000>; 134 no-map; 135 }; 136 137 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 138 secmon_reserved: secmon@5000000 { 139 reg = <0x0 0x05000000 0x0 0x300000>; 140 no-map; 141 }; 142 }; 143 144 scpi { 145 compatible = "arm,scpi-pre-1.0"; 146 mboxes = <&mailbox 1 &mailbox 2>; 147 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 148 149 scpi_clocks: clocks { 150 compatible = "arm,scpi-clocks"; 151 152 scpi_dvfs: clock-controller { 153 compatible = "arm,scpi-dvfs-clocks"; 154 #clock-cells = <1>; 155 clock-indices = <0>; 156 clock-output-names = "vcpu"; 157 }; 158 }; 159 160 scpi_sensors: sensors { 161 compatible = "amlogic,meson-gxbb-scpi-sensors"; 162 #thermal-sensor-cells = <1>; 163 }; 164 }; 165 166 soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 ethmac: ethernet@ff3f0000 { 173 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 174 reg = <0x0 0xff3f0000 0x0 0x10000 175 0x0 0xff634540 0x0 0x8>; 176 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "macirq"; 178 clocks = <&clkc CLKID_ETH>, 179 <&clkc CLKID_FCLK_DIV2>, 180 <&clkc CLKID_MPLL2>; 181 clock-names = "stmmaceth", "clkin0", "clkin1"; 182 status = "disabled"; 183 }; 184 185 pdm: audio-controller@ff632000 { 186 compatible = "amlogic,axg-pdm"; 187 reg = <0x0 0xff632000 0x0 0x34>; 188 #sound-dai-cells = <0>; 189 sound-name-prefix = "PDM"; 190 clocks = <&clkc_audio AUD_CLKID_PDM>, 191 <&clkc_audio AUD_CLKID_PDM_DCLK>, 192 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 193 clock-names = "pclk", "dclk", "sysclk"; 194 status = "disabled"; 195 }; 196 197 periphs: bus@ff634000 { 198 compatible = "simple-bus"; 199 reg = <0x0 0xff634000 0x0 0x2000>; 200 #address-cells = <2>; 201 #size-cells = <2>; 202 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 203 204 hwrng: rng@18 { 205 compatible = "amlogic,meson-rng"; 206 reg = <0x0 0x18 0x0 0x4>; 207 clocks = <&clkc CLKID_RNG0>; 208 clock-names = "core"; 209 }; 210 211 pinctrl_periphs: pinctrl@480 { 212 compatible = "amlogic,meson-axg-periphs-pinctrl"; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 ranges; 216 217 gpio: bank@480 { 218 reg = <0x0 0x00480 0x0 0x40>, 219 <0x0 0x004e8 0x0 0x14>, 220 <0x0 0x00520 0x0 0x14>, 221 <0x0 0x00430 0x0 0x3c>; 222 reg-names = "mux", "pull", "pull-enable", "gpio"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 gpio-ranges = <&pinctrl_periphs 0 0 86>; 226 }; 227 228 i2c0_pins: i2c0 { 229 mux { 230 groups = "i2c0_sck", 231 "i2c0_sda"; 232 function = "i2c0"; 233 bias-disable; 234 }; 235 }; 236 237 i2c1_x_pins: i2c1_x { 238 mux { 239 groups = "i2c1_sck_x", 240 "i2c1_sda_x"; 241 function = "i2c1"; 242 bias-disable; 243 }; 244 }; 245 246 i2c1_z_pins: i2c1_z { 247 mux { 248 groups = "i2c1_sck_z", 249 "i2c1_sda_z"; 250 function = "i2c1"; 251 bias-disable; 252 }; 253 }; 254 255 i2c2_a_pins: i2c2_a { 256 mux { 257 groups = "i2c2_sck_a", 258 "i2c2_sda_a"; 259 function = "i2c2"; 260 bias-disable; 261 }; 262 }; 263 264 i2c2_x_pins: i2c2_x { 265 mux { 266 groups = "i2c2_sck_x", 267 "i2c2_sda_x"; 268 function = "i2c2"; 269 bias-disable; 270 }; 271 }; 272 273 i2c3_a6_pins: i2c3_a6 { 274 mux { 275 groups = "i2c3_sda_a6", 276 "i2c3_sck_a7"; 277 function = "i2c3"; 278 bias-disable; 279 }; 280 }; 281 282 i2c3_a12_pins: i2c3_a12 { 283 mux { 284 groups = "i2c3_sda_a12", 285 "i2c3_sck_a13"; 286 function = "i2c3"; 287 bias-disable; 288 }; 289 }; 290 291 i2c3_a19_pins: i2c3_a19 { 292 mux { 293 groups = "i2c3_sda_a19", 294 "i2c3_sck_a20"; 295 function = "i2c3"; 296 bias-disable; 297 }; 298 }; 299 300 emmc_pins: emmc { 301 mux { 302 groups = "emmc_nand_d0", 303 "emmc_nand_d1", 304 "emmc_nand_d2", 305 "emmc_nand_d3", 306 "emmc_nand_d4", 307 "emmc_nand_d5", 308 "emmc_nand_d6", 309 "emmc_nand_d7", 310 "emmc_clk", 311 "emmc_cmd", 312 "emmc_ds"; 313 function = "emmc"; 314 bias-disable; 315 }; 316 }; 317 318 emmc_clk_gate_pins: emmc_clk_gate { 319 mux { 320 groups = "BOOT_8"; 321 function = "gpio_periphs"; 322 bias-pull-down; 323 }; 324 }; 325 326 eth_rgmii_x_pins: eth-x-rgmii { 327 mux { 328 groups = "eth_mdio_x", 329 "eth_mdc_x", 330 "eth_rgmii_rx_clk_x", 331 "eth_rx_dv_x", 332 "eth_rxd0_x", 333 "eth_rxd1_x", 334 "eth_rxd2_rgmii", 335 "eth_rxd3_rgmii", 336 "eth_rgmii_tx_clk", 337 "eth_txen_x", 338 "eth_txd0_x", 339 "eth_txd1_x", 340 "eth_txd2_rgmii", 341 "eth_txd3_rgmii"; 342 function = "eth"; 343 bias-disable; 344 }; 345 }; 346 347 eth_rgmii_y_pins: eth-y-rgmii { 348 mux { 349 groups = "eth_mdio_y", 350 "eth_mdc_y", 351 "eth_rgmii_rx_clk_y", 352 "eth_rx_dv_y", 353 "eth_rxd0_y", 354 "eth_rxd1_y", 355 "eth_rxd2_rgmii", 356 "eth_rxd3_rgmii", 357 "eth_rgmii_tx_clk", 358 "eth_txen_y", 359 "eth_txd0_y", 360 "eth_txd1_y", 361 "eth_txd2_rgmii", 362 "eth_txd3_rgmii"; 363 function = "eth"; 364 bias-disable; 365 }; 366 }; 367 368 eth_rmii_x_pins: eth-x-rmii { 369 mux { 370 groups = "eth_mdio_x", 371 "eth_mdc_x", 372 "eth_rgmii_rx_clk_x", 373 "eth_rx_dv_x", 374 "eth_rxd0_x", 375 "eth_rxd1_x", 376 "eth_txen_x", 377 "eth_txd0_x", 378 "eth_txd1_x"; 379 function = "eth"; 380 bias-disable; 381 }; 382 }; 383 384 eth_rmii_y_pins: eth-y-rmii { 385 mux { 386 groups = "eth_mdio_y", 387 "eth_mdc_y", 388 "eth_rgmii_rx_clk_y", 389 "eth_rx_dv_y", 390 "eth_rxd0_y", 391 "eth_rxd1_y", 392 "eth_txen_y", 393 "eth_txd0_y", 394 "eth_txd1_y"; 395 function = "eth"; 396 bias-disable; 397 }; 398 }; 399 400 mclk_b_pins: mclk_b { 401 mux { 402 groups = "mclk_b"; 403 function = "mclk_b"; 404 bias-disable; 405 }; 406 }; 407 408 mclk_c_pins: mclk_c { 409 mux { 410 groups = "mclk_c"; 411 function = "mclk_c"; 412 bias-disable; 413 }; 414 }; 415 416 pdm_dclk_a14_pins: pdm_dclk_a14 { 417 mux { 418 groups = "pdm_dclk_a14"; 419 function = "pdm"; 420 bias-disable; 421 }; 422 }; 423 424 pdm_dclk_a19_pins: pdm_dclk_a19 { 425 mux { 426 groups = "pdm_dclk_a19"; 427 function = "pdm"; 428 bias-disable; 429 }; 430 }; 431 432 pdm_din0_pins: pdm_din0 { 433 mux { 434 groups = "pdm_din0"; 435 function = "pdm"; 436 bias-disable; 437 }; 438 }; 439 440 pdm_din1_pins: pdm_din1 { 441 mux { 442 groups = "pdm_din1"; 443 function = "pdm"; 444 bias-disable; 445 }; 446 }; 447 448 pdm_din2_pins: pdm_din2 { 449 mux { 450 groups = "pdm_din2"; 451 function = "pdm"; 452 bias-disable; 453 }; 454 }; 455 456 pdm_din3_pins: pdm_din3 { 457 mux { 458 groups = "pdm_din3"; 459 function = "pdm"; 460 bias-disable; 461 }; 462 }; 463 464 pwm_a_a_pins: pwm_a_a { 465 mux { 466 groups = "pwm_a_a"; 467 function = "pwm_a"; 468 bias-disable; 469 }; 470 }; 471 472 pwm_a_x18_pins: pwm_a_x18 { 473 mux { 474 groups = "pwm_a_x18"; 475 function = "pwm_a"; 476 bias-disable; 477 }; 478 }; 479 480 pwm_a_x20_pins: pwm_a_x20 { 481 mux { 482 groups = "pwm_a_x20"; 483 function = "pwm_a"; 484 bias-disable; 485 }; 486 }; 487 488 pwm_a_z_pins: pwm_a_z { 489 mux { 490 groups = "pwm_a_z"; 491 function = "pwm_a"; 492 bias-disable; 493 }; 494 }; 495 496 pwm_b_a_pins: pwm_b_a { 497 mux { 498 groups = "pwm_b_a"; 499 function = "pwm_b"; 500 bias-disable; 501 }; 502 }; 503 504 pwm_b_x_pins: pwm_b_x { 505 mux { 506 groups = "pwm_b_x"; 507 function = "pwm_b"; 508 bias-disable; 509 }; 510 }; 511 512 pwm_b_z_pins: pwm_b_z { 513 mux { 514 groups = "pwm_b_z"; 515 function = "pwm_b"; 516 bias-disable; 517 }; 518 }; 519 520 pwm_c_a_pins: pwm_c_a { 521 mux { 522 groups = "pwm_c_a"; 523 function = "pwm_c"; 524 bias-disable; 525 }; 526 }; 527 528 pwm_c_x10_pins: pwm_c_x10 { 529 mux { 530 groups = "pwm_c_x10"; 531 function = "pwm_c"; 532 bias-disable; 533 }; 534 }; 535 536 pwm_c_x17_pins: pwm_c_x17 { 537 mux { 538 groups = "pwm_c_x17"; 539 function = "pwm_c"; 540 bias-disable; 541 }; 542 }; 543 544 pwm_d_x11_pins: pwm_d_x11 { 545 mux { 546 groups = "pwm_d_x11"; 547 function = "pwm_d"; 548 bias-disable; 549 }; 550 }; 551 552 pwm_d_x16_pins: pwm_d_x16 { 553 mux { 554 groups = "pwm_d_x16"; 555 function = "pwm_d"; 556 bias-disable; 557 }; 558 }; 559 560 sdio_pins: sdio { 561 mux { 562 groups = "sdio_d0", 563 "sdio_d1", 564 "sdio_d2", 565 "sdio_d3", 566 "sdio_cmd", 567 "sdio_clk"; 568 function = "sdio"; 569 bias-disable; 570 }; 571 }; 572 573 sdio_clk_gate_pins: sdio_clk_gate { 574 mux { 575 groups = "GPIOX_4"; 576 function = "gpio_periphs"; 577 bias-pull-down; 578 }; 579 }; 580 581 spdif_in_z_pins: spdif_in_z { 582 mux { 583 groups = "spdif_in_z"; 584 function = "spdif_in"; 585 bias-disable; 586 }; 587 }; 588 589 spdif_in_a1_pins: spdif_in_a1 { 590 mux { 591 groups = "spdif_in_a1"; 592 function = "spdif_in"; 593 bias-disable; 594 }; 595 }; 596 597 spdif_in_a7_pins: spdif_in_a7 { 598 mux { 599 groups = "spdif_in_a7"; 600 function = "spdif_in"; 601 bias-disable; 602 }; 603 }; 604 605 spdif_in_a19_pins: spdif_in_a19 { 606 mux { 607 groups = "spdif_in_a19"; 608 function = "spdif_in"; 609 bias-disable; 610 }; 611 }; 612 613 spdif_in_a20_pins: spdif_in_a20 { 614 mux { 615 groups = "spdif_in_a20"; 616 function = "spdif_in"; 617 bias-disable; 618 }; 619 }; 620 621 spdif_out_a1_pins: spdif_out_a1 { 622 mux { 623 groups = "spdif_out_a1"; 624 function = "spdif_out"; 625 bias-disable; 626 }; 627 }; 628 629 spdif_out_a11_pins: spdif_out_a11 { 630 mux { 631 groups = "spdif_out_a11"; 632 function = "spdif_out"; 633 bias-disable; 634 }; 635 }; 636 637 spdif_out_a19_pins: spdif_out_a19 { 638 mux { 639 groups = "spdif_out_a19"; 640 function = "spdif_out"; 641 bias-disable; 642 }; 643 }; 644 645 spdif_out_a20_pins: spdif_out_a20 { 646 mux { 647 groups = "spdif_out_a20"; 648 function = "spdif_out"; 649 bias-disable; 650 }; 651 }; 652 653 spdif_out_z_pins: spdif_out_z { 654 mux { 655 groups = "spdif_out_z"; 656 function = "spdif_out"; 657 bias-disable; 658 }; 659 }; 660 661 spi0_pins: spi0 { 662 mux { 663 groups = "spi0_miso", 664 "spi0_mosi", 665 "spi0_clk"; 666 function = "spi0"; 667 bias-disable; 668 }; 669 }; 670 671 spi0_ss0_pins: spi0_ss0 { 672 mux { 673 groups = "spi0_ss0"; 674 function = "spi0"; 675 bias-disable; 676 }; 677 }; 678 679 spi0_ss1_pins: spi0_ss1 { 680 mux { 681 groups = "spi0_ss1"; 682 function = "spi0"; 683 bias-disable; 684 }; 685 }; 686 687 spi0_ss2_pins: spi0_ss2 { 688 mux { 689 groups = "spi0_ss2"; 690 function = "spi0"; 691 bias-disable; 692 }; 693 }; 694 695 spi1_a_pins: spi1_a { 696 mux { 697 groups = "spi1_miso_a", 698 "spi1_mosi_a", 699 "spi1_clk_a"; 700 function = "spi1"; 701 bias-disable; 702 }; 703 }; 704 705 spi1_ss0_a_pins: spi1_ss0_a { 706 mux { 707 groups = "spi1_ss0_a"; 708 function = "spi1"; 709 bias-disable; 710 }; 711 }; 712 713 spi1_ss1_pins: spi1_ss1 { 714 mux { 715 groups = "spi1_ss1"; 716 function = "spi1"; 717 bias-disable; 718 }; 719 }; 720 721 spi1_x_pins: spi1_x { 722 mux { 723 groups = "spi1_miso_x", 724 "spi1_mosi_x", 725 "spi1_clk_x"; 726 function = "spi1"; 727 bias-disable; 728 }; 729 }; 730 731 spi1_ss0_x_pins: spi1_ss0_x { 732 mux { 733 groups = "spi1_ss0_x"; 734 function = "spi1"; 735 bias-disable; 736 }; 737 }; 738 739 tdma_din0_pins: tdma_din0 { 740 mux { 741 groups = "tdma_din0"; 742 function = "tdma"; 743 bias-disable; 744 }; 745 }; 746 747 tdma_dout0_x14_pins: tdma_dout0_x14 { 748 mux { 749 groups = "tdma_dout0_x14"; 750 function = "tdma"; 751 bias-disable; 752 }; 753 }; 754 755 tdma_dout0_x15_pins: tdma_dout0_x15 { 756 mux { 757 groups = "tdma_dout0_x15"; 758 function = "tdma"; 759 bias-disable; 760 }; 761 }; 762 763 tdma_dout1_pins: tdma_dout1 { 764 mux { 765 groups = "tdma_dout1"; 766 function = "tdma"; 767 bias-disable; 768 }; 769 }; 770 771 tdma_din1_pins: tdma_din1 { 772 mux { 773 groups = "tdma_din1"; 774 function = "tdma"; 775 bias-disable; 776 }; 777 }; 778 779 tdma_fs_pins: tdma_fs { 780 mux { 781 groups = "tdma_fs"; 782 function = "tdma"; 783 bias-disable; 784 }; 785 }; 786 787 tdma_fs_slv_pins: tdma_fs_slv { 788 mux { 789 groups = "tdma_fs_slv"; 790 function = "tdma"; 791 bias-disable; 792 }; 793 }; 794 795 tdma_sclk_pins: tdma_sclk { 796 mux { 797 groups = "tdma_sclk"; 798 function = "tdma"; 799 bias-disable; 800 }; 801 }; 802 803 tdma_sclk_slv_pins: tdma_sclk_slv { 804 mux { 805 groups = "tdma_sclk_slv"; 806 function = "tdma"; 807 bias-disable; 808 }; 809 }; 810 811 tdmb_din0_pins: tdmb_din0 { 812 mux { 813 groups = "tdmb_din0"; 814 function = "tdmb"; 815 bias-disable; 816 }; 817 }; 818 819 tdmb_din1_pins: tdmb_din1 { 820 mux { 821 groups = "tdmb_din1"; 822 function = "tdmb"; 823 bias-disable; 824 }; 825 }; 826 827 tdmb_din2_pins: tdmb_din2 { 828 mux { 829 groups = "tdmb_din2"; 830 function = "tdmb"; 831 bias-disable; 832 }; 833 }; 834 835 tdmb_din3_pins: tdmb_din3 { 836 mux { 837 groups = "tdmb_din3"; 838 function = "tdmb"; 839 bias-disable; 840 }; 841 }; 842 843 tdmb_dout0_pins: tdmb_dout0 { 844 mux { 845 groups = "tdmb_dout0"; 846 function = "tdmb"; 847 bias-disable; 848 }; 849 }; 850 851 tdmb_dout1_pins: tdmb_dout1 { 852 mux { 853 groups = "tdmb_dout1"; 854 function = "tdmb"; 855 bias-disable; 856 }; 857 }; 858 859 tdmb_dout2_pins: tdmb_dout2 { 860 mux { 861 groups = "tdmb_dout2"; 862 function = "tdmb"; 863 bias-disable; 864 }; 865 }; 866 867 tdmb_dout3_pins: tdmb_dout3 { 868 mux { 869 groups = "tdmb_dout3"; 870 function = "tdmb"; 871 bias-disable; 872 }; 873 }; 874 875 tdmb_fs_pins: tdmb_fs { 876 mux { 877 groups = "tdmb_fs"; 878 function = "tdmb"; 879 bias-disable; 880 }; 881 }; 882 883 tdmb_fs_slv_pins: tdmb_fs_slv { 884 mux { 885 groups = "tdmb_fs_slv"; 886 function = "tdmb"; 887 bias-disable; 888 }; 889 }; 890 891 tdmb_sclk_pins: tdmb_sclk { 892 mux { 893 groups = "tdmb_sclk"; 894 function = "tdmb"; 895 bias-disable; 896 }; 897 }; 898 899 tdmb_sclk_slv_pins: tdmb_sclk_slv { 900 mux { 901 groups = "tdmb_sclk_slv"; 902 function = "tdmb"; 903 bias-disable; 904 }; 905 }; 906 907 tdmc_fs_pins: tdmc_fs { 908 mux { 909 groups = "tdmc_fs"; 910 function = "tdmc"; 911 bias-disable; 912 }; 913 }; 914 915 tdmc_fs_slv_pins: tdmc_fs_slv { 916 mux { 917 groups = "tdmc_fs_slv"; 918 function = "tdmc"; 919 bias-disable; 920 }; 921 }; 922 923 tdmc_sclk_pins: tdmc_sclk { 924 mux { 925 groups = "tdmc_sclk"; 926 function = "tdmc"; 927 bias-disable; 928 }; 929 }; 930 931 tdmc_sclk_slv_pins: tdmc_sclk_slv { 932 mux { 933 groups = "tdmc_sclk_slv"; 934 function = "tdmc"; 935 bias-disable; 936 }; 937 }; 938 939 tdmc_din0_pins: tdmc_din0 { 940 mux { 941 groups = "tdmc_din0"; 942 function = "tdmc"; 943 bias-disable; 944 }; 945 }; 946 947 tdmc_din1_pins: tdmc_din1 { 948 mux { 949 groups = "tdmc_din1"; 950 function = "tdmc"; 951 bias-disable; 952 }; 953 }; 954 955 tdmc_din2_pins: tdmc_din2 { 956 mux { 957 groups = "tdmc_din2"; 958 function = "tdmc"; 959 bias-disable; 960 }; 961 }; 962 963 tdmc_din3_pins: tdmc_din3 { 964 mux { 965 groups = "tdmc_din3"; 966 function = "tdmc"; 967 bias-disable; 968 }; 969 }; 970 971 tdmc_dout0_pins: tdmc_dout0 { 972 mux { 973 groups = "tdmc_dout0"; 974 function = "tdmc"; 975 bias-disable; 976 }; 977 }; 978 979 tdmc_dout1_pins: tdmc_dout1 { 980 mux { 981 groups = "tdmc_dout1"; 982 function = "tdmc"; 983 bias-disable; 984 }; 985 }; 986 987 tdmc_dout2_pins: tdmc_dout2 { 988 mux { 989 groups = "tdmc_dout2"; 990 function = "tdmc"; 991 bias-disable; 992 }; 993 }; 994 995 tdmc_dout3_pins: tdmc_dout3 { 996 mux { 997 groups = "tdmc_dout3"; 998 function = "tdmc"; 999 bias-disable; 1000 }; 1001 }; 1002 1003 uart_a_pins: uart_a { 1004 mux { 1005 groups = "uart_tx_a", 1006 "uart_rx_a"; 1007 function = "uart_a"; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 uart_a_cts_rts_pins: uart_a_cts_rts { 1013 mux { 1014 groups = "uart_cts_a", 1015 "uart_rts_a"; 1016 function = "uart_a"; 1017 bias-disable; 1018 }; 1019 }; 1020 1021 uart_b_x_pins: uart_b_x { 1022 mux { 1023 groups = "uart_tx_b_x", 1024 "uart_rx_b_x"; 1025 function = "uart_b"; 1026 bias-disable; 1027 }; 1028 }; 1029 1030 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1031 mux { 1032 groups = "uart_cts_b_x", 1033 "uart_rts_b_x"; 1034 function = "uart_b"; 1035 bias-disable; 1036 }; 1037 }; 1038 1039 uart_b_z_pins: uart_b_z { 1040 mux { 1041 groups = "uart_tx_b_z", 1042 "uart_rx_b_z"; 1043 function = "uart_b"; 1044 bias-disable; 1045 }; 1046 }; 1047 1048 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1049 mux { 1050 groups = "uart_cts_b_z", 1051 "uart_rts_b_z"; 1052 function = "uart_b"; 1053 bias-disable; 1054 }; 1055 }; 1056 1057 uart_ao_b_z_pins: uart_ao_b_z { 1058 mux { 1059 groups = "uart_ao_tx_b_z", 1060 "uart_ao_rx_b_z"; 1061 function = "uart_ao_b_z"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1067 mux { 1068 groups = "uart_ao_cts_b_z", 1069 "uart_ao_rts_b_z"; 1070 function = "uart_ao_b_z"; 1071 bias-disable; 1072 }; 1073 }; 1074 }; 1075 }; 1076 1077 hiubus: bus@ff63c000 { 1078 compatible = "simple-bus"; 1079 reg = <0x0 0xff63c000 0x0 0x1c00>; 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1083 1084 sysctrl: system-controller@0 { 1085 compatible = "amlogic,meson-axg-hhi-sysctrl", 1086 "simple-mfd", "syscon"; 1087 reg = <0 0 0 0x400>; 1088 1089 clkc: clock-controller { 1090 compatible = "amlogic,axg-clkc"; 1091 #clock-cells = <1>; 1092 }; 1093 }; 1094 }; 1095 1096 mailbox: mailbox@ff63c404 { 1097 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1098 reg = <0 0xff63c404 0 0x4c>; 1099 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1100 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1101 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1102 #mbox-cells = <1>; 1103 }; 1104 1105 audio: bus@ff642000 { 1106 compatible = "simple-bus"; 1107 reg = <0x0 0xff642000 0x0 0x2000>; 1108 #address-cells = <2>; 1109 #size-cells = <2>; 1110 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1111 1112 clkc_audio: clock-controller@0 { 1113 compatible = "amlogic,axg-audio-clkc"; 1114 reg = <0x0 0x0 0x0 0xb4>; 1115 #clock-cells = <1>; 1116 1117 clocks = <&clkc CLKID_AUDIO>, 1118 <&clkc CLKID_MPLL0>, 1119 <&clkc CLKID_MPLL1>, 1120 <&clkc CLKID_MPLL2>, 1121 <&clkc CLKID_MPLL3>, 1122 <&clkc CLKID_HIFI_PLL>, 1123 <&clkc CLKID_FCLK_DIV3>, 1124 <&clkc CLKID_FCLK_DIV4>, 1125 <&clkc CLKID_GP0_PLL>; 1126 clock-names = "pclk", 1127 "mst_in0", 1128 "mst_in1", 1129 "mst_in2", 1130 "mst_in3", 1131 "mst_in4", 1132 "mst_in5", 1133 "mst_in6", 1134 "mst_in7"; 1135 1136 resets = <&reset RESET_AUDIO>; 1137 }; 1138 1139 toddr_a: audio-controller@100 { 1140 compatible = "amlogic,axg-toddr"; 1141 reg = <0x0 0x100 0x0 0x1c>; 1142 #sound-dai-cells = <0>; 1143 sound-name-prefix = "TODDR_A"; 1144 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1145 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1146 resets = <&arb AXG_ARB_TODDR_A>; 1147 status = "disabled"; 1148 }; 1149 1150 toddr_b: audio-controller@140 { 1151 compatible = "amlogic,axg-toddr"; 1152 reg = <0x0 0x140 0x0 0x1c>; 1153 #sound-dai-cells = <0>; 1154 sound-name-prefix = "TODDR_B"; 1155 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1156 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1157 resets = <&arb AXG_ARB_TODDR_B>; 1158 status = "disabled"; 1159 }; 1160 1161 toddr_c: audio-controller@180 { 1162 compatible = "amlogic,axg-toddr"; 1163 reg = <0x0 0x180 0x0 0x1c>; 1164 #sound-dai-cells = <0>; 1165 sound-name-prefix = "TODDR_C"; 1166 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1167 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1168 resets = <&arb AXG_ARB_TODDR_C>; 1169 status = "disabled"; 1170 }; 1171 1172 frddr_a: audio-controller@1c0 { 1173 compatible = "amlogic,axg-frddr"; 1174 reg = <0x0 0x1c0 0x0 0x1c>; 1175 #sound-dai-cells = <0>; 1176 sound-name-prefix = "FRDDR_A"; 1177 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1178 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1179 resets = <&arb AXG_ARB_FRDDR_A>; 1180 status = "disabled"; 1181 }; 1182 1183 frddr_b: audio-controller@200 { 1184 compatible = "amlogic,axg-frddr"; 1185 reg = <0x0 0x200 0x0 0x1c>; 1186 #sound-dai-cells = <0>; 1187 sound-name-prefix = "FRDDR_B"; 1188 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1189 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1190 resets = <&arb AXG_ARB_FRDDR_B>; 1191 status = "disabled"; 1192 }; 1193 1194 frddr_c: audio-controller@240 { 1195 compatible = "amlogic,axg-frddr"; 1196 reg = <0x0 0x240 0x0 0x1c>; 1197 #sound-dai-cells = <0>; 1198 sound-name-prefix = "FRDDR_C"; 1199 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1200 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1201 resets = <&arb AXG_ARB_FRDDR_C>; 1202 status = "disabled"; 1203 }; 1204 1205 arb: reset-controller@280 { 1206 compatible = "amlogic,meson-axg-audio-arb"; 1207 reg = <0x0 0x280 0x0 0x4>; 1208 #reset-cells = <1>; 1209 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1210 }; 1211 1212 tdmin_a: audio-controller@300 { 1213 compatible = "amlogic,axg-tdmin"; 1214 reg = <0x0 0x300 0x0 0x40>; 1215 sound-name-prefix = "TDMIN_A"; 1216 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1217 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1218 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1219 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1220 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1221 clock-names = "pclk", "sclk", "sclk_sel", 1222 "lrclk", "lrclk_sel"; 1223 status = "disabled"; 1224 }; 1225 1226 tdmin_b: audio-controller@340 { 1227 compatible = "amlogic,axg-tdmin"; 1228 reg = <0x0 0x340 0x0 0x40>; 1229 sound-name-prefix = "TDMIN_B"; 1230 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1231 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1232 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1233 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1234 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1235 clock-names = "pclk", "sclk", "sclk_sel", 1236 "lrclk", "lrclk_sel"; 1237 status = "disabled"; 1238 }; 1239 1240 tdmin_c: audio-controller@380 { 1241 compatible = "amlogic,axg-tdmin"; 1242 reg = <0x0 0x380 0x0 0x40>; 1243 sound-name-prefix = "TDMIN_C"; 1244 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1245 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1246 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1247 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1248 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1249 clock-names = "pclk", "sclk", "sclk_sel", 1250 "lrclk", "lrclk_sel"; 1251 status = "disabled"; 1252 }; 1253 1254 tdmin_lb: audio-controller@3c0 { 1255 compatible = "amlogic,axg-tdmin"; 1256 reg = <0x0 0x3c0 0x0 0x40>; 1257 sound-name-prefix = "TDMIN_LB"; 1258 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1259 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1260 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1261 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1262 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1263 clock-names = "pclk", "sclk", "sclk_sel", 1264 "lrclk", "lrclk_sel"; 1265 status = "disabled"; 1266 }; 1267 1268 spdifout: audio-controller@480 { 1269 compatible = "amlogic,axg-spdifout"; 1270 reg = <0x0 0x480 0x0 0x50>; 1271 #sound-dai-cells = <0>; 1272 sound-name-prefix = "SPDIFOUT"; 1273 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1274 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1275 clock-names = "pclk", "mclk"; 1276 status = "disabled"; 1277 }; 1278 1279 tdmout_a: audio-controller@500 { 1280 compatible = "amlogic,axg-tdmout"; 1281 reg = <0x0 0x500 0x0 0x40>; 1282 sound-name-prefix = "TDMOUT_A"; 1283 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1284 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1285 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1286 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1287 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1288 clock-names = "pclk", "sclk", "sclk_sel", 1289 "lrclk", "lrclk_sel"; 1290 status = "disabled"; 1291 }; 1292 1293 tdmout_b: audio-controller@540 { 1294 compatible = "amlogic,axg-tdmout"; 1295 reg = <0x0 0x540 0x0 0x40>; 1296 sound-name-prefix = "TDMOUT_B"; 1297 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1298 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1299 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1300 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1301 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1302 clock-names = "pclk", "sclk", "sclk_sel", 1303 "lrclk", "lrclk_sel"; 1304 status = "disabled"; 1305 }; 1306 1307 tdmout_c: audio-controller@580 { 1308 compatible = "amlogic,axg-tdmout"; 1309 reg = <0x0 0x580 0x0 0x40>; 1310 sound-name-prefix = "TDMOUT_C"; 1311 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1312 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1313 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1314 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1315 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1316 clock-names = "pclk", "sclk", "sclk_sel", 1317 "lrclk", "lrclk_sel"; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 aobus: bus@ff800000 { 1323 compatible = "simple-bus"; 1324 reg = <0x0 0xff800000 0x0 0x100000>; 1325 #address-cells = <2>; 1326 #size-cells = <2>; 1327 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1328 1329 sysctrl_AO: sys-ctrl@0 { 1330 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1331 reg = <0x0 0x0 0x0 0x100>; 1332 1333 clkc_AO: clock-controller { 1334 compatible = "amlogic,meson-axg-aoclkc"; 1335 #clock-cells = <1>; 1336 #reset-cells = <1>; 1337 }; 1338 }; 1339 1340 pinctrl_aobus: pinctrl@14 { 1341 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1342 #address-cells = <2>; 1343 #size-cells = <2>; 1344 ranges; 1345 1346 gpio_ao: bank@14 { 1347 reg = <0x0 0x00014 0x0 0x8>, 1348 <0x0 0x0002c 0x0 0x4>, 1349 <0x0 0x00024 0x0 0x8>; 1350 reg-names = "mux", "pull", "gpio"; 1351 gpio-controller; 1352 #gpio-cells = <2>; 1353 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1354 }; 1355 1356 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1357 mux { 1358 groups = "i2c_ao_sck_4"; 1359 function = "i2c_ao"; 1360 bias-disable; 1361 }; 1362 }; 1363 1364 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1365 mux { 1366 groups = "i2c_ao_sck_8"; 1367 function = "i2c_ao"; 1368 bias-disable; 1369 }; 1370 }; 1371 1372 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1373 mux { 1374 groups = "i2c_ao_sck_10"; 1375 function = "i2c_ao"; 1376 bias-disable; 1377 }; 1378 }; 1379 1380 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1381 mux { 1382 groups = "i2c_ao_sda_5"; 1383 function = "i2c_ao"; 1384 bias-disable; 1385 }; 1386 }; 1387 1388 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1389 mux { 1390 groups = "i2c_ao_sda_9"; 1391 function = "i2c_ao"; 1392 bias-disable; 1393 }; 1394 }; 1395 1396 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1397 mux { 1398 groups = "i2c_ao_sda_11"; 1399 function = "i2c_ao"; 1400 bias-disable; 1401 }; 1402 }; 1403 1404 remote_input_ao_pins: remote_input_ao { 1405 mux { 1406 groups = "remote_input_ao"; 1407 function = "remote_input_ao"; 1408 bias-disable; 1409 }; 1410 }; 1411 1412 uart_ao_a_pins: uart_ao_a { 1413 mux { 1414 groups = "uart_ao_tx_a", 1415 "uart_ao_rx_a"; 1416 function = "uart_ao_a"; 1417 bias-disable; 1418 }; 1419 }; 1420 1421 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1422 mux { 1423 groups = "uart_ao_cts_a", 1424 "uart_ao_rts_a"; 1425 function = "uart_ao_a"; 1426 bias-disable; 1427 }; 1428 }; 1429 1430 uart_ao_b_pins: uart_ao_b { 1431 mux { 1432 groups = "uart_ao_tx_b", 1433 "uart_ao_rx_b"; 1434 function = "uart_ao_b"; 1435 bias-disable; 1436 }; 1437 }; 1438 1439 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1440 mux { 1441 groups = "uart_ao_cts_b", 1442 "uart_ao_rts_b"; 1443 function = "uart_ao_b"; 1444 bias-disable; 1445 }; 1446 }; 1447 }; 1448 1449 sec_AO: ao-secure@140 { 1450 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1451 reg = <0x0 0x140 0x0 0x140>; 1452 amlogic,has-chip-id; 1453 }; 1454 1455 pwm_AO_cd: pwm@2000 { 1456 compatible = "amlogic,meson-axg-ao-pwm"; 1457 reg = <0x0 0x02000 0x0 0x20>; 1458 #pwm-cells = <3>; 1459 status = "disabled"; 1460 }; 1461 1462 uart_AO: serial@3000 { 1463 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1464 reg = <0x0 0x3000 0x0 0x18>; 1465 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1466 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1467 clock-names = "xtal", "pclk", "baud"; 1468 status = "disabled"; 1469 }; 1470 1471 uart_AO_B: serial@4000 { 1472 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1473 reg = <0x0 0x4000 0x0 0x18>; 1474 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1475 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1476 clock-names = "xtal", "pclk", "baud"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c_AO: i2c@5000 { 1481 compatible = "amlogic,meson-axg-i2c"; 1482 reg = <0x0 0x05000 0x0 0x20>; 1483 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1484 clocks = <&clkc CLKID_AO_I2C>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 status = "disabled"; 1488 }; 1489 1490 pwm_AO_ab: pwm@7000 { 1491 compatible = "amlogic,meson-axg-ao-pwm"; 1492 reg = <0x0 0x07000 0x0 0x20>; 1493 #pwm-cells = <3>; 1494 status = "disabled"; 1495 }; 1496 1497 ir: ir@8000 { 1498 compatible = "amlogic,meson-gxbb-ir"; 1499 reg = <0x0 0x8000 0x0 0x20>; 1500 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1501 status = "disabled"; 1502 }; 1503 1504 saradc: adc@9000 { 1505 compatible = "amlogic,meson-axg-saradc", 1506 "amlogic,meson-saradc"; 1507 reg = <0x0 0x9000 0x0 0x38>; 1508 #io-channel-cells = <1>; 1509 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1510 clocks = <&xtal>, 1511 <&clkc_AO CLKID_AO_SAR_ADC>, 1512 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1513 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1514 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1515 status = "disabled"; 1516 }; 1517 }; 1518 1519 gic: interrupt-controller@ffc01000 { 1520 compatible = "arm,gic-400"; 1521 reg = <0x0 0xffc01000 0 0x1000>, 1522 <0x0 0xffc02000 0 0x2000>, 1523 <0x0 0xffc04000 0 0x2000>, 1524 <0x0 0xffc06000 0 0x2000>; 1525 interrupt-controller; 1526 interrupts = <GIC_PPI 9 1527 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1528 #interrupt-cells = <3>; 1529 #address-cells = <0>; 1530 }; 1531 1532 cbus: bus@ffd00000 { 1533 compatible = "simple-bus"; 1534 reg = <0x0 0xffd00000 0x0 0x25000>; 1535 #address-cells = <2>; 1536 #size-cells = <2>; 1537 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1538 1539 reset: reset-controller@1004 { 1540 compatible = "amlogic,meson-axg-reset"; 1541 reg = <0x0 0x01004 0x0 0x9c>; 1542 #reset-cells = <1>; 1543 }; 1544 1545 gpio_intc: interrupt-controller@f080 { 1546 compatible = "amlogic,meson-gpio-intc"; 1547 reg = <0x0 0xf080 0x0 0x10>; 1548 interrupt-controller; 1549 #interrupt-cells = <2>; 1550 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1551 status = "disabled"; 1552 }; 1553 1554 watchdog@f0d0 { 1555 compatible = "amlogic,meson-gxbb-wdt"; 1556 reg = <0x0 0xf0d0 0x0 0x10>; 1557 clocks = <&xtal>; 1558 }; 1559 1560 pwm_ab: pwm@1b000 { 1561 compatible = "amlogic,meson-axg-ee-pwm"; 1562 reg = <0x0 0x1b000 0x0 0x20>; 1563 #pwm-cells = <3>; 1564 status = "disabled"; 1565 }; 1566 1567 pwm_cd: pwm@1a000 { 1568 compatible = "amlogic,meson-axg-ee-pwm"; 1569 reg = <0x0 0x1a000 0x0 0x20>; 1570 #pwm-cells = <3>; 1571 status = "disabled"; 1572 }; 1573 1574 spicc0: spi@13000 { 1575 compatible = "amlogic,meson-axg-spicc"; 1576 reg = <0x0 0x13000 0x0 0x3c>; 1577 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&clkc CLKID_SPICC0>; 1579 clock-names = "core"; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 spicc1: spi@15000 { 1586 compatible = "amlogic,meson-axg-spicc"; 1587 reg = <0x0 0x15000 0x0 0x3c>; 1588 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1589 clocks = <&clkc CLKID_SPICC1>; 1590 clock-names = "core"; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 i2c3: i2c@1c000 { 1597 compatible = "amlogic,meson-axg-i2c"; 1598 reg = <0x0 0x1c000 0x0 0x20>; 1599 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1600 clocks = <&clkc CLKID_I2C>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 status = "disabled"; 1604 }; 1605 1606 i2c2: i2c@1d000 { 1607 compatible = "amlogic,meson-axg-i2c"; 1608 reg = <0x0 0x1d000 0x0 0x20>; 1609 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1610 clocks = <&clkc CLKID_I2C>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c1: i2c@1e000 { 1617 compatible = "amlogic,meson-axg-i2c"; 1618 reg = <0x0 0x1e000 0x0 0x20>; 1619 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1620 clocks = <&clkc CLKID_I2C>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 i2c0: i2c@1f000 { 1627 compatible = "amlogic,meson-axg-i2c"; 1628 reg = <0x0 0x1f000 0x0 0x20>; 1629 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1630 clocks = <&clkc CLKID_I2C>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 1636 uart_B: serial@23000 { 1637 compatible = "amlogic,meson-gx-uart"; 1638 reg = <0x0 0x23000 0x0 0x18>; 1639 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1640 status = "disabled"; 1641 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1642 clock-names = "xtal", "pclk", "baud"; 1643 }; 1644 1645 uart_A: serial@24000 { 1646 compatible = "amlogic,meson-gx-uart"; 1647 reg = <0x0 0x24000 0x0 0x18>; 1648 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1649 status = "disabled"; 1650 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1651 clock-names = "xtal", "pclk", "baud"; 1652 }; 1653 }; 1654 1655 apb: bus@ffe00000 { 1656 compatible = "simple-bus"; 1657 reg = <0x0 0xffe00000 0x0 0x200000>; 1658 #address-cells = <2>; 1659 #size-cells = <2>; 1660 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1661 1662 sd_emmc_b: sd@5000 { 1663 compatible = "amlogic,meson-axg-mmc"; 1664 reg = <0x0 0x5000 0x0 0x800>; 1665 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1666 status = "disabled"; 1667 clocks = <&clkc CLKID_SD_EMMC_B>, 1668 <&clkc CLKID_SD_EMMC_B_CLK0>, 1669 <&clkc CLKID_FCLK_DIV2>; 1670 clock-names = "core", "clkin0", "clkin1"; 1671 resets = <&reset RESET_SD_EMMC_B>; 1672 }; 1673 1674 sd_emmc_c: mmc@7000 { 1675 compatible = "amlogic,meson-axg-mmc"; 1676 reg = <0x0 0x7000 0x0 0x800>; 1677 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1678 status = "disabled"; 1679 clocks = <&clkc CLKID_SD_EMMC_C>, 1680 <&clkc CLKID_SD_EMMC_C_CLK0>, 1681 <&clkc CLKID_FCLK_DIV2>; 1682 clock-names = "core", "clkin0", "clkin1"; 1683 resets = <&reset RESET_SD_EMMC_C>; 1684 }; 1685 }; 1686 1687 sram: sram@fffc0000 { 1688 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1689 reg = <0x0 0xfffc0000 0x0 0x20000>; 1690 #address-cells = <1>; 1691 #size-cells = <1>; 1692 ranges = <0 0x0 0xfffc0000 0x20000>; 1693 1694 cpu_scp_lpri: scp-shmem@13000 { 1695 compatible = "amlogic,meson-axg-scp-shmem"; 1696 reg = <0x13000 0x400>; 1697 }; 1698 1699 cpu_scp_hpri: scp-shmem@13400 { 1700 compatible = "amlogic,meson-axg-scp-shmem"; 1701 reg = <0x13400 0x400>; 1702 }; 1703 }; 1704 }; 1705 1706 timer { 1707 compatible = "arm,armv8-timer"; 1708 interrupts = <GIC_PPI 13 1709 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1710 <GIC_PPI 14 1711 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1712 <GIC_PPI 11 1713 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1714 <GIC_PPI 10 1715 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1716 }; 1717 1718 xtal: xtal-clk { 1719 compatible = "fixed-clock"; 1720 clock-frequency = <24000000>; 1721 clock-output-names = "xtal"; 1722 #clock-cells = <0>; 1723 }; 1724}; 1725