1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-audio-clkc.h>
10#include <dt-bindings/clock/axg-clkc.h>
11#include <dt-bindings/clock/axg-aoclkc.h>
12#include <dt-bindings/gpio/meson-axg-gpio.h>
13#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
14
15/ {
16	compatible = "amlogic,meson-axg";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	reserved-memory {
23		#address-cells = <2>;
24		#size-cells = <2>;
25		ranges;
26
27		/* 16 MiB reserved for Hardware ROM Firmware */
28		hwrom_reserved: hwrom@0 {
29			reg = <0x0 0x0 0x0 0x1000000>;
30			no-map;
31		};
32
33		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
34		secmon_reserved: secmon@5000000 {
35			reg = <0x0 0x05000000 0x0 0x300000>;
36			no-map;
37		};
38	};
39
40	cpus {
41		#address-cells = <0x2>;
42		#size-cells = <0x0>;
43
44		cpu0: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53", "arm,armv8";
47			reg = <0x0 0x0>;
48			enable-method = "psci";
49			next-level-cache = <&l2>;
50		};
51
52		cpu1: cpu@1 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a53", "arm,armv8";
55			reg = <0x0 0x1>;
56			enable-method = "psci";
57			next-level-cache = <&l2>;
58		};
59
60		cpu2: cpu@2 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53", "arm,armv8";
63			reg = <0x0 0x2>;
64			enable-method = "psci";
65			next-level-cache = <&l2>;
66		};
67
68		cpu3: cpu@3 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53", "arm,armv8";
71			reg = <0x0 0x3>;
72			enable-method = "psci";
73			next-level-cache = <&l2>;
74		};
75
76		l2: l2-cache0 {
77			compatible = "cache";
78		};
79	};
80
81	arm-pmu {
82		compatible = "arm,cortex-a53-pmu";
83		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88	};
89
90	psci {
91		compatible = "arm,psci-1.0";
92		method = "smc";
93	};
94
95	timer {
96		compatible = "arm,armv8-timer";
97		interrupts = <GIC_PPI 13
98			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
99			     <GIC_PPI 14
100			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
101			     <GIC_PPI 11
102			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
103			     <GIC_PPI 10
104			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
105	};
106
107	xtal: xtal-clk {
108		compatible = "fixed-clock";
109		clock-frequency = <24000000>;
110		clock-output-names = "xtal";
111		#clock-cells = <0>;
112	};
113
114	ao_alt_xtal: ao_alt_xtal-clk {
115		compatible = "fixed-clock";
116		clock-frequency = <32000000>;
117		clock-output-names = "ao_alt_xtal";
118		#clock-cells = <0>;
119	};
120
121	soc {
122		compatible = "simple-bus";
123		#address-cells = <2>;
124		#size-cells = <2>;
125		ranges;
126
127		apb: apb@ffe00000 {
128			compatible = "simple-bus";
129			reg = <0x0 0xffe00000 0x0 0x200000>;
130			#address-cells = <2>;
131			#size-cells = <2>;
132			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
133
134			sd_emmc_b: sd@5000 {
135				compatible = "amlogic,meson-axg-mmc";
136				reg = <0x0 0x5000 0x0 0x2000>;
137				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
138				status = "disabled";
139				clocks = <&clkc CLKID_SD_EMMC_B>,
140					<&clkc CLKID_SD_EMMC_B_CLK0>,
141					<&clkc CLKID_FCLK_DIV2>;
142				clock-names = "core", "clkin0", "clkin1";
143				resets = <&reset RESET_SD_EMMC_B>;
144			};
145
146			sd_emmc_c: mmc@7000 {
147				compatible = "amlogic,meson-axg-mmc";
148				reg = <0x0 0x7000 0x0 0x2000>;
149				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
150				status = "disabled";
151				clocks = <&clkc CLKID_SD_EMMC_C>,
152					<&clkc CLKID_SD_EMMC_C_CLK0>,
153					<&clkc CLKID_FCLK_DIV2>;
154				clock-names = "core", "clkin0", "clkin1";
155				resets = <&reset RESET_SD_EMMC_C>;
156			};
157		};
158
159		audio: bus@ff642000 {
160			compatible = "simple-bus";
161			reg = <0x0 0xff642000 0x0 0x2000>;
162			#address-cells = <2>;
163			#size-cells = <2>;
164			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
165
166			clkc_audio: clock-controller@0 {
167				compatible = "amlogic,axg-audio-clkc";
168				reg = <0x0 0x0 0x0 0xb4>;
169				#clock-cells = <1>;
170
171				clocks = <&clkc CLKID_AUDIO>,
172					 <&clkc CLKID_MPLL0>,
173					 <&clkc CLKID_MPLL1>,
174					 <&clkc CLKID_MPLL2>,
175					 <&clkc CLKID_MPLL3>,
176					 <&clkc CLKID_HIFI_PLL>,
177					 <&clkc CLKID_FCLK_DIV3>,
178					 <&clkc CLKID_FCLK_DIV4>,
179					 <&clkc CLKID_GP0_PLL>;
180				clock-names = "pclk",
181					      "mst_in0",
182					      "mst_in1",
183					      "mst_in2",
184					      "mst_in3",
185					      "mst_in4",
186					      "mst_in5",
187					      "mst_in6",
188					      "mst_in7";
189
190				resets = <&reset RESET_AUDIO>;
191			};
192
193			arb: reset-controller@280 {
194				compatible = "amlogic,meson-axg-audio-arb";
195				reg = <0x0 0x280 0x0 0x4>;
196				#reset-cells = <1>;
197				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
198			};
199		};
200
201		cbus: bus@ffd00000 {
202			compatible = "simple-bus";
203			reg = <0x0 0xffd00000 0x0 0x25000>;
204			#address-cells = <2>;
205			#size-cells = <2>;
206			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
207
208			gpio_intc: interrupt-controller@f080 {
209				compatible = "amlogic,meson-gpio-intc";
210				reg = <0x0 0xf080 0x0 0x10>;
211				interrupt-controller;
212				#interrupt-cells = <2>;
213				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
214				status = "disabled";
215			};
216
217			pwm_ab: pwm@1b000 {
218				compatible = "amlogic,meson-axg-ee-pwm";
219				reg = <0x0 0x1b000 0x0 0x20>;
220				#pwm-cells = <3>;
221				status = "disabled";
222			};
223
224			pwm_cd: pwm@1a000 {
225				compatible = "amlogic,meson-axg-ee-pwm";
226				reg = <0x0 0x1a000 0x0 0x20>;
227				#pwm-cells = <3>;
228				status = "disabled";
229			};
230
231			reset: reset-controller@1004 {
232				compatible = "amlogic,meson-axg-reset";
233				reg = <0x0 0x01004 0x0 0x9c>;
234				#reset-cells = <1>;
235			};
236
237			spicc0: spi@13000 {
238				compatible = "amlogic,meson-axg-spicc";
239				reg = <0x0 0x13000 0x0 0x3c>;
240				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
241				clocks = <&clkc CLKID_SPICC0>;
242				clock-names = "core";
243				#address-cells = <1>;
244				#size-cells = <0>;
245				status = "disabled";
246			};
247
248			spicc1: spi@15000 {
249				compatible = "amlogic,meson-axg-spicc";
250				reg = <0x0 0x15000 0x0 0x3c>;
251				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
252				clocks = <&clkc CLKID_SPICC1>;
253				clock-names = "core";
254				#address-cells = <1>;
255				#size-cells = <0>;
256				status = "disabled";
257			};
258
259			i2c0: i2c@1f000 {
260				compatible = "amlogic,meson-axg-i2c";
261				reg = <0x0 0x1f000 0x0 0x20>;
262				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
263				clocks = <&clkc CLKID_I2C>;
264				#address-cells = <1>;
265				#size-cells = <0>;
266				status = "disabled";
267			};
268
269			i2c1: i2c@1e000 {
270				compatible = "amlogic,meson-axg-i2c";
271				reg = <0x0 0x1e000 0x0 0x20>;
272				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
273				clocks = <&clkc CLKID_I2C>;
274				#address-cells = <1>;
275				#size-cells = <0>;
276				status = "disabled";
277			};
278
279			i2c2: i2c@1d000 {
280				compatible = "amlogic,meson-axg-i2c";
281				reg = <0x0 0x1d000 0x0 0x20>;
282				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
283				clocks = <&clkc CLKID_I2C>;
284				#address-cells = <1>;
285				#size-cells = <0>;
286				status = "disabled";
287			};
288
289			i2c3: i2c@1c000 {
290				compatible = "amlogic,meson-axg-i2c";
291				reg = <0x0 0x1c000 0x0 0x20>;
292				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
293				clocks = <&clkc CLKID_I2C>;
294				#address-cells = <1>;
295				#size-cells = <0>;
296				status = "disabled";
297			};
298
299			uart_A: serial@24000 {
300				compatible = "amlogic,meson-gx-uart";
301				reg = <0x0 0x24000 0x0 0x18>;
302				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
303				status = "disabled";
304				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
305				clock-names = "xtal", "pclk", "baud";
306			};
307
308			uart_B: serial@23000 {
309				compatible = "amlogic,meson-gx-uart";
310				reg = <0x0 0x23000 0x0 0x18>;
311				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
312				status = "disabled";
313				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
314				clock-names = "xtal", "pclk", "baud";
315			};
316		};
317
318		ethmac: ethernet@ff3f0000 {
319			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
320			reg = <0x0 0xff3f0000 0x0 0x10000
321				0x0 0xff634540 0x0 0x8>;
322			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
323			interrupt-names = "macirq";
324			clocks = <&clkc CLKID_ETH>,
325				 <&clkc CLKID_FCLK_DIV2>,
326				 <&clkc CLKID_MPLL2>;
327			clock-names = "stmmaceth", "clkin0", "clkin1";
328			status = "disabled";
329		};
330
331		gic: interrupt-controller@ffc01000 {
332			compatible = "arm,gic-400";
333			reg = <0x0 0xffc01000 0 0x1000>,
334			      <0x0 0xffc02000 0 0x2000>,
335			      <0x0 0xffc04000 0 0x2000>,
336			      <0x0 0xffc06000 0 0x2000>;
337			interrupt-controller;
338			interrupts = <GIC_PPI 9
339				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
340			#interrupt-cells = <3>;
341			#address-cells = <0>;
342		};
343
344		hiubus: bus@ff63c000 {
345			compatible = "simple-bus";
346			reg = <0x0 0xff63c000 0x0 0x1c00>;
347			#address-cells = <2>;
348			#size-cells = <2>;
349			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
350
351			sysctrl: system-controller@0 {
352				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
353				reg = <0 0 0 0x400>;
354
355				clkc: clock-controller {
356					compatible = "amlogic,axg-clkc";
357					#clock-cells = <1>;
358				};
359			};
360		};
361
362		mailbox: mailbox@ff63dc00 {
363			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
364			reg = <0 0xff63dc00 0 0x400>;
365			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
366				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
367				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
368			#mbox-cells = <1>;
369		};
370
371		periphs: periphs@ff634000 {
372			compatible = "simple-bus";
373			reg = <0x0 0xff634000 0x0 0x2000>;
374			#address-cells = <2>;
375			#size-cells = <2>;
376			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
377
378			hwrng: rng {
379				compatible = "amlogic,meson-rng";
380				reg = <0x0 0x18 0x0 0x4>;
381				clocks = <&clkc CLKID_RNG0>;
382				clock-names = "core";
383			};
384
385			pinctrl_periphs: pinctrl@480 {
386				compatible = "amlogic,meson-axg-periphs-pinctrl";
387				#address-cells = <2>;
388				#size-cells = <2>;
389				ranges;
390
391				gpio: bank@480 {
392					reg = <0x0 0x00480 0x0 0x40>,
393						<0x0 0x004e8 0x0 0x14>,
394						<0x0 0x00520 0x0 0x14>,
395						<0x0 0x00430 0x0 0x3c>;
396					reg-names = "mux", "pull", "pull-enable", "gpio";
397					gpio-controller;
398					#gpio-cells = <2>;
399					gpio-ranges = <&pinctrl_periphs 0 0 86>;
400				};
401
402				emmc_pins: emmc {
403					mux {
404						groups = "emmc_nand_d0",
405							"emmc_nand_d1",
406							"emmc_nand_d2",
407							"emmc_nand_d3",
408							"emmc_nand_d4",
409							"emmc_nand_d5",
410							"emmc_nand_d6",
411							"emmc_nand_d7",
412							"emmc_clk",
413							"emmc_cmd",
414							"emmc_ds";
415						function = "emmc";
416					};
417				};
418
419				emmc_clk_gate_pins: emmc_clk_gate {
420					mux {
421						groups = "BOOT_8";
422						function = "gpio_periphs";
423					};
424					cfg-pull-down {
425						pins = "BOOT_8";
426						bias-pull-down;
427					};
428				};
429
430				sdio_pins: sdio {
431					mux {
432						groups = "sdio_d0",
433							"sdio_d1",
434							"sdio_d2",
435							"sdio_d3",
436							"sdio_cmd",
437							"sdio_clk";
438						function = "sdio";
439					};
440				};
441
442				sdio_clk_gate_pins: sdio_clk_gate {
443					mux {
444						groups = "GPIOX_4";
445						function = "gpio_periphs";
446					};
447					cfg-pull-down {
448						pins = "GPIOX_4";
449						bias-pull-down;
450					};
451				};
452
453				eth_rmii_x_pins: eth-x-rmii {
454					mux {
455						groups = "eth_mdio_x",
456						       "eth_mdc_x",
457						       "eth_rgmii_rx_clk_x",
458						       "eth_rx_dv_x",
459						       "eth_rxd0_x",
460						       "eth_rxd1_x",
461						       "eth_txen_x",
462						       "eth_txd0_x",
463						       "eth_txd1_x";
464						function = "eth";
465					};
466				};
467
468				eth_rmii_y_pins: eth-y-rmii {
469					mux {
470						groups = "eth_mdio_y",
471						       "eth_mdc_y",
472						       "eth_rgmii_rx_clk_y",
473						       "eth_rx_dv_y",
474						       "eth_rxd0_y",
475						       "eth_rxd1_y",
476						       "eth_txen_y",
477						       "eth_txd0_y",
478						       "eth_txd1_y";
479						function = "eth";
480					};
481				};
482
483				eth_rgmii_x_pins: eth-x-rgmii {
484					mux {
485						groups = "eth_mdio_x",
486						       "eth_mdc_x",
487						       "eth_rgmii_rx_clk_x",
488						       "eth_rx_dv_x",
489						       "eth_rxd0_x",
490						       "eth_rxd1_x",
491						       "eth_rxd2_rgmii",
492						       "eth_rxd3_rgmii",
493						       "eth_rgmii_tx_clk",
494						       "eth_txen_x",
495						       "eth_txd0_x",
496						       "eth_txd1_x",
497						       "eth_txd2_rgmii",
498						       "eth_txd3_rgmii";
499						function = "eth";
500					};
501				};
502
503				eth_rgmii_y_pins: eth-y-rgmii {
504					mux {
505						groups = "eth_mdio_y",
506						       "eth_mdc_y",
507						       "eth_rgmii_rx_clk_y",
508						       "eth_rx_dv_y",
509						       "eth_rxd0_y",
510						       "eth_rxd1_y",
511						       "eth_rxd2_rgmii",
512						       "eth_rxd3_rgmii",
513						       "eth_rgmii_tx_clk",
514						       "eth_txen_y",
515						       "eth_txd0_y",
516						       "eth_txd1_y",
517						       "eth_txd2_rgmii",
518						       "eth_txd3_rgmii";
519						function = "eth";
520					};
521				};
522
523				pdm_dclk_a14_pins: pdm_dclk_a14 {
524					mux {
525						groups = "pdm_dclk_a14";
526						function = "pdm";
527					};
528				};
529
530				pdm_dclk_a19_pins: pdm_dclk_a19 {
531					mux {
532						groups = "pdm_dclk_a19";
533						function = "pdm";
534					};
535				};
536
537				pdm_din0_pins: pdm_din0 {
538					mux {
539						groups = "pdm_din0";
540						function = "pdm";
541					};
542				};
543
544				pdm_din1_pins: pdm_din1 {
545					mux {
546						groups = "pdm_din1";
547						function = "pdm";
548					};
549				};
550
551				pdm_din2_pins: pdm_din2 {
552					mux {
553						groups = "pdm_din2";
554						function = "pdm";
555					};
556				};
557
558				pdm_din3_pins: pdm_din3 {
559					mux {
560						groups = "pdm_din3";
561						function = "pdm";
562					};
563				};
564
565				pwm_a_a_pins: pwm_a_a {
566					mux {
567						groups = "pwm_a_a";
568						function = "pwm_a";
569					};
570				};
571
572				pwm_a_x18_pins: pwm_a_x18 {
573					mux {
574						groups = "pwm_a_x18";
575						function = "pwm_a";
576					};
577				};
578
579				pwm_a_x20_pins: pwm_a_x20 {
580					mux {
581						groups = "pwm_a_x20";
582						function = "pwm_a";
583					};
584				};
585
586				pwm_a_z_pins: pwm_a_z {
587					mux {
588						groups = "pwm_a_z";
589						function = "pwm_a";
590					};
591				};
592
593				pwm_b_a_pins: pwm_b_a {
594					mux {
595						groups = "pwm_b_a";
596						function = "pwm_b";
597					};
598				};
599
600				pwm_b_x_pins: pwm_b_x {
601					mux {
602						groups = "pwm_b_x";
603						function = "pwm_b";
604					};
605				};
606
607				pwm_b_z_pins: pwm_b_z {
608					mux {
609						groups = "pwm_b_z";
610						function = "pwm_b";
611					};
612				};
613
614				pwm_c_a_pins: pwm_c_a {
615					mux {
616						groups = "pwm_c_a";
617						function = "pwm_c";
618					};
619				};
620
621				pwm_c_x10_pins: pwm_c_x10 {
622					mux {
623						groups = "pwm_c_x10";
624						function = "pwm_c";
625					};
626				};
627
628				pwm_c_x17_pins: pwm_c_x17 {
629					mux {
630						groups = "pwm_c_x17";
631						function = "pwm_c";
632					};
633				};
634
635				pwm_d_x11_pins: pwm_d_x11 {
636					mux {
637						groups = "pwm_d_x11";
638						function = "pwm_d";
639					};
640				};
641
642				pwm_d_x16_pins: pwm_d_x16 {
643					mux {
644						groups = "pwm_d_x16";
645						function = "pwm_d";
646					};
647				};
648
649				spdif_in_z_pins: spdif_in_z {
650					mux {
651						groups = "spdif_in_z";
652						function = "spdif_in";
653					};
654				};
655
656				spdif_in_a1_pins: spdif_in_a1 {
657					mux {
658						groups = "spdif_in_a1";
659						function = "spdif_in";
660					};
661				};
662
663				spdif_in_a7_pins: spdif_in_a7 {
664					mux {
665						groups = "spdif_in_a7";
666						function = "spdif_in";
667					};
668				};
669
670				spdif_in_a19_pins: spdif_in_a19 {
671					mux {
672						groups = "spdif_in_a19";
673						function = "spdif_in";
674					};
675				};
676
677				spdif_in_a20_pins: spdif_in_a20 {
678					mux {
679						groups = "spdif_in_a20";
680						function = "spdif_in";
681					};
682				};
683
684				spdif_out_z_pins: spdif_out_z {
685					mux {
686						groups = "spdif_out_z";
687						function = "spdif_out";
688					};
689				};
690
691				spdif_out_a1_pins: spdif_out_a1 {
692					mux {
693						groups = "spdif_out_a1";
694						function = "spdif_out";
695					};
696				};
697
698				spdif_out_a11_pins: spdif_out_a11 {
699					mux {
700						groups = "spdif_out_a11";
701						function = "spdif_out";
702					};
703				};
704
705				spdif_out_a19_pins: spdif_out_a19 {
706					mux {
707						groups = "spdif_out_a19";
708						function = "spdif_out";
709					};
710				};
711
712				spdif_out_a20_pins: spdif_out_a20 {
713					mux {
714						groups = "spdif_out_a20";
715						function = "spdif_out";
716					};
717				};
718
719				spi0_pins: spi0 {
720					mux {
721						groups = "spi0_miso",
722							"spi0_mosi",
723							"spi0_clk";
724						function = "spi0";
725					};
726				};
727
728				spi0_ss0_pins: spi0_ss0 {
729					mux {
730						groups = "spi0_ss0";
731						function = "spi0";
732					};
733				};
734
735				spi0_ss1_pins: spi0_ss1 {
736					mux {
737						groups = "spi0_ss1";
738						function = "spi0";
739					};
740				};
741
742				spi0_ss2_pins: spi0_ss2 {
743					mux {
744						groups = "spi0_ss2";
745						function = "spi0";
746					};
747				};
748
749
750				spi1_a_pins: spi1_a {
751					mux {
752						groups = "spi1_miso_a",
753							"spi1_mosi_a",
754							"spi1_clk_a";
755						function = "spi1";
756					};
757				};
758
759				spi1_ss0_a_pins: spi1_ss0_a {
760					mux {
761						groups = "spi1_ss0_a";
762						function = "spi1";
763					};
764				};
765
766				spi1_ss1_pins: spi1_ss1 {
767					mux {
768						groups = "spi1_ss1";
769						function = "spi1";
770					};
771				};
772
773				spi1_x_pins: spi1_x {
774					mux {
775						groups = "spi1_miso_x",
776							"spi1_mosi_x",
777							"spi1_clk_x";
778						function = "spi1";
779					};
780				};
781
782				spi1_ss0_x_pins: spi1_ss0_x {
783					mux {
784						groups = "spi1_ss0_x";
785						function = "spi1";
786					};
787				};
788
789				i2c0_pins: i2c0 {
790					mux {
791						groups = "i2c0_sck",
792							"i2c0_sda";
793						function = "i2c0";
794					};
795				};
796
797				i2c1_z_pins: i2c1_z {
798					mux {
799						groups = "i2c1_sck_z",
800							"i2c1_sda_z";
801						function = "i2c1";
802					};
803				};
804
805				i2c1_x_pins: i2c1_x {
806					mux {
807						groups = "i2c1_sck_x",
808							"i2c1_sda_x";
809						function = "i2c1";
810					};
811				};
812
813				i2c2_x_pins: i2c2_x {
814					mux {
815						groups = "i2c2_sck_x",
816							"i2c2_sda_x";
817						function = "i2c2";
818					};
819				};
820
821				i2c2_a_pins: i2c2_a {
822					mux {
823						groups = "i2c2_sck_a",
824							"i2c2_sda_a";
825						function = "i2c2";
826					};
827				};
828
829				i2c3_a6_pins: i2c3_a6 {
830					mux {
831						groups = "i2c3_sda_a6",
832							"i2c3_sck_a7";
833						function = "i2c3";
834					};
835				};
836
837				i2c3_a12_pins: i2c3_a12 {
838					mux {
839						groups = "i2c3_sda_a12",
840							"i2c3_sck_a13";
841						function = "i2c3";
842					};
843				};
844
845				i2c3_a19_pins: i2c3_a19 {
846					mux {
847						groups = "i2c3_sda_a19",
848							"i2c3_sck_a20";
849						function = "i2c3";
850					};
851				};
852
853				uart_a_pins: uart_a {
854					mux {
855						groups = "uart_tx_a",
856							"uart_rx_a";
857						function = "uart_a";
858					};
859				};
860
861				uart_a_cts_rts_pins: uart_a_cts_rts {
862					mux {
863						groups = "uart_cts_a",
864							"uart_rts_a";
865						function = "uart_a";
866					};
867				};
868
869				uart_b_x_pins: uart_b_x {
870					mux {
871						groups = "uart_tx_b_x",
872							"uart_rx_b_x";
873						function = "uart_b";
874					};
875				};
876
877				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
878					mux {
879						groups = "uart_cts_b_x",
880							"uart_rts_b_x";
881						function = "uart_b";
882					};
883				};
884
885				uart_b_z_pins: uart_b_z {
886					mux {
887						groups = "uart_tx_b_z",
888							"uart_rx_b_z";
889						function = "uart_b";
890					};
891				};
892
893				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
894					mux {
895						groups = "uart_cts_b_z",
896							"uart_rts_b_z";
897						function = "uart_b";
898					};
899				};
900
901				uart_ao_b_z_pins: uart_ao_b_z {
902					mux {
903						groups = "uart_ao_tx_b_z",
904							"uart_ao_rx_b_z";
905						function = "uart_ao_b_z";
906					};
907				};
908
909				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
910					mux {
911						groups = "uart_ao_cts_b_z",
912							"uart_ao_rts_b_z";
913						function = "uart_ao_b_z";
914					};
915				};
916
917				mclk_b_pins: mclk_b {
918					mux {
919						groups = "mclk_b";
920						function = "mclk_b";
921					};
922				};
923
924				mclk_c_pins: mclk_c {
925					mux {
926						groups = "mclk_c";
927						function = "mclk_c";
928					};
929				};
930
931				tdma_sclk_pins: tdma_sclk {
932					mux {
933						groups = "tdma_sclk";
934						function = "tdma";
935					};
936				};
937
938				tdma_sclk_slv_pins: tdma_sclk_slv {
939					mux {
940						groups = "tdma_sclk_slv";
941						function = "tdma";
942					};
943				};
944
945				tdma_fs_pins: tdma_fs {
946					mux {
947						groups = "tdma_fs";
948						function = "tdma";
949					};
950				};
951
952				tdma_fs_slv_pins: tdma_fs_slv {
953					mux {
954						groups = "tdma_fs_slv";
955						function = "tdma";
956					};
957				};
958
959				tdma_din0_pins: tdma_din0 {
960					mux {
961						groups = "tdma_din0";
962						function = "tdma";
963					};
964				};
965
966				tdma_dout0_x14_pins: tdma_dout0_x14 {
967					mux {
968						groups = "tdma_dout0_x14";
969						function = "tdma";
970					};
971				};
972
973				tdma_dout0_x15_pins: tdma_dout0_x15 {
974					mux {
975						groups = "tdma_dout0_x15";
976						function = "tdma";
977					};
978				};
979
980				tdma_dout1_pins: tdma_dout1 {
981					mux {
982						groups = "tdma_dout1";
983						function = "tdma";
984					};
985				};
986
987				tdma_din1_pins: tdma_din1 {
988					mux {
989						groups = "tdma_din1";
990						function = "tdma";
991					};
992				};
993
994				tdmb_sclk_pins: tdmb_sclk {
995					mux {
996						groups = "tdmb_sclk";
997						function = "tdmb";
998					};
999				};
1000
1001				tdmb_sclk_slv_pins: tdmb_sclk_slv {
1002					mux {
1003						groups = "tdmb_sclk_slv";
1004						function = "tdmb";
1005					};
1006				};
1007
1008				tdmb_fs_pins: tdmb_fs {
1009					mux {
1010						groups = "tdmb_fs";
1011						function = "tdmb";
1012					};
1013				};
1014
1015				tdmb_fs_slv_pins: tdmb_fs_slv {
1016					mux {
1017						groups = "tdmb_fs_slv";
1018						function = "tdmb";
1019					};
1020				};
1021
1022				tdmb_din0_pins: tdmb_din0 {
1023					mux {
1024						groups = "tdmb_din0";
1025						function = "tdmb";
1026					};
1027				};
1028
1029				tdmb_dout0_pins: tdmb_dout0 {
1030					mux {
1031						groups = "tdmb_dout0";
1032						function = "tdmb";
1033					};
1034				};
1035
1036				tdmb_din1_pins: tdmb_din1 {
1037					mux {
1038						groups = "tdmb_din1";
1039						function = "tdmb";
1040					};
1041				};
1042
1043				tdmb_dout1_pins: tdmb_dout1 {
1044					mux {
1045						groups = "tdmb_dout1";
1046						function = "tdmb";
1047					};
1048				};
1049
1050				tdmb_din2_pins: tdmb_din2 {
1051					mux {
1052						groups = "tdmb_din2";
1053						function = "tdmb";
1054					};
1055				};
1056
1057				tdmb_dout2_pins: tdmb_dout2 {
1058					mux {
1059						groups = "tdmb_dout2";
1060						function = "tdmb";
1061					};
1062				};
1063
1064				tdmb_din3_pins: tdmb_din3 {
1065					mux {
1066						groups = "tdmb_din3";
1067						function = "tdmb";
1068					};
1069				};
1070
1071				tdmb_dout3_pins: tdmb_dout3 {
1072					mux {
1073						groups = "tdmb_dout3";
1074						function = "tdmb";
1075					};
1076				};
1077
1078				tdmc_sclk_pins: tdmc_sclk {
1079					mux {
1080						groups = "tdmc_sclk";
1081						function = "tdmc";
1082					};
1083				};
1084
1085				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1086					mux {
1087						groups = "tdmc_sclk_slv";
1088						function = "tdmc";
1089					};
1090				};
1091
1092				tdmc_fs_pins: tdmc_fs {
1093					mux {
1094						groups = "tdmc_fs";
1095						function = "tdmc";
1096					};
1097				};
1098
1099				tdmc_fs_slv_pins: tdmc_fs_slv {
1100					mux {
1101						groups = "tdmc_fs_slv";
1102						function = "tdmc";
1103					};
1104				};
1105
1106				tdmc_din0_pins: tdmc_din0 {
1107					mux {
1108						groups = "tdmc_din0";
1109						function = "tdmc";
1110					};
1111				};
1112
1113				tdmc_dout0_pins: tdmc_dout0 {
1114					mux {
1115						groups = "tdmc_dout0";
1116						function = "tdmc";
1117					};
1118				};
1119
1120				tdmc_din1_pins: tdmc_din1 {
1121					mux {
1122						groups = "tdmc_din1";
1123						function = "tdmc";
1124					};
1125				};
1126
1127				tdmc_dout1_pins: tdmc_dout1 {
1128					mux {
1129						groups = "tdmc_dout1";
1130						function = "tdmc";
1131					};
1132				};
1133
1134				tdmc_din2_pins: tdmc_din2 {
1135					mux {
1136						groups = "tdmc_din2";
1137						function = "tdmc";
1138					};
1139				};
1140
1141				tdmc_dout2_pins: tdmc_dout2 {
1142					mux {
1143						groups = "tdmc_dout2";
1144						function = "tdmc";
1145					};
1146				};
1147
1148				tdmc_din3_pins: tdmc_din3 {
1149					mux {
1150						groups = "tdmc_din3";
1151						function = "tdmc";
1152					};
1153				};
1154
1155				tdmc_dout3_pins: tdmc_dout3 {
1156					mux {
1157						groups = "tdmc_dout3";
1158						function = "tdmc";
1159					};
1160				};
1161			};
1162		};
1163
1164		sram: sram@fffc0000 {
1165			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1166			reg = <0x0 0xfffc0000 0x0 0x20000>;
1167			#address-cells = <1>;
1168			#size-cells = <1>;
1169			ranges = <0 0x0 0xfffc0000 0x20000>;
1170
1171			cpu_scp_lpri: scp-shmem@0 {
1172				compatible = "amlogic,meson-axg-scp-shmem";
1173				reg = <0x13000 0x400>;
1174			};
1175
1176			cpu_scp_hpri: scp-shmem@200 {
1177				compatible = "amlogic,meson-axg-scp-shmem";
1178				reg = <0x13400 0x400>;
1179			};
1180		};
1181
1182		aobus: bus@ff800000 {
1183			compatible = "simple-bus";
1184			reg = <0x0 0xff800000 0x0 0x100000>;
1185			#address-cells = <2>;
1186			#size-cells = <2>;
1187			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1188
1189			sysctrl_AO: sys-ctrl@0 {
1190				compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1191				reg =  <0x0 0x0 0x0 0x100>;
1192
1193				clkc_AO: clock-controller {
1194					compatible = "amlogic,meson-axg-aoclkc";
1195					#clock-cells = <1>;
1196					#reset-cells = <1>;
1197				};
1198			};
1199
1200			pinctrl_aobus: pinctrl@14 {
1201				compatible = "amlogic,meson-axg-aobus-pinctrl";
1202				#address-cells = <2>;
1203				#size-cells = <2>;
1204				ranges;
1205
1206				gpio_ao: bank@14 {
1207					reg = <0x0 0x00014 0x0 0x8>,
1208						<0x0 0x0002c 0x0 0x4>,
1209						<0x0 0x00024 0x0 0x8>;
1210					reg-names = "mux", "pull", "gpio";
1211					gpio-controller;
1212					#gpio-cells = <2>;
1213					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1214				};
1215
1216				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1217					mux {
1218						groups = "i2c_ao_sck_4";
1219						function = "i2c_ao";
1220					};
1221				};
1222
1223				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1224					mux {
1225						groups = "i2c_ao_sck_8";
1226						function = "i2c_ao";
1227					};
1228				};
1229
1230				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1231					mux {
1232						groups = "i2c_ao_sck_10";
1233						function = "i2c_ao";
1234					};
1235				};
1236
1237				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1238					mux {
1239						groups = "i2c_ao_sda_5";
1240						function = "i2c_ao";
1241					};
1242				};
1243
1244				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1245					mux {
1246						groups = "i2c_ao_sda_9";
1247						function = "i2c_ao";
1248					};
1249				};
1250
1251				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1252					mux {
1253						groups = "i2c_ao_sda_11";
1254						function = "i2c_ao";
1255					};
1256				};
1257
1258				remote_input_ao_pins: remote_input_ao {
1259					mux {
1260						groups = "remote_input_ao";
1261						function = "remote_input_ao";
1262					};
1263				};
1264
1265				uart_ao_a_pins: uart_ao_a {
1266					mux {
1267						groups = "uart_ao_tx_a",
1268							"uart_ao_rx_a";
1269						function = "uart_ao_a";
1270					};
1271				};
1272
1273				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1274					mux {
1275						groups = "uart_ao_cts_a",
1276							"uart_ao_rts_a";
1277						function = "uart_ao_a";
1278					};
1279				};
1280
1281				uart_ao_b_pins: uart_ao_b {
1282					mux {
1283						groups = "uart_ao_tx_b",
1284							"uart_ao_rx_b";
1285						function = "uart_ao_b";
1286					};
1287				};
1288
1289				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1290					mux {
1291						groups = "uart_ao_cts_b",
1292							"uart_ao_rts_b";
1293						function = "uart_ao_b";
1294					};
1295				};
1296			};
1297
1298			sec_AO: ao-secure@140 {
1299				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1300				reg = <0x0 0x140 0x0 0x140>;
1301				amlogic,has-chip-id;
1302			};
1303
1304			pwm_AO_ab: pwm@7000 {
1305				compatible = "amlogic,meson-axg-ao-pwm";
1306				reg = <0x0 0x07000 0x0 0x20>;
1307				#pwm-cells = <3>;
1308				status = "disabled";
1309			};
1310
1311			pwm_AO_cd: pwm@2000 {
1312				compatible = "amlogic,meson-axg-ao-pwm";
1313				reg = <0x0 0x02000  0x0 0x20>;
1314				#pwm-cells = <3>;
1315				status = "disabled";
1316			};
1317
1318			i2c_AO: i2c@5000 {
1319				compatible = "amlogic,meson-axg-i2c";
1320				reg = <0x0 0x05000 0x0 0x20>;
1321				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1322				clocks = <&clkc CLKID_AO_I2C>;
1323				#address-cells = <1>;
1324				#size-cells = <0>;
1325				status = "disabled";
1326			};
1327
1328			uart_AO: serial@3000 {
1329				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1330				reg = <0x0 0x3000 0x0 0x18>;
1331				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1332				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1333				clock-names = "xtal", "pclk", "baud";
1334				status = "disabled";
1335			};
1336
1337			uart_AO_B: serial@4000 {
1338				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1339				reg = <0x0 0x4000 0x0 0x18>;
1340				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1341				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1342				clock-names = "xtal", "pclk", "baud";
1343				status = "disabled";
1344			};
1345
1346			ir: ir@8000 {
1347				compatible = "amlogic,meson-gxbb-ir";
1348				reg = <0x0 0x8000 0x0 0x20>;
1349				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1350				status = "disabled";
1351			};
1352
1353			saradc: adc@9000 {
1354				compatible = "amlogic,meson-axg-saradc",
1355					"amlogic,meson-saradc";
1356				reg = <0x0 0x9000 0x0 0x38>;
1357				#io-channel-cells = <1>;
1358				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1359				clocks = <&xtal>,
1360					<&clkc_AO CLKID_AO_SAR_ADC>,
1361					<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1362					<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1363				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1364				status = "disabled";
1365			};
1366		};
1367	};
1368};
1369